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Eric Gidzinski & Akshansh Gupta 1

Project 3: Non-Pipelined Control Unit

The objective for this project was to create the control unit within a basic processor. The
control unit designed will be explained by going over the unit’s design process, components
created, what happens for each opcode along with what specific optimizations were incorporated
into the unit. We used Logism for the implementation of various circuits.

Basic Characteristics:
1) Word size of 16-bits
2) Memory address/data bus size of 16 bits
3) Byte addressable memory
4) 64K byte main memory
5) 16-bit program status word (PSW) with status bits Z and N
6) 16 opcode instructions
7) 8 16-bit general purpose registers
8) 16-bit program counter
9) 16-bit countdown timer
10) 2’s complement number representation

Instruction Format (Figure 1):

Figure 1: Instruction set format

Rd/Rs1/Rs2: Specify one of the general purpose registers

S: Controls the setting of the condition codes
Shift bits: Cause the Rs2 register value to be left shifted by the corresponding value (0, 1, 2, or 3)

GPR[]/MM[]: Register contents/memory contents.
IR.S: Determines if the execution of the instruction should set the condition code (0 or 1). The
condition code bit (N and Z) should be set based on the value resulting from the operation.
Short Offset and Long Offset are sign extended with logical left shift and arithmetic right shift.
Left shifted(GPR[Rs2],IR.Shift)3−0 denotes the low order 4 bits of the operand value.
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Figure 2 displays various instructions along with their conditions:

Figure 2: Instruction set format

1) Program Check Violation
a) User mode (PSW privileged bit (P) not set): First 14 instructions can be executed
b) Privileged mode: All 16 instructions can be executed
c) Program check violation: Attempting to execute a privileged instruction when in
user mode
d) Swap PC→ MM[0] = PSW; MM[2] = PC; PSW = MM[4]; PC = MM[6]
2) Timeout
a) When the internal state bit is set and the control unit is at an instruction boundary
b) Modify PC→ MM[8] = PSW; MM[10] = PC; PSW = MM[12]; PC = MM[14]
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Figure 3 displays our approach to the circuit design through a state table:
State Condition Executed Next State (Decode D​4​D​3​D​2​D​1​D​0​)

F E​1​-E​15​, D​3​, Clock Pause 0 0 0 0 0

D​0 F 0 0 0 0 1

E​0 D​0​ for Op​0 0 0 0 1 0

E​1 D​0​ for Op​1 0 0 0 1 1

E​2 D​0​ for Op​2 0 0 1 0 0

E​3 D​0​ for Op​3 0 0 1 0 1

E​4 D​0​ for Op​4 0 0 1 1 0

E​5 D​0​ for Op​5 0 0 1 1 1

D​1 F 0 1 0 0 0

E​6 D​1​ for Op​6 0 1 0 0 1

E​7 D​1​ for Op​7 0 1 0 1 0

E​8 D​1​ for Op​8 0 1 0 1 1

E​12 D​1​ for Op​12 0 1 1 0 0

D​2 F 0 1 1 0 1

E​13 D​2​ for Op​13 0 1 1 1 0

D​3 F 0 1 1 1 1

E​9 D​3​ for Op​9 for

​ CC.N = 1 1 0 0 0 0

E​10 D​3​ for Op​10 ​for CC.Z = 1 1 0 0 0 1

E​11 D​3​ for Op​11 1 0 0 1 0

E​14 D​3​ for Op​14 for

​ PSW.P = 1 1 0 0 1 1

E​15 D​3​ for Op​15 for

​ PSW.P = 1 1 0 1 0 0

Clock pause If PSW.P = 0 for PSW.S = 1 (F ≠ 14 || 1 0 1 0 1


Violation D​3​ for PSW.P = 0 (Op​14​ & Op​15​) 1 0 1 1 0

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Figure 3: State Table

Figure 4 displays the state machine diagram along with the decode explanation:
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Figure 4: State Machine Diagram


I. 16-Bit Arithmetic Logic Unit (ALU)

The ALU connection layout is given in Figure 5.

Figure 5: ALU Connection Layout

The interior layout of the ALU is provided in Figure 6.

Figure 6: ALU Interior Circuit Layout

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The ALU (Arithmetic Logic Unit) created has 10 built-in functions. In order to select one
of these functions, the 4-bit selector pins must be used. The 4-bit number that corresponds to
each function is displayed in Figure 7.

Input Output Notes

S​3 S​2 S​1 S​0 Function

0 0 0 0 Add

0 0 0 1 AND

0 0 1 0 OR

0 0 1 1 NOT Uses left input

0 1 0 0 Subtract

0 1 0 1 Pass Left

0 1 1 0 Pass Right

0 1 1 1 Shift Left Put IR.Shift into Y register

1 0 0 0 Shift Right Put IR.Shift into Y register

1 0 0 1 Increment Increments left input

1 0 1 0 N/A

1 0 1 1 N/A

1 1 0 0 N/A

1 1 0 1 N/A

1 1 1 0 N/A

1 1 1 1 N/A
Figure 7: ALU Function Output Truth Table

All 10 functions in the ALU can be explained through their implementations. Starting
with the adder/subtractor circuit, an array of 1-bit full adders was used. The carry out of the
previous adder feeds into the carry in of the current adder, thereby creating a circuit capable of
adding 16-bit values. To make the circuit capable of adding or subtracting, the 3rd bit in the
select input XORs with each bit of the right input. The XOR gate is necessary because it allows
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the right input signal to be converted to its 2’s complement form, which can be added with the
left input to subtract the two numbers.
The logical AND circuit was implemented by putting each corresponding bit in the left
and right input into and AND gate. The logical OR circuit works the same way with the
exception of an OR gate instead of an AND gate. The logical NOT function inverts each bit of
the left input via NOT gates. The pass left and right functions output the left and right inputs

A segment of the logical left shift circuit is given in Figure 8:

Figure 8: Logical Left Shift Circuitry

As shown in Figure 8, an array of 16 1-bit shifts were created, where the LSB has a right
input bit of 0. This difference is because logical shift left means that the input is shifted left,
clipping the MSB, and setting the LSB to 0. To accommodate the requirements, an array of 4 of
these 16-bit shifters were created. The top inputs of Figure 8 decide how many times the inputted
signal gets shifted. In order for the circuit to correctly fulfill opcode 3’s requirements, the lower
4 bits of the outputted signal are replaced with the right input’s lower 4 bits only if the left input
is shifted 4 times.
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The arithmetic shift right circuit segment is given in Figure 9:

Figure 9: Arithmetic Shift Right Circuitry

Arithmetic shift right is implemented similarly to the shift left circuit; however, the shift
right has an array of 16 1-bit right shifters. The MSB right shifter is different from the others in
that the left and right input of the 1-bit shifter is the MSB of the inputted signal. This change is
necessary because arithmetic right shifting requires the MSB of the shifted value to be the same
as the MSB of the inputted value. As with the logical shift left, the lower 4 bits of the right
inputted signal replace the lower 4 bits of the outputted signal only if the inputted signal is
shifted 4 times. This requirement is necessary for opcode 4.

II. 16-bit Register

As given in the control unit requirements, a 16-bit register had to be designed. The
connection pins of the register are given in Figure 10.

Figure 10: 16-Bit Register Connection Layout

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The internal circuitry of the register is given in Figure 11.

Figure 11: 16-Bit Register Interior Circuitry

As shown in Figure X+1, D-latches (when enable input is on, signal goes directly from
input D to output Q) were used to store each bit in the register. The d-latch was selected because
it needs only 1 bit of input (unlike SR latches). This circuit was tested using Logisim.
Test Cases:
1) Input data when both enable and clock were off. Register did not save the data. Test passed.
2) Clock was activated. Register did not save the data. Test passed.
3) Enable bit was activated. Register saved the data.
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III. 16-bit General Purpose Register

The control unit was required to have 8 general purpose registers than could be read and
written. These registers were compacted into a singular circuit. The connection pins for this
circuit is given in Figure 12.

Figure 12: GPR Register Control Connection Layout

A segment of the internal circuitry is given in Figure 13.

Figure 13: GPR Register Control Internal Circuitry

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Figure 13 shows the main part of the GPR Register Control circuit. The wires that
continue below the figure lead to the remaining 6 registers. The circuit has a 16-bit input that
allows for a 16-bit value to be stored in the register. There is a 3-bit selector input that allows for
choosing which of the 8 registers to read/ write to. This function was implemented using a 3x8
decoder. The decoder was used because it allows for a 3-bit input to activate only 1 of 8 outputs.
The selector pins also feed into a 1-8 demultiplexer. The demultiplexer was used because it
allows for the 16-bit input to be correctly channeled to the selected register. Another input is the
1-bit read input; if the read input is activated, the circuit will output the current value stored on
the currently selected register. The clock input allows for the circuit to follow the control unit’s
clock cycles. Incrementing of the program counter is done through the increment function
implemented in the ALU.
Of the 8 registers, there are 2 specially reserved registers.
- Register 0: To hold a 16-bit value of 0 regardless of what is inputted to the
- Register 7: The control unit’s program counter.
The GPR Register Control circuit has 1 output. This 16-bit output is capable of reading
the output of the currently selected register. This function was implemented using a 8-1
multiplexer, which has an an enable bit and a 3-bit selector. The selector input comes from the
inputted register selector. The enable bit comes from the read input; by including an enable bit to
the multiplexer, the GPR Register Control will only output a value if the control unit needs to
read a register.

IV. Random Access Memory (RAM)

Rather than design a RAM module, the prebuilt module provided by Logisim was used.
The connection layout of the RAM module is given in Figure 14.

Figure 14: RAM Connection Layout

The RAM module used is capable of storing 64 kB of information, as required for the
control unit. Interacting with the RAM module requires at minimum an address and clock input.
The address input for this project is 16-bits wide and feeds into the “A” input shown in Figure
14. The address input points at the decimal value equivalent address spot in memory. The clock
input is the “/\” input at the bottom of the RAM module. The “D” output is 16-bits in width and
outputs the value stored at the currently selected spot.
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V. Read Only Memory (ROM)

Like the RAM module, the Logisim ROM module was used instead of designing one.
The connection layout of the ROM module is given in Figure 15.

Figure 15: ROM Connection Layout

The ROM module used in the project has the capability to store 8 different values. The
ROM requires 1 input for this lab. The address input “A” on the left side is a 3-bit input. The
address chooses which of 8 stored constants in the ROM to output. For this lab, 0, 2, 4, 6, 8, 10,
12, and 14 were stored because these values would be needed throughout the project. The output
“D” is 16-bits and is the binary equivalent of the value at the selected address.

VI. 16-Bit Countdown Timer

For this lab, a countdown timer did not have to be implemented. In its place, a 16-bit
register was used in its place. The connection layout of the timer is given in Figure 16.

Figure 16: Timer Connection Layout

The objective of the timer is to countdown by 1-bit every time an instruction is

completed. An internal circuit in the timer counts down its current value. The timer links up the
control unit clock, allowing for the timer to count in sync with the rest of the unit. The input of
the circuit allows for the internal countdown circuit to tick the timer every time an instruction is
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completed. The one output of the timer is a signal that outputs only when the counter reaches 0.
When this occurs, and internal state bit is activated, which is outputted by the timer. This state bit
then causes the Timeout violation to occur. To deactivate the internal state bit, opcode 15, which
changes the clock, must be occur.

Control Signals

Using Figures 2 and 3, the control signals for each opcode was determined. The control
signals for the opcodes and violations are included in Figure 17.


Fetch 1. GPR[R7]​​OUT​, ALU/ Increment,

MAR​IN​, Z​IN​, Read_mm


D​0​ - Opcodes 0, 1, 2, 3, 4, 5 1. GPR[IR.Rs1]​out​, Tmp1​in

2. IR.Shift​out​, Y​in
3. GPR[IR.Rs2]​out​, ALU/shift_left​by_left​,
4. Z​out​,​ ​Tmp2​in

D​1​ - Opcodes 6, 7, 8, 12 1. PC​out​, Y​in

2. IR.Short_Offset​out​, ALU/Add, Z​in
3. Z​out​, Tmp1​in

D​2​ - Opcode 13 1. GPR[IR.Rd]​out​, Y​in

2. IR.Short_Offset​out​, ALU/Add, Z​in
3. Z​out​, Tmp1​in

D​3​ - Opcode 9, 10, 11, 14, 15 1. PC​out​, Y​in

2. IR.Long_Offset​out​, ALU/Add, Z​in
3. Z​out​, Tmp1​In


ADD Opcode = 0000 1. Tmp1​out​, Y​in

2. Tmp2​out​, ALU/Add, Z​in
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3. Z​out,​GPR[IR.Rd]​in

SUB Opcode = 0001 1. Tmp1​out​, Y​in

2. Tmp2​out​, ALU/Sub, Z​in
3. Z​out,​GPR[IR.Rd]​in

AND Opcode = 0010 1. Tmp1​out​, Y​in

2. Tmp2​out​, ALU/And, Z​in
3. Z​out,​GPR[IR.Rd]​in

SHL Opcode = 0011 1. Tmp1​out​, Y​in

2. Tmp2​out​, ALU/Shift_left, Z​in
3. Z​out,​GPR[IR.Rd]​in

SHRA Opcode = 0100 1. Tmp1​out​, Y​in

2. Tmp2​out​, ALU/Shift_right, Z​in
3. Z​out,​GPR[IR.Rd]​in

OR Opcode = 0101 1. Tmp1​out​, Y​in

2. Tmp2​out​, ALU/Or, Z​in
3. Z​out,​GPR[IR.Rd]​in

NOT Opcode = 0110 1. Tmp1​out​, ALU/Not, Z​in

2. Z​out,​GPR[IR.Rd]​in

LD Opcode = 0111 1. Tmp1​out​, GPR[IR.Rd]​in

ST Opcode = 1000 1. Set MAR to Tmp2,​ MDR​

​ In​, Tmp1​out​,
3. GPR[IR.Rd]​out

BRN Opcode = 1001 PSW.N = 1 1. Tmp1​out​, Y​in

2. Tmp2​out​, ALU/Add, Z​in
3. Z​out​, PC​in

BRZ Opcode = 1010 PSW.Z = 1 1. Tmp1​out​, Y​in

2. Tmp2​out​, ALU/Add, Z​in
3. Z​out​, PC​in

BR Opcode = 1011 1. Tmp1​out​, Y​in

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2. Tmp2​out​, ALU/Add, Z​in

3. Z​out​, PC​in

JSR Opcode = 1100 1. PC​out​, GPR[IR.Rd]​IN

2. Tmp1​out, PC​
​ In​,

RTS Opcode = 1101 1. Tmp1​out​, PC​In

CLK Opcode = 1110 PSW.P = 1 1. Tmp1​out, MAR​

​ IN, Read_mm

3. MDR​OUT​, ​Timer​IN

LPSW Opcode = 1111 PSW.P = 1 1. Tmp1​out​, PSW​in

Timeout (Timer Interrupt) PSW.P = 0 Internal 1. PSW​OUT​, MDR​IN

State Bit = 1 2. ROM[8]​OUT​, MAR​IN​, Write_mm
4. GPR[R7]​OUT, MDR​
​ IN​
5. ROM[10]​OUT​, MAR​IN​, Write_mm
7. ROM[12]​OUT​, MAR​IN​, Read_mm
10. ROM[14]​OUT​, MAR​IN​, Read_mm
11. WMFC
12. MDR​OUT​,​ GPR[R7]​IN

Program Check Violation Opcode = 0000 - 1. ROM[0]​OUT​, MAR​IN​,

1101 PSW.P = 0 2. PSW​OUT​, MDR​IN​, Write_mm
4. ROM[2]​OUT​, MAR​IN​,
5. GPR[R7]​OUT​, MDR​IN​, Write_mm
7. ROM[4]​OUT​, MAR​IN​, Read_mm
10. ROM[6]​OUT​, MAR​IN​, Read_mm
11. WMFC
12. MDR​OUT​, GPR[R7]​IN

Figure 17: Control Unit Control Signals

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Control Signal Sequential Circuit

Each opcode implementation can be presented using a sequential circuit. This section of
the report will go over the creation of the sequential circuit for opcode 0. The sequential circuits
for the other opcodes and violations can be found in the ​Appendix​. For these sequential circuits,
the flip flops were chosen to be D flip flops. Each number in the control signals in Figure 17 can
then be considered as a unique flip flop in the circuit.

I. Fetch

Since the fetch state is common with all opcodes and violations, the fetch segment of the
sequential circuit can be used for all future sequential circuits. Using the control signals in Figure
17, the sequential circuit for Fetch is included in Figure 18.

Figure 18: Fetch Sequential Circuit

II. Decode

The fetch segment of the circuit then feeds into the decode 0 segment of the circuit. The
decode segments of the sequential circuits are control signals common among multiple opcodes.
For example, the D0 decode is common among opcodes 0 through 5. By creating D0, the
opcodes could share a common decode and reduce the size of the control unit. The sequential
circuit for the decode part of the opcode 0 circuit is given in Figure 19.
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Figure 19: Decode Sequential Circuit

III. Execute

The execute phase of the sequential circuits are where the opcode circuit differentiate
themselves from one another. The execute phase of the opcode 0 sequential circuit is given in
Figure 20.

Figure 20: Execute Sequential Circuit

Final Control Unit Circuit

With the needed sequential circuits explained along with its accompanying necessary
components, the final control unit circuit can be created. The circuit diagram will be split into 3
parts, with the right side of the current page connecting to the left of the next page, and the right
of the next page connecting to the left of the page after next. Some overlap was made for easier
connecting between the pages. With that in mind, the Control Unit circuit diagram is in Figure
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Figure 21: Control Unit Circuit Diagram

The circuit uses tristate buffers to control what data is loaded onto the bus. The signals
outputted by the sequential circuits activates and deactivates these buffers. A dummy circuit,
called “OPCODE Sequential Circuits” in Figure 21, is used in place of where the sequential
circuits for the opcodes and violations reside. Selecting which opcode sequential circuit will be
used is done via a decoder. The selector for the decoder would be IR.Opcode. The violation
sequential circuits would be activated depending on if their needed conditions are met while the
opcode circuits are in use. The tristate buffer control bits as well as the ALU, ROM, and GPR
Register Control selection bits are also close to the sequential circuits for easy wiring.
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During the design of the circuit, several optimizations to the design were implemented.

1) Ripple Carry Adder in the ALU + Increment

In the ALU circuit, a ripple carry adder was created with an array of 1-bit full adders
instead of 1-bit half adders. The full adder was used because it reduces the circuitry needed to
implement a 16-bit adder/ subtractor because additional gates would be needed for the half
adders to have carry in and out values, which are necessary for adding values greater than 1 bit.
Furthermore, we used the ripple carry adder to implement the increment function. Implementing
the increment function is given in Figure 22.

Figure 22: Increment Circuit Diagram

The increment function uses a 2-1 multiplexer. Each right input’s bit is put into the 0
input of the multiplexer. The other input contains a constant 0 for all bits except the LSB of the
right input, which has a constant 1. The selector bit is the MSB of the ALU selector input
because that bit differentiates increment from the add/subtract function outputs. As a result,
when the increment function is selected, the multiplexer bypasses the right input and adds 1 to
the left input. By incorporating this function into the adder circuit, the area consumed by the
ALU is reduced.

2) Splitting into Decodes

If one were to look at the control signals in Figure 17, it can be seen that signals common
among multiple opcodes or violations were grouped into multiple decode states. This grouping
allows for less flip flops and control signal outputs in the circuit, therefore reducing the cost and
space used by the control unit.

3) Tri State Buffer Grouping

The tristate buffer activator inputs as well as selector inputs for the ALU, ROM, and
register control were grouped up and labeled next to the dummy sequential circuit. This grouping
of inputs makes for easy connecting of the sequential circuits to the control unit.
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The following circuit diagrams are for the opcodes and violations sequential circuits.
Please note that after opcode 0, the input of the first Fetch flip flop is not shown to be the
AND’ing of all of the Q’ signals of the flip flops. This was done to simplify the design along
with easier user interpretation.
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Figure 23: Opcode 0 Sequential Circuit

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Figure 24: Opcode 1 Sequential Circuit

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Figure 25: Opcode 2 Sequential Circuit

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Figure 26: Opcode 3 Sequential Circuit

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Figure 27: Opcode 4 Sequential Circuit

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Figure 28: Opcode 5 Sequential Circuit

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Figure 29: Opcode 6 Sequential Circuit

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Figure 30: Opcode 7 Sequential Circuit

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Figure 31: Opcode 8 Sequential Circuit

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Figure 32: Opcode 9 Sequential Circuit

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Figure 33: Opcode 10 Sequential Circuit

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Figure 34: Opcode 11 Sequential Circuit

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Figure 35: Opcode 12 Sequential Circuit

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Figure 36: Opcode 13 Sequential Circuit

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Figure 37: Opcode 14 Sequential Circuit

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Figure 38: Opcode 15 Sequential Circuit

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Figure 39: Program Check Violation Sequential Circuit

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Figure 40: Timeout Violation Sequential Circuit