EE5320 ANALOG IC DESIGN

ASSIGNMENT - 3

SURE AVINASH
(EE17M046)
1) A) Vth vs L
NMOS

PMOS
B) Vgs – Vth vs Vov
NMOS
PMOS
C) gm vs Vov
NMOS
PMOS
D) gm/Id vs Vov
NMOS
W = 0.24u

W = 2u
W = 10u

PMOS
W = 0.24u
W = 2u

W = 10u
E) fT vs Vov
NMOS
PMOS
F) rds vs Vds
NMOS
PMOS
G) gm*rds vs Vds
NMOS
PMOS
2)

Design a single-stage two-transistor (excluding bias transistors) common-source amplifier with

a DC gain of Av = 50V/V, unity gain bandwidth of 200MHz, and an output swing of 600mV
(amplitude) with minimum power. Assume supply voltage of 1.8V and a load capacitance of
10pF.

AC anlaysis Results
Voltage Gain = 65.34 V/V
Unity Gain Frequency = 202MHz

Voltage swing > 600mV

3) Design a single-stage two-transistor (excluding bias transistors) source follower that level
shifts-up the input by 0.8V with a DC gain of Av > 0.9V/V and -3dB bandwidth of 2GHz with
minimum power. Assume supply voltage of 1.8V and a load capacitance of 10pF.

Schematic

Gain = 0.904V/V
3db Bandwidth = 2.07GHz
AC Analysis Results

Output when a pulse of 500mV is applied.

Time taken for Settling is 450.9ps.