1

Depletion and Enhancement Mode MOSFET Design

Using Germanium and Aluminum Oxide
Final Report
ELE 335 Fall 2015
Group #3

Alexander Freeland (Z1663158), Nathan Freitag (Z1694640), Nathan Glatz (Z1719368),

Andrew Hanley (Z1671016), Tyler Hathaway (Z1722405)
Northern Illinois University
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Table of Contents
Executive Summary……………………………………………………………………………………………………………...3
A. MOSFET Design Overview................................................................................................................................................ 3
B. Materials and Values (Calculated and Assumed) ............................................................................................................... 3
C. Spice and Final Results ....................................................................................................................................................... 3
I. Introduction .............................................................................................................................................................................. 4
A. Background of the MOSFET .............................................................................................................................................. 4
B. Benefits of Designing a Custom MOSFET......................................................................................................................... 4
C. Overview of the Design Steps ............................................................................................................................................ 4
II. Design ....................................................................................................................................................................................... 5
A. Fabrication Materials and Values ....................................................................................................................................... 5
B. Enhancement and Depletion Fabrication Process ............................................................................................................... 5
III. Analysis................................................................................................................................................................................... 7
A. MOSFET Analysis Using Spice ......................................................................................................................................... 7
B. AC Amplifier ...................................................................................................................................................................... 8
C. DCFL Inverter .................................................................................................................................................................... 9
IV. Conclusions ............................................................................................................................................................................. 9
V. Acknowledgment ................................................................................................................................................................... 10
VI. References ............................................................................................................................................................................. 10
Appendix I - Mathcad ................................................................................................................................................................ 11
A. Enhancement Mode Calculations ..................................................................................................................................... 11
B. Depletion Mode Calculations ........................................................................................................................................... 13
Appendix II – Mathcad IV Characteristics.............................................................................................................................. 14
A. Enhancement I-V Characteristics ..................................................................................................................................... 14
B. Depletion I-V Characteristics ........................................................................................................................................... 15
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Executive Summary
The overall design presented contains a digital inverter and an amplifier. The amplifier and inverter
contain n-MOSFETs that were designed in order to meet the criteria set for ideal operation. In order for the
inverter and amplifier to function properly, the following parameters were set and were followed throughout
the design as follows: For the Enhancement mode n-MOSFET, there is a drain current (𝐼𝐷𝑆 ) of 10mA in the
saturation region at a gate-source voltage (𝑉𝐺𝑆 ) of 5V. The threshold voltage (𝑉𝑇 ) is set to 1V as well. In
addition to the Enhancement mode n-MOSFET, a Depletion mode n-MOSFET was also designed with the
pre-proclaimed drain current of 2.5mA in the saturation region at a gate-source voltage of 0.0V. In order for
the circuit to perform with precision, a threshold voltage of -4V was also chosen.

As for the fabrication of the MOSFETs, the substrate and gate oxide to be used in the build are Germanium
and Aluminum Oxide (𝐴𝑙2 𝑂3 ) respectively. Outside of the given values, the rest of the parameters were
strategically selected to optimize the design’s performance. The parameters that were chosen were the channel
length, the doping of the enhancement and depletion modes, and the metal to be deposited on the gate, source,
and drain. The channel length was chosen to be 0.5𝜇m for both the enhancement and depletion modes. For
the doping of the emitter, a value of 1.1x1016 𝑐𝑚−3 was chosen, and for the depletion, a value of
0.576x1017 𝑐𝑚−3 was chosen. The doping values were chosen carefully in order to keep the device realistic
to produce while also being cost efficient. The logic for the increased doping from the enhancement to
depletion mode is to maintain the same gate oxide thickness between the two modes to simplify the fabrication
of the device. By choosing the values for the doping, the mobility was determined through examining mobility
𝑐𝑚2
and doping graphs, giving the mobility of the enhancement mode as 3100 𝑉∗𝑠 , and the mobility of the depletion
𝑐𝑚2
mode as 2950 𝑉∗𝑠 . Aluminum, a very common metal to use for depositing on semiconductors, was chosen as
the metal to be deposited on the drain, source, and gate for this design. Aluminum also gave a work function
value of 4.28V that worked well with the desired threshold values of 1V and -4V. Choosing these values and
properties resulted in a gate oxide thickness (d) of 0.259𝜇m and a device width (Z) of 6.026𝜇m in the
enhancement mode. As for the depletion mode, the device width (Z) comes out to be 1.583𝜇m, which is
approximately one fourth of the value of the device width in the enhancement mode. The fabrication of the
devices was illustrated in Solid Works. The steps of the fabrication include: preparing the substrate, adding a
thermal oxidation layer of Aluminum Oxide, photogravure which is photo etching a window in the gate oxide,
diffusion of the drain and source, and finally depositing the Aluminum metal on the drain, source, and gate.
The only difference in the fabrication process between the two modes is the depletion mode has an extra step
after the deposit of the Aluminum metal, leading to the n-Channel depletion region formation.

Once the device was fabricated, simulations were run using B2 Spice Lite version. The simulations
ultimately resulted in the digital inverter and amplifier circuits functioning with optimum efficiency for the
desired design. In order to achieve optimization, preliminary parameters were needed including I-V
characteristics and various internal parameters of the enhanced and depletion MOSFETs. Specifically, the
amplifier gave a calculated gain of 3.75. The inverter successfully inverted a pulse signal with minimal change
to the amplitude. Operation points were chosen in order to prevent clipping. The biasing was achieved using
voltage sources to create a DC offset. Through successive simulations, the inverter and amplifier circuits were
obtained and function extremely efficiently. Analyzing the spice models and the meticulous selection of
parameters and materials demonstrates that the desired results were achieved.

Depletion and Enhancement Mode MOSFET Design
Using Germanium and Aluminum Oxide
Alexander Freeland (Z1663158), Nathan Freitag (Z1694640), Nathan Glatz (Z1719368),
Andrew Hanley (Z1671016), Tyler Hathaway (Z1722405)
Northern Illinois University
Abstract- The content of this paper deals with the design
and fabrication of n-MOSFETs operating in the
enhancement and depletion modes. These MOSFETs are
implemented into digital inverter and amplifier circuits and
contain parameters designed specifically for this
application. The overall design has a high efficiency and is
capable of being put into production.
I. INTRODUCTION
A. Background of the MOSFET
The metal-oxide semiconductor field-effect transistor
(MOSFET) is made up of an MOS capacitor and two p-n
junctions placed immediately adjacent to the MOS capacitor
[1]. The MOSFET has two different designs, enhancement
and depletion. The difference between the enhancement
MOSFET and depletion MOSFET has to do with the voltage
applied to the gate. The n-channel MOSFET in this design is
enhanced when a positive voltage is applied to the gate.
Similarly, applying a negative voltage to the gate depletes the
carriers in the channel, resulting in the depletion n-channel
MOSFET. If instead a large positive voltage is applied to the
gate, a surface inversion layer is formed. While designing a
MOSFET, one of the most important parameters to consider
is the threshold voltage. The threshold voltage can be
calculated using the following equations depending on
whether the MOSFET is in the enhancement or depletion
mode.
Enhancement Mode:
√2𝜀𝑠 𝑞𝑁𝐴 ∗ 2𝜑𝐵
𝑉𝑇 = 𝑉𝐹𝐵 + 2𝜑𝐵 +
𝐶0
Depletion Mode:
√2𝜀𝑠 𝑞𝑁𝐴 ∗ 2𝜑𝐵
𝑉𝑇 = 𝑉𝐹𝐵 − 2𝜑𝐵 −
𝐶0
Where 𝜑𝐵 is the energy difference between Ef and Ei, 𝜀𝑠 is
the semiconductor permeability, 𝐶0 is the capacitance of the
oxide layer, and 𝑉𝐹𝐵 is flat band voltage.
B. Benefits of Designing a Custom MOSFET
Some of the benefits of MOSFETs are that they consume
a low amount of power and have a high manufacturing yield
[1]. Additionally, there is a high success rate when producing
the MOSFETs for companies and the power that the
MOSFET uses is minimal. The MOSFET is controlled by a
4
voltage and prevents thermal runaway. It also has a much
lower on-state loss than its predecessor, the bipolar transistor
[12]. By designing a custom MOSFET, the size and internal
parameters can be controlled to ensure the cost is minimized.
Also, designing a custom MOSFET allows the doping to be
selected which is an extremely important value to set in order
to have a similar fabrication process between the
enhancement and depletion modes.
C. Overview of the Design Steps
In order to understand the ideal operation of the MOS
Capacitor and MOSFET, chapter five of Semiconductor
Devices: Physics and Technology [1] was examined.
Successively, example design problems of MOSFET’s were
analyzed to further the understanding of the device. Once
there was a sufficient understanding of the ideal parameters
necessary for a Germanium substrate and Aluminum Oxide
gate oxide, research was performed to understand similar
MOSFET designs to acquire the values needed for this
application. Using the application Mathcad, the research was
mathematically organized and parameter values were
calculated. The calculations made use of the equations
presented throughout the chapter such as the threshold
voltage equation and saturation current equation [1]. Through
the manipulation of these two equations, the gate oxide
thickness and width of the device were obtained. Some of the
other equations used to complete the design were the flat-
band voltage equation and work function difference equation,
which were found from the same resource. Keeping in mind
the material specified for this design, realistic parameters
were concluded through research from various sources [2] [3]
[4] [5]. Next, various values were tested to obtain the design
with the best performance. The channel length and gate oxide
thickness were concluded to have the same values for both
the depletion mode and the enhancement mode. Device width
in the depletion was discovered to be one-fourth that of the
enhancement device. Through the use of Solid Works and B2
Spice Lite Version, fabrication and analysis were performed.
This process resulted in a fully operational amplifier and
inverter while maintaining a reasonable production cost.
II. DESIGN
A. Fabrication Materials and Values
The first portion of our design included making an
enhancement mode MOSFET using Germanium (Ge) and

Aluminum Oxide (𝐴𝑙2 𝑂3 ). The design specifications
required the device to provide 𝐼𝐷𝑆 = 10mA in the saturation
region at 𝐼𝐺𝑆 = 5V and a threshold voltage of 1V (𝑉𝑇 = 1V).
These values are the exact values produced and verified
through simulation. We will assume the smallest conceivable
n-channel to be 0.5𝜇m in order get the fastest possible
switching speed for the MOSFET. The doping value chosen
was Na = 1.1x1016 𝑐𝑚−3 . This falls within the range of
reasonable values given in a Semiconductor Devices
textbook by Prof. Jasprit Singh [11]. This source also gave
respectable work function values for the Aluminum
deposited on the source, gate, and drain. Prof. Jasprit Singh’s
textbook also contributed the electron affinity value for
Germanium, which was equal to 4.13V. In comparison to
several other sources, this value for the electron affinity was
deemed an acceptable value. Constants such as the
temperature, dielectric constant, and intrinsic carrier
concentration were acquired from Semiconductor Devices:
Physics and Technology by S.M. Sze and M.K. Lee [1].
Additionally, S.M. Sze and M.K. Lee’s textbook also
contributed the equations necessary to calculate the threshold
voltage, capacitance of the oxide layer, and saturation
current. Through various manipulations of the equations
discovered in this textbook, practical values for the gate oxide
thickness and the device width were determined. While
calculating the device width, the mobility of Germanium--
given our doping--was concluded using the figure below.
Fig. 1 Mobility vs. Impurity Concentration for Germanium
For simplification of the fabrication process, the
enhancement and depletion modes were designed to have the
same value for the oxide thickness. The drain current for the
depletion mode is specified to be 2.5mA in the saturation
5
region with a gate to source voltage of 0V. For this design,
the threshold voltage was chosen to be -4V to correctly
manipulate our gate oxide thickness and match our desired
saturation current of 2.5mA. In comparison to the doping of
the enhancement mode, the depletion mode doping was
increased to a value of 0.576x1017 𝑐𝑚−3 in order to achieve
the same capacitance in the oxide layer. By obtaining the
same value for the capacitance in the oxide layer combined
with the increased doping, the same gate oxide thickness as
the enhancement mode is ultimately achieved. For the
depletion mode, reasonable values for the doping and
mobility were determined through comparisons with
examples in Solid State Electronic Devices by Ben Streetman
and Sanjay Banerjee [8]. It was also found that while in the
depletion mode, the device width is approximately one fourth
of the value of the device width in
the enhancement mode.
B. Enhancement and Depletion Fabrication Process
For the fabrication of the MOSFET, enhancement and
depletion, many steps of the fabrication process are fairly
similar. In order to fabricate the enhancement mode, five
steps were taken. The first step in the process is the
preparation of the substrate, which is a solid block of
germanium. The substrate has a length of 2.5𝜇m and a width
of 6.026𝜇m. Next in the process, thermal oxidation occurs
which is then followed by photogravure where a window of
the gate oxide is removed by photo etching. The fourth step
of the process involves the diffusion of the drain and source,
and the fabrication is completed through an Aluminum
deposit on the drain, source, and gate for our design. While
dealing with the depletion mode, as mentioned previously
many of the steps remain the same. There are however
significant differences such as the device width being
changed to 1.583𝜇m. The substrate is prepared, thermal
oxidation occurs, and then the photogravure where the
window is removed by photo etching occurs. This is then
similarly followed by the diffusion of the drain and source
with Aluminum being deposited on the drain, source, and
gate as before. The main difference in the fabrication of the
depletion mode is the sixth step where the n-channel
depletion occurs. These two processes can be seen in the
figures below.
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Fig 2. Enhancement n-channel MOSFET fabrication process

Fig. 3 Depletion n-channel MOSFET fabrication process

The result of the fabrication steps provides the results in the figures below. The gate oxide thickness (d) is 0.259𝜇m and the channel
length (L) is 0.5𝜇m for both the enhancement and depletion modes. Per the figures, the drain metal, substrate, deposited metal, and
gate oxide can be observed to be Aluminum, Germanium, Aluminum, and Aluminum Oxide respectively. While in the enhancement
mode there is no depletion region, a depletion region can be observed in the second figure, which shows the depletion mode.

Fig. 4 Enhancement n-channel MOSFET (normally off) Fig. 5 Depletion n-channel MOSFET (normally on)

V. ANALYSIS A. MOSFET Analysis Using Spice

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In order to show that the MOSFETs designs were valid, There are additional parameters that could be calculated and
we preformed Spice simulations. The version of simulator added but for the purpose of this study these values give
that we used was B2Spice Lite version. Two circuits were sufficient accuracy. The values for l and w correspond to l
designed in order to test the MOSFETs capabilities. The first and z in our Mathcad analysis. The other values are
is a MOSFET small signal amplifier and the second is an calculated. They are found to be 𝑎𝑑 = 𝑎𝑠 = 2 ∗ 𝑙 ∗ 𝑧, 𝑝𝑑 =
inverter. These circuits show the use of our designed 2∗𝑙
𝑝𝑠 = 4 ∗ 𝑙 + 2 ∗ 𝑧, and 𝑛𝑟𝑑 = 𝑛𝑟𝑠 = . These values are
MOSFETs in a practical setting. To implement the designs, 𝑧
entered into the MOSFET properties window in B2 Spice
we first need to find the I-V characteristics of our
along with the other values from the table.
enhancement and depletion mode MOSFET designs. This
will allow us to choose an appropriate operating point that
prevents clipping or distortion and verifies that the MOSFET
operates in the saturation region. The I-V characteristics are
governed by the following equation.
𝐾𝑝
𝐼𝐷 = (𝑉 − 𝑉𝑇 )2
2 𝐺
Here 𝐼𝐷 is the current going into the drain, 𝐾𝑃 is the
transconductance parameter of the MOSFET design, 𝑉𝐺 is the
gate voltage, and 𝑉𝑇 is the threshold voltage. All of these
values are the same ones that were calculated using Mathcad.
The transconductance parameter is found using the equation
below.
𝐾𝑝 = 𝜇𝑛 𝐶0

In order to make the generic MOSFET model in B2 spice into Fig. #6 I-V Characteristic circuit for enhancement mode MOSFET
one with the specifications of our MOSFET we need to set a
list of standard parameters [9]. These parameters and their We used two voltage sources (V1 for 𝑉𝐺𝑆 and V2 for 𝑉𝐷𝑆 ) and
values are given below for each of the two MOSFET designs. preformed a dual parameter DC sweep to get the I-V
We used the LEVEL 2, MOS2 model in both of our designs characteristic graphs. V2 is varied from 0V to 10V in 1V
[9]. increments (this generates the 10 different curves) while V1
is incremented from 0V to 15V in 0.1V increments (the
TABLE I smaller step is used to make the curves smooth). We then use
I-V CHARACTERISTICS FOR ENHANCEMENT MODE MOSFET
this graph to choose the appropriate operating point.
B2 Spice Parameter Name Calculated Units
symbol Value
l Channel length 0.5 𝜇m
w Channel width 6.026 𝜇m
as Source diffusion 6.026x10−12 𝑚2
area
ad Drain diffusion 6.026x10−12 𝑚2
area
ps Source junction 1.405x10−5 m
perimeter
pd Drain junction 1.405x10−5 m
perimeter
nrd # of squares of the 0.166 1
source diffusion 𝑚
nrs # of squares of the 0.166 1
drain diffusion 𝑚
temp Instance operating 30 °C
temperature
Fig. #7 I-V Characteristic graph for enhancement mode MOSFET
vto Threshold voltage 1 V
kp Transconductance 0.104 𝑚𝐴
parameter 𝑉2
From the graph we choose an operating point of 𝑉𝐺𝑆 = 4V: 𝐼𝐷
= 6mA for use later in the amplifier design. This is the
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amount that we will offset the small signal input for the
amplifier. For the inverter we chose an operating point of 3
volts. From the graph we can also see that the maximum
value for the current at 𝑉𝐺 = 10V is 𝐼𝐷 = 50mA. This agrees
with the equations graphed in Mathcad (Appendix II). The
load line shown is used to select the operating point. It
depends on the resistor value used in the circuit.
𝑉𝑚𝑎𝑥 𝑉𝐷𝑆
𝐼= −
𝑅 𝑅
Here R is the resistor connected to the drain. 𝑉𝑚𝑎𝑥 = 15V and
𝑉𝐷𝑆 varies with the DC sweep.
TABLE II
I-V CHARACTERISTICS FOR DEPLETION MODE MOSFET
B2 Spice Parameter Name Calculated Units Fig. #8 I-V Characteristic circuit for depletion mode MOSFET
symbol Value
l Channel length 0.5 𝜇m
w Channel width 1.583 𝜇m
as Source diffusion 1.583x10−12 𝑚2
area
ad Drain diffusion 1.583x10−12 𝑚2
area
ps Source junction 5.166x10−6 m
perimeter
pd Drain junction 5.166x10−6 m
perimeter
nrd # of squares of the 0.632 1
source diffusion 𝑚
nrs # of squares of the 0.632 1
drain diffusion 𝑚
temp Instance operating 30 °C
temperature
vto Threshold voltage -4 V
kp Transconductance 0.099 𝑚𝐴
parameter 𝑉2
Fig. #9 I-V Characteristic graph for depletion mode MOSFET

The values for the depletion mode are calculated using the Again like the enhancement mode the graphs match the
same equations as the enhancement mode. Notably, the value Mathcad results from Appendix II.
for w is approximately ¼ the value in the enhancement mode.
Also, the 𝑉𝑡𝑜 and 𝐾𝑃 are considerably different. Because the B. AC Amplifier
transconductance parameter is smaller, and since it is directly
proportional to the magnitude of the current in the I-V
characteristic plots, the max graph current will (at 10V) be
less than the max for the enhancement mode.

Fig. #10 I-V Amplifier circuit for depletion mode MOSFET


We use two voltage sources at the gate. V1 is the ac signal
and V2 is the DC bias to set the correct operating point. For
V1 the frequency is 1MHz and the amplitude is 0.3 volts (0.6
volts peak-to-peak). The two capacitors act as filters. The
resistor is what determines the load line. We can also see that
the operating point is reflected with the 4 volts DC offset
source and the 5.57mA current read on the ammeter. This
matches the I-V characteristic operating point that we chose.
Fig. #11 I-V Amplifier graph for depletion mode MOSFET showing
input and output waveforms
The input voltage is 0.6 volts peak-to-peak, just like we set.
Measuring the output gives a 𝑉𝑚𝑎𝑥 = 10.5 volts and 𝑉𝑚𝑖𝑛 =
8.25 volts. This gives an output peak-to-peak of 10.5 – 8.25
𝑉 2.25
= 2.25V. The gain is 𝑜𝑢𝑡 = = 3.75. This matches the value
𝑉𝑖𝑛 0.6
that we expect from looking at the IV characteristic plots.
C. DCFL Inverter
Fig. #12 I-V DCFL circuit – uses both depletion and enhancement mode
designs
9
This inverter design uses an operating point of 3 volts and
2.5mA. This gave an output that was changed minimally in
magnitude. The lower operating point is also needed because
the source voltage 𝑉𝐷𝐷 is only 5 volts for this design. The
depletion mode MOSFET has the gate and the source
connected in a “diode connected” arrangement - so called
because it acts like a diode.
Fig. #13 I-V DCFL Inverter graphs showing input and output
waveforms
This plot shows a 1ms pulse that is inverted using the
combination of enhancement mode and depletion mode
MOSFETs. All of these spice simulations allowed an
analytical study of the designs, proving that they performed
correctly and within tolerances.
VI. CONCLUSION
Through meticulous planning and research, it is
concluded that the presented design is suitable for the use of
a metal-oxide semiconductor field-effect transistor
(MOSFET) using the specified parameters. Between the
research, planning, and testing/simulating, the MOSFET
specifications of the given parameters were determined to
have a channel length (l) of 0.5𝜇m in both the enhancement
and depletion modes, gate oxide thickness (d) of 0.259𝜇m
also in both modes, an enhancement mode device width of
6.026𝜇m, a depletion mode device width of 1.583𝜇m, doping
of 1.1x1016 𝑐𝑚−3 in the enhancement mode, and a doping
slightly higher in the depletion mode of 5.76x1016 𝑐𝑚−3 .
Using B2 Spice Lite, Solid Works, and Mathcad 3.1 to design
and analyze the MOSFET parameters, there is conclusive
evidence that the designed MOSFETs function as expected
and are feasible to produce.
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VII. ACKNOWLEDGMENT
Martin Kocanda – Assisted in the design of the B2-spice
circuits
Ibrahim M. Abdel-Motaleb – Assisted in the design of the
B2-Spice circuits and the calculations for the specifications
of the MOSFETs
Michael J. Haji-Sheikh – Assisted with the calculations for
the specifications of the MOSFETs

VIII. REFERENCES
[1] S.M. Sze and M. K. Lee, “Semiconductor Devices: Physics and
Technology,” 3rd ed., pp. 187, Wiley, May 2012.
[2] Ioffe, “Basic parameters at 300 K of Geranium,” Retrieved from
http://www.ioffe.ru/SVA/NSM/Semicond/Ge/basic.html
[3] Ioffe, “Band Structure and Carrier Concentration of Geranium,”
Retrieved from
http://www.ioffe.ru/SVA/NSM/Semicond/Ge/bandstr.html
[4] Ioffe, “Electrical Properties of Geranium,” Retrieved from
http://www.ioffe.ru/SVA/NSM/Semicond/Ge/electric.html
[5] Accuratus, “Aluminum Oxide, Al2O3 Ceramic Properties,” 2013,
Retrieved from http://accuratus.com/alumox.html
[6] P Kordos, A Fox, R Kudela, M Mikulics, R Stoklas, and D
Gregusova, “GaAs-Based Metal-Oxide-Semiconductor Field-Effect
Transistor with Aluminum Oxide Gate Insulator Prepared in Situ by
MOCVD,” Sep. 26, 2012, Retrieved from
http://iopscience.iop.org/article/10.1088/0268-
1242/27/11/115002/meta
[7] B. Sapoval, Claudine Hermann, and C. Hermann, “Physics of
Semiconductors,” pp. 259, Springer Science & Business Media, Oct.
13, 2003.
[8] Ben Streetman and Sanjay Banerjee, “Solid State Electronic
Devices,” 5th ed., Prentice Hall, 1999.
[9] Jon Engelbert, Thien Nguyen, and Colleen Thurston, “B2 Spice A/D
2000 User’s Manual,” Beige Bag Software, Inc, 1996.
[10] C. Kittel, “Introduction to Solid State Physics,” 6th ed., pp. 185,
Wiley, 1986.
[11] Jasprit Singh, “Semiconductor Devices: Basic Principles,” Wiley,
July 2000.
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APPENDIX I.
12
13
 14

APPENDIX II.
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