Percobaan 5

Synthesizable MIPS32®
Microprocessor Bagian III : Top Level Design
dan Testbench
Dini Nur Farida Putri (13215018)
Asisten : Faldy Queimena (13214089)
Tanggal Percobaan : 28/11/2017
EL3111 Praktikum Arsitektur Sistem Komputer
Laboratorium Sinyal dan Sistem – Sekolah Teknik Elektro dan Informatika
Institut Teknologi Bandung

Pada praktikum ke 5 dengan judul Synthesizable MIPS32® desain mikroprosesor Single-Cycle MIPS32® dalam
Microprocessor Bagian III : Top Level Design dan Testbench ini kode VHDL dan dapat disimulasikan dengan Altera®
menggunakan beberapa perangkat. Beberapa perangkat yang Quartus® II v9.1sp2
digunakan dintaranya PC dengan system operasi Microsoft ®
Windows TM 7/8/8.1, Altera® Quartus® II v9.1sp2, PCSpim sebagai
simulator MIPS32®, dan Notepad++. Praktikum ini akan dilakukan
2 tugas. 2 tugas diantaranya yaitu Implementasi Top Level Design
MIPS32® dan Pengujian Menggunakan Testbench. II. LANDASAN TEORETIS

Kata Kunci—VHDL, Altera®, MIPS32®, Multiplexer. A. Data Path dan Control

I. PENDAHULUAN
D alam praktikum ke 5 ini akan dilakukan
pengimplementasian top level design MIPS32® dan
dilakukan pengujian menggunakan testbench. Bahasa yang
digunakan dalam eprcobaan ke 4 ini yaitu Bahasa VHDL secara
structural dan secara behavioral. Setiap percobaan akan diamati
dengan simulasi functional dan simulasi timing.
Tujuan yang ingin dicapai pada praktikum percobaan 5 ini
yaitu:
1. Praktikan dapat memahami arsitektur mikroprosesor
MIPS32® beserta datapath eksekusinya.
2. Praktikan dapat memahami instruction set dari
MIPS32® dan dapat membuat program sederhana dalam
Bahasa assembly yang dapat dieksekusi pada MIPS32®
3. Praktikan dapat melakukan eksekusi program MIPS32®
pada program simulasi SPIM dan memahami cara setiap
instruksi dieksekusi
4. Praktikan dapat menggabungkan komponen-komponen
desain yang telah dibuat dari praaktikum sebelumnya
dalam kode VHDL untuk membuat top level design dari
mikroprosesor Single-Cycle MIPS32® yang
synthesizable dna dapat disimulasikam dengan Altera®
Quartus ® II v9.1sp2
5. Praktikan dapat membuat testbench untuk menguji
Dalam desain mikroprosesor Single-Cycle MIPS32®,
rangkaian digital dapat dikelompokkan menjadi dua macam,
yaitu datapath (jalur data) dan control (kontrol). Datapath
merupakan komponen dari mikroprosesor yang melakukan
operasi aritmetik serta melakukan penyimpanan data. Dalam
datapath pula kelima tahap pemrosesan instruksi meliputi
instruction fetch, instruction decode, execute, memory access,
dan write back dilaksanakan. Sedangkan control merupakan
komponen dari mikroprosesor yang mengatur datapath
berdasarkan instruksi yang sedang dieksekusi.
Bagian kontrol telah direpresentasikan oleh control unit
yang telah kita desain pada praktikum sebelumnya. Untuk
bagian datapath, kita perlu menggabungkan komponen-
komponen yang telah kita buat meliputi multiplexer, ALU,
register, data memory, instruction memory, dan sebagainya
untuk membentuk sebuah jalur yang dapat dilewati oleh data.
Dengan demikian, control dan datapath tidak dapat dipisahkan
dalam desain sebuah mikroprosesor. Datapath dan control akan
membentuk sebuah desainmikroprosesor Single-Cycle
MIPS32® yang disebut sebuah top-level design (desain paling
atas). Top-level design pada umumnya hanya berisi port
mapping dari satu komponen ke komponen lain.

B. Menggunakan Testbench untuk Simulasi
Dalam melakukan simulasi sebuah rangkaian digital,
biasanya kita memberikan sinyal input secara manual melalui
sebuah waveform editor. Cara ini boleh dibilang sederhana
namun akan sangat tidak efektif apabila kita melakukan
simulasi secara berulang-ulang. Cara lain untuk melakukan
simulasi suatu rangkaian digital tanpa memberikan input satu
per satu menggunakan waveform editor adalah menggunakan
testbench.
Testbench terdiri atas kode VHDL atau Verilog HDL,
tergantung pada implementasi. Testbench sendiri dapat berisi
sebuah desain yang menyimpan nilai-nilai sinyal input yang
harus diberikan kepada desain yang sedang diuji (design under
test). Kemudian, testbench ini akan mengeluarkan
masingmasing input yang harus diberikan kepada desain yang
sedang diuji berdasarkan suatu trigger, misalnya clock.
B. Tugas 2 : Perancangan Left Shift Dua Kali
III. HASIL DAN ANALISIS
A. Tugas I : Implementasi Top Level Design MIPS32®
Pada tugas 1 ini diminta untuk menggabungkan komponen-
komponen yang dibuat pada percobaan sebelumnya. Data-data
yang perlu dimasukan yaitu code script komponen ALU, bus-
merger, cla_32,comparator, CU, data_memory, instrucMEM,
instruction_memory, lshift_26_28, lshift 32_32, mips,
mux_2to1_8bit, mux_2to1_32bit, mux_4to1_5bit,
mux_4to1_32bit, program_counter, reg_file, dan
sign_extender. Dan yang dihasilkan pada tugas 1 ini yaitu
sebuat top level design MIPS32® dengan datapath seperti pada
gambar berikut.
 Single-Cycle MIPS32® dapat dirancang dengan
- Simulasi Functional
Gambar hasil simulasi functional akan ditampilkan pada
lampiran.
Hasil simulasi functional sudah sesuai dengan yang
diharapkan. Program counter multiplexer 2 to 1 dengan input
reset dan clock akan menghasilkan counter dengan selisih 4
yang kemudian hasilnya berisi alamat data dikirim ke
multiplexer 2 to 1 instruction memory. Instruction memory
memiliki input PC_out dan clock serta mengeluarkan output
INSTR yang merupakan data dari alamat yang dikirimkan
oleh program counter. Setiap proses dari program counter dan
instruction memory mengalami delay selama masing-masing
1 clock. Sehingga output INSTR mengalami delay selama 2
clock dari awal program dijalankan.
- Simulasi Timing
Gambar hasil simulasi functional akan ditampilkan pada
lampiran.
Untuk hasil simulasi timing terdapat perbedaan dengan
hasil simulasi functional. Pada hasil simulasi timing terdapat
delay yang tidak beraturan dan sering terjadi pada saat
pergantian clock. Namun nilai ouput yang sebenarnya tetap
sesuai hanya saja hanya terlihat muncul sedikit sehingga
tidaak terlihat pada gambar.
Pada tugas 2 ini tidak dapat dilakukan dikarenakan
kekurangan waktu untuk mengerjakannya. Namun hasilnya
(nilai INSTR) berbeda dengan yang tugas 1 karena program
yang digunakan berbeda. Selain itu pada tugas 2 ini
menggunakan testbench sehingga output yang terlihat hanya
output yang diinginkan saja (sesuai code yang dibuat). Kalau
tanpa testbench hasil output yang terlihat yaitu semua hasil
operasi bahkan pada bagian yang diinginkan.
IV. SIMPULAN
menggabungkan komponen-komponen yang diperlukan
 dalam system.
 Single-Cycle MIPS32® dapat menggunakan testbench yang
berguna untuk mempermudahkan hasil output yang diamati

REFERENSI
[1] Tim Asisten Praktikum. 2017. Modul Praktikum EL3111 Arsitektur
Sistem Komputer. Bandung. Laboratorium Sinyal dan Sistem Sekolah
Teknik Elektri dan Informatika Institut Teknologi Bandung.
 Lampiran
1. Hasil Simulasi Tugas 1:
- Simulasi functional

- Simulasi timing

2. Code Tugas 1
- ALU.vhd
- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
- USE ieee.std_logic_unsigned.ALL;
-
- ENTITY ALU IS
- PORT
- (
- OPRND_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- OPRND_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- OP_SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
- RESULT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
- );
- END ALU;
-
- ARCHITECTURE behavioral OF ALU IS
-
- SIGNAL CARRY : STD_LOGIC;
- SIGNAL OPRND_2_CHOOSED : STD_LOGIC_VECTOR(31 DOWNTO 0);
-
 - COMPONENT cla_32 IS
- PORT(
- OPRND_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- OPRND_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- C_IN : IN STD_LOGIC;
- RESULT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- C_OUT : OUT STD_LOGIC
- );
- END COMPONENT;
-
- BEGIN
- adder : cla_32
- PORT MAP (
- OPRND_1 => OPRND_1,
- OPRND_2 => OPRND_2_CHOOSED,
- C_IN => '0',
- RESULT => RESULT,
- C_OUT => carry
- );
-
- OPRND_2_CHOOSED <= OPRND_2 WHEN (OP_SEL = "00") ELSE (NOT OPRND_2
+ 1);
- END behavioral;
- bus_merger.vhd
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
-
- --- Bus Merger
- ENTITY bus_merger IS
- PORT( DATA_IN1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
- DATA_IN2 : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
- DATA_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
- );
- END bus_merger;
-
- ARCHITECTURE behavior OF bus_merger IS
- BEGIN
- DATA_OUT(31 DOWNTO 28) <= DATA_IN1;
- DATA_OUT(27 DOWNTO 0) <= DATA_IN2;
- END behavior;
- cla_32.vhd
-
- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
-
- ENTITY cla_32 IS
 - PORT
- (
- OPRND_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- OPRND_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- C_IN : IN STD_LOGIC;
- RESULT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- C_OUT : OUT STD_LOGIC
- );
- END cla_32;
-
- ARCHITECTURE behavioral OF cla_32 IS
-
- SIGNAL H_SUM : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL G : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL P : STD_LOGIC_VECTOR(31 DOWNTO 0);
- SIGNAL C_IN_INTERNAL : STD_LOGIC_VECTOR(31 DOWNTO 1);
-
- BEGIN
- H_SUM <= OPRND_1 XOR OPRND_2;
- G <= OPRND_1 AND OPRND_2;
- P <= OPRND_1 OR OPRND_2;
- PROCESS (G,P,C_IN_INTERNAL)
- BEGIN
- C_IN_INTERNAL(1) <= G(0) OR (P(0) AND C_IN);
- inst: FOR i IN 1 TO 30 LOOP
- C_IN_INTERNAL(i+1) <= G(i) OR (P(i) AND
C_IN_INTERNAL(i));
- END LOOP;
- C_OUT <= G(31) OR (P(31) AND C_IN_INTERNAL(31));
- END PROCESS;
-
- RESULT(0) <= H_SUM(0) XOR C_IN;
- RESULT(31 DOWNTO 1) <= H_SUM(31 DOWNTO 1) XOR C_IN_INTERNAL(31
DOWNTO 1);
- END behavioral;
- comparator.vhd
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
-
- --- COMPARATOR n-BIT
- ENTITY comparator IS
- GENERIC(n:INTEGER:=32); --- Mengatur jumlah bit
- PORT( D_1,D_2 : IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
- EQ : OUT STD_LOGIC
- );
- END comparator;
-
 - ARCHITECTURE behavior OF comparator IS
- SIGNAL zeros : STD_LOGIC_VECTOR (n-1 DOWNTO 0) := (others =>
'0');
- SIGNAL comp : STD_LOGIC_VECTOR (n-1 DOWNTO 0);
- BEGIN
-
-
- comp <= D_1 XOR D_2;
-
- --- Cara kerja komparator memanfaatkan fungsi XNOR
- EQ <= '1' WHEN (zeros = comp) ELSE '0';
- END behavior;
- CU.vhd
-
- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
- USE ieee.std_logic_unsigned.ALL;
-
- ENTITY CU IS
- PORT (
- OP_In : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
- FUNCT_In : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
- Sig_Jmp : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
- Sig_Bne : OUT STD_LOGIC;
- Sig_Branch : OUT STD_LOGIC;
- Sig_MemtoReg : OUT STD_LOGIC;
- Sig_MemRead : OUT STD_LOGIC;
- Sig_MemWrite : OUT STD_LOGIC;
- Sig_RegDest : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
- Sig_RegWrite : OUT STD_LOGIC;
- Sig_ALUSrc : OUT STD_LOGIC;
- Sig_ALUCtrl : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
- );
- END CU;
-
- ARCHITECTURE behavioral OF CU IS
- BEGIN
- PROCESS(OP_In, FUNCT_In)
- BEGIN
- IF (OP_In = x"00") THEN -- Instruksi Tipe R
- Sig_Jmp <= "00";
- Sig_Bne <= '0';
- Sig_Branch <= '0';
- Sig_MemtoReg <= '0';
- Sig_MemRead <= '0';
- Sig_MemWrite <= '0';
- Sig_RegDest <= "01";
- Sig_RegWrite <= '1';
- Sig_ALUSrc <= '0';
- IF (FUNCT_In = x"20") THEN
- Sig_ALUCtrl <= "00";
- ELSE -- Subtraksi
- Sig_ALUCtrl <= "01";
- END IF;
- ELSIF (OP_In = x"04") THEN -- Instruksi untuk beq
- Sig_Jmp <= "00";
- Sig_Bne <= '0';
- Sig_Branch <= '1';
- Sig_MemtoReg <= '0';
- Sig_MemRead <= '0';
- Sig_MemWrite <= '0';
- Sig_RegWrite <= '0';
- ELSIF (OP_In = x"05") THEN -- Instruksi untuk bnq
- Sig_Jmp <= "00";
- Sig_Bne <= '1';
- Sig_Branch <= '0';
- Sig_MemtoReg <= '0';
- Sig_MemRead <= '0';
- Sig_MemWrite <= '0';
- Sig_RegWrite <= '0';
- ELSIF (OP_In = x"08") THEN -- Instruksi addi
- Sig_Jmp <= "00";
- Sig_Bne <= '0';
- Sig_Branch <= '0';
- Sig_MemtoReg <= '0';
- Sig_MemRead <= '0';
- Sig_MemWrite <= '0';
- Sig_RegDest <= "01";
- Sig_RegWrite <= '1';
- Sig_ALUSrc <= '1';
- Sig_ALUCtrl <= "00";
- ELSIF (OP_In = x"23") THEN -- Instruksi lw
- Sig_Jmp <= "00";
- Sig_Bne <= '0';
- Sig_Branch <= '0';
- Sig_MemtoReg <= '1';
- Sig_MemRead <= '1';
- Sig_MemWrite <= '0';
- Sig_RegDest <= "00";
- Sig_RegWrite <= '1';
- Sig_ALUSrc <= '1';
- Sig_ALUCtrl <= "00";
- ELSIF (OP_In = x"2b") THEN -- Instruksi sw
- Sig_Jmp <= "00";
 - Sig_Bne <= '0';
- Sig_Branch <= '0';
- Sig_MemtoReg <= '0';
- Sig_MemRead <= '0';
- Sig_MemWrite <= '1';
- Sig_RegDest <= "00";
- Sig_RegWrite <= '0';
- Sig_ALUSrc <= '1';
- Sig_ALUCtrl <= "00";
- ELSIF (OP_In = x"02") THEN -- Instruksi jmp
- Sig_Jmp <= "01";
- Sig_Bne <= '0';
- Sig_Branch <= '0';
- Sig_MemtoReg <= '0';
- Sig_MemRead <= '0';
- Sig_MemWrite <= '0';
- Sig_RegWrite <= '0';
- ELSE
- Sig_Jmp <= "00";
- Sig_Bne <= '0';
- Sig_Branch <= '0';
- Sig_MemtoReg <= '0';
- Sig_MemRead <= '0';
- Sig_MemWrite <= '0';
- Sig_RegDest <= "00";
- Sig_RegWrite <= '0';
- Sig_ALUSrc <= '0';
- Sig_ALUCtrl <= "00";
- END IF;
- END PROCESS;
- END behavioral;
- Data_memory.vhd
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- LIBRARY altera_mf;
- USE altera_mf.all;
-
- ENTITY data_memory IS
- PORT (
- ADDR : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- alamat
- WR_EN : IN STD_LOGIC; --Indikator Penulisan
- RD_EN : IN STD_LOGIC; --Indikator Pembacaan
- clock : IN STD_LOGIC := '1'; -- clock
- RD_Data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
- WR_Data : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
- );
- END ENTITY;
 -
- ARCHITECTURE structural OF data_memory IS
- COMPONENT altsyncram
- -- komponen memori
- GENERIC
- (
- init_file : STRING; -- name of the .mif file
- operation_mode : STRING; -- the operation mode
- widthad_a : NATURAL; -- width of address_a[]
- width_a : NATURAL -- width of data_a[]
- );
- PORT
- (
- wren_a : IN STD_LOGIC; -- Write Enable Activation
- clock0 : IN STD_LOGIC ; -- Clock
- address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- Address
Input
- q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- Data Output
- data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0) -- Data Input
- );
- END COMPONENT;
-
- BEGIN
- altsyncram_component : altsyncram
- GENERIC MAP
- (
- init_file => "dmemory.mif",
- operation_mode => "SINGLE_PORT",
- widthad_a => 8,
- width_a => 8
- )
- PORT MAP
- (
- wren_a => WR_EN, -- isi yang sesuai
- clock0 => clock,
- address_a => ADDR,
- q_a => RD_Data, -- isi yang sesuai
- data_a => WR_Data
- );
-
- END structural;
- instrucMEM.vhd
- -- Praktikum EL3111 Arsitektur Sistem Komputer
- -- Modul : 05
- -- Percobaan : 01 dan 02
- -- Tanggal : 28 November 2017
- -- Kelompok : 02
- -- Rombongan : B
- -- Nama (NIM) 1: Dini Nur Farida Putri (13215018)
- -- Nama (NIM) 2: Charlie Tahar (13215079)
- -- Nama File : instrucMEM.vhd
- -- Deskripsi : Desain instruction memory
-
-
- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.STD_LOGIC_ARITH.ALL;
- USE IEEE.STD_LOGIC_UNSIGNED.ALL;
- LIBRARY altera_mf;
- USE altera_mf.altera_mf_components.ALL;
-
- ENTITY instrucMEM IS
- PORT (
- ADDR : IN std_logic_vector (31 DOWNTO 0);
- clock : IN std_logic; reset : IN std_logic;
- INSTR : OUT std_logic_vector (31 DOWNTO 0)
- );
- END ENTITY;
-
- ARCHITECTURE behavior OF instrucMEM IS
- TYPE ramtype IS ARRAY (31 DOWNTO 0) OF std_logic_vector (31 DOWNTO
0);
- SIGNAL mem: ramtype;
- BEGIN
- PROCESS (reset,ADDR,mem)
- BEGIN
- IF (reset='1') THEN
- INSTR <= (OTHERS => '0');
- ELSE
- INSTR <= mem(conv_integer (ADDR));
- END IF;
- END PROCESS;
- -- Isi dalam instruction memory
- mem(0) <= X"20100000";
- mem(4) <= X"20110000";
- mem(8) <= X"2012000A";
- mem(12) <= X"00000000";
- mem(1C) <= X"22100001";
- mem(20) <= X"22310001";
- mem(24) <= X"1651FFFD";
- mem(2C) <= X"00000000";
- END behavior;
-
- instruction_memory.vhd
-
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- LIBRARY altera_mf;
- USE altera_mf.all;
-
- ENTITY instruction_memory IS
- PORT (
- ADDR : IN STD_LOGIC_VECTOR (15 DOWNTO 0); -- alamat
- clock : IN STD_LOGIC := '1'; -- clock
- INSTR : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) -- output
- );
- END ENTITY;
-
- ARCHITECTURE structural OF instruction_memory IS
- SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
- -- signal keluaran output
- COMPONENT altsyncram
- -- komponen memori
- GENERIC
- (
- init_file : STRING; -- name of the .mif file
- operation_mode : STRING; -- the operation mode
- widthad_a : NATURAL; -- width of address_a[]
- width_a : NATURAL -- width of data_a[]
- );
- PORT
- (
- clock0 : IN STD_LOGIC ;
- address_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
- q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
- );
- END COMPONENT;
-
- BEGIN
- INSTR <= sub_wire0;
- altsyncram_component : altsyncram
- GENERIC MAP
- (
- init_file => "imemory.mif",
- operation_mode => "ROM",
- widthad_a => 16,
- width_a => 32
- )
- PORT MAP
- (
 - clock0 => clock,
- address_a => ADDR,
- q_a => sub_wire0
- );
- END structural ;
- lshift_26_28.vhd
-
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
-
- --- COMPARATOR n-BIT
- ENTITY lshift_26_28 IS
- GENERIC(n:INTEGER:=26); --- Mengatur jumlah bit
- PORT( D_IN : IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
- D_OUT : OUT STD_LOGIC_VECTOR (n+1 DOWNTO 0)
- );
- END lshift_26_28;
-
- ARCHITECTURE behavior OF lshift_26_28 IS
- BEGIN
- D_OUT(27 DOWNTO 2) <= D_IN;
- D_OUT(1 DOWNTO 0) <= "00";
- END behavior;
- lshift32_32.vhd
-
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
-
- --- COMPARATOR n-BIT
- ENTITY lshift_32_32 IS
- GENERIC(n:INTEGER:=32); --- Mengatur jumlah bit
- PORT( D_IN : IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
- D_OUT : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0)
- );
- END lshift_32_32;
-
- ARCHITECTURE behavior OF lshift_32_32 IS
- BEGIN
- D_OUT(31 DOWNTO 2) <= D_IN(29 DOWNTO 0);
- D_OUT(1 DOWNTO 0) <= "00";
- END behavior;
- mips32.vhd
-
- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.all;
- USE IEEE.STD_LOGIC_ARITH.all;
- USE IEEE.STD_LOGIC_UNSIGNED.all;
-
- ENTITY MIPS32 IS
- PORT ( reset : IN STD_LOGIC;
- clockin : IN STD_LOGIC;
- PC_in_test : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- PC_out_test : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- adder1_test : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- adder2_test : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- INSTR_test : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- ADDR1_test : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
- ADDR2_test : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
- ADDR3_test : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
- OP_In_test : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
- FUNCT_In_test : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
- Sig_Jmp_test : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
- Sig_Bne_test : OUT STD_LOGIC;
- Sig_Branch_test : OUT STD_LOGIC;
- Sig_Bnb_rst_test : OUT STD_LOGIC;
- Sig_MemtoReg_test : OUT STD_LOGIC;
- Sig_MemRead_test : OUT STD_LOGIC;
- Sig_MemWrite_test : OUT STD_LOGIC;
- Sig_RegDest_test : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
- Sig_RegWrite_test : OUT STD_LOGIC;
- Sig_ALUsrc_test : OUT STD_LOGIC;
- Sig_ALUCtrl_test : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
- WR_Data_3_test : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- RD_Data_test : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
- RD_Data_1_test : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- RD_Data_2_test : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- Bus_merge_test : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- Sign_extend_test : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- lshift_32_32_test : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
- lshift_26_28_test : OUT STD_LOGIC_VECTOR (27 DOWNTO 0);
- ALU_test : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
- );
- END MIPS32;
-
- ARCHITECTURE behavior OF MIPS32 IS
-
- COMPONENT mux_2to1_32bit IS
- PORT (
- D1 : IN std_logic_vector (31 DOWNTO 0);
- D2 : IN std_logic_vector (31 DOWNTO 0);
- Y : OUT std_logic_vector (31 DOWNTO 0);
- S : IN std_logic
- );
- END COMPONENT ;
-
- COMPONENT mux_2to1_8bit IS
- PORT (
- D1 : IN std_logic_vector (7 DOWNTO 0);
- D2 : IN std_logic_vector (7 DOWNTO 0);
- Y : OUT std_logic_vector (7 DOWNTO 0);
- S : IN std_logic
- );
- END COMPONENT ;
-
- COMPONENT mux_4to1_32bit IS
- PORT (
- D1 : IN std_logic_vector (31 DOWNTO 0);
- D2 : IN std_logic_vector (31 DOWNTO 0);
- D3 : IN std_logic_vector (31 DOWNTO 0);
- D4 : IN std_logic_vector (31 DOWNTO 0);
- Y : OUT std_logic_vector (31 DOWNTO 0);
- S : IN std_logic_vector (1 DOWNTO 0)
- );
- END COMPONENT ;
-
- COMPONENT mux_4to1_5bit IS
- PORT (
- D1 : IN std_logic_vector (4 DOWNTO 0);
- D2 : IN std_logic_vector (4 DOWNTO 0);
- D3 : IN std_logic_vector (4 DOWNTO 0);
- D4 : IN std_logic_vector (4 DOWNTO 0);
- Y : OUT std_logic_vector (4 DOWNTO 0);
- S : IN std_logic_vector (1 DOWNTO 0)
- );
- END COMPONENT ;
-
- COMPONENT cla_32 IS
- PORT (
- OPRND_1 : IN std_logic_vector (31 DOWNTO 0);
- OPRND_2 : IN std_logic_vector (31 DOWNTO 0);
- C_IN : IN std_logic;
- RESULT : OUT std_logic_vector (31 DOWNTO 0);
- C_OUT : OUT std_logic
- );
- END COMPONENT ;
-
- COMPONENT program_counter IS
- PORT (
- clk : IN std_logic;
- PC_in : IN std_logic_vector (31 DOWNTO 0);
- PC_out : OUT std_logic_vector (31 DOWNTO 0)
- );
- END COMPONENT ;
-
- COMPONENT instruction_memory IS
- PORT (
- ADDR : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
- clock : IN STD_LOGIC;
- INSTR : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT reg_file IS
- PORT (
- clock : IN STD_LOGIC;
- WR_EN : IN STD_LOGIC;
- ADDR_1 : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
- ADDR_2 : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
- ADDR_3 : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
- WR_Data_3 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
- RD_Data_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- RD_Data_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT cu IS
- PORT (
- OP_In : IN std_logic_vector (5 DOWNTO 0);
- FUNCT_In : IN std_logic_vector (5 DOWNTO 0);
- Sig_Jmp : OUT std_logic_vector (1 DOWNTO 0);
- Sig_Bne : OUT std_logic;
- Sig_Branch : OUT std_logic;
- Sig_MemtoReg : OUT std_logic;
- Sig_MemRead : OUT std_logic;
- Sig_MemWrite : OUT std_logic;
- Sig_RegDest : OUT std_logic_vector (1 DOWNTO 0);
- Sig_RegWrite : OUT std_logic;
- Sig_ALUsrc : OUT std_logic;
- Sig_ALUCtrl : OUT std_logic_vector (1 DOWNTO 0)
- );
- END COMPONENT ;
-
- COMPONENT ALU IS
- PORT (
- OPRND_1 : IN std_logic_vector (31 DOWNTO 0);
- OPRND_2 : IN std_logic_vector (31 DOWNTO 0);
- OP_SEL : IN std_logic_vector (1 DOWNTO 0);
- RESULT : OUT std_logic_vector (31 DOWNTO 0)
- );
- END COMPONENT ;
-
- COMPONENT data_memory IS
- PORT (
- ADDR : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
- WR_EN : IN STD_LOGIC;
- RD_EN : IN STD_LOGIC;
- clock : IN STD_LOGIC;
- RD_Data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
- WR_Data : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
- );
- END COMPONENT ;
-
- COMPONENT comparator IS
- PORT (
- D_1 : IN std_logic_vector (31 DOWNTO 0);
- D_2 : IN std_logic_vector (31 DOWNTO 0);
- EQ : OUT std_logic
- );
- END COMPONENT ;
-
- COMPONENT lshift_26_28 IS
- PORT (
- D_IN : IN std_logic_vector (25 DOWNTO 0);
- D_OUT : OUT std_logic_vector (27 DOWNTO 0)
- );
- END COMPONENT ;
-
- COMPONENT lshift_32_32 IS
- PORT (
- D_IN : IN std_logic_vector (31 DOWNTO 0);
- D_OUT : OUT std_logic_vector (31 DOWNTO 0)
- );
- END COMPONENT ;
-
- COMPONENT sign_extender IS
- PORT (
- D_In : IN std_logic_vector (15 DOWNTO 0);
- D_Out : OUT std_logic_vector (31 DOWNTO 0)
- );
- END COMPONENT ;
-
- COMPONENT bus_merger IS
- PORT (
- DATA_IN1 : IN std_logic_vector (3 DOWNTO 0);
- DATA_IN2 : IN std_logic_vector (27 DOWNTO 0);
- DATA_OUT : OUT std_logic_vector (31 DOWNTO 0)
- );
- END COMPONENT ;
-
- SIGNAL outmux211, outmux213, outmux411, outmux412, se_out,
ls32out ,inwrd3 : std_logic_vector (31 DOWNTO 0);
- SIGNAL add1, add2, adr, alu_rst, alu_in, rd1, rd2, wrd, inst,
bm_out, blank1 : std_logic_vector (31 DOWNTO 0);
- SIGNAL ls28out : std_logic_vector
(27 DOWNTO 0);
- SIGNAL ls28in : std_logic_vector
(25 DOWNTO 0);
- SIGNAL se_in : std_logic_vector (15
DOWNTO 0);
- SIGNAL rd0, outmux212 :
std_logic_vector (7 DOWNTO 0);
- SIGNAL adr3, blank2 :
std_logic_vector (4 DOWNTO 0);
- SIGNAL s_regd, s_aluctrl, s_jump :
std_logic_vector (1 DOWNTO 0);
- SIGNAL s_bne, s_branch, s_bnb, s_mreg, s_memr, s_memw, s_regw,
s_alusrc, s_eq, c1, c2 : std_logic;
-
- BEGIN
-
- with reset select
- outmux213 <= outmux411 WHEN '0',
- x"00000000" WHEN '1';
-
- muxPCj :mux_2to1_32bit
- PORT MAP(
- D1 => add1,
- D2 => add2,
- Y => outmux211,
- S => s_bnb
- );
-
- muxWB:mux_2to1_8bit
- PORT MAP(
- D1 => alu_rst(7 downto 0),
- D2 => rd0,
- Y => outmux212,
- S => s_mreg
- );
-
- muxJmp :mux_4to1_32bit
- PORT MAP(
- D1 => outmux211,
- D2 => bm_out,
- D3 => blank1,
- D4 => blank1,
- Y => outmux411,
- S => s_jump
- );
- muxALU2 :mux_4to1_32bit
- PORT MAP( D1 => rd2,
- D2 => se_out,
- D3 => blank1,
- D4 => blank1,
- Y => outmux412,
- S => '0' & s_alusrc
- );
-
- muxAddr3 :mux_4to1_5bit
- PORT MAP(
- D1 => inst(20 DOWNTO 16),
- D2 => inst(15 DOWNTO 11),
- D3 => blank2,
- D4 => blank2,
- Y => adr3,
- S => s_regd
- );
-
- adderPC4 :cla_32 -- Sudah
- PORT MAP(
- OPRND_1 => adr,
- OPRND_2 => x"00000004",
- C_IN => '0',
- RESULT => add1,
- C_OUT => c1
- );
-
- adderPCj :cla_32
- PORT MAP(
- OPRND_1 => ls32out,
- OPRND_2 => add1,
- C_IN => '0',
- RESULT => add2,
- C_OUT => c2
- );
-
- counter :program_counter
- PORT MAP(
- clk => clockin,
- PC_in => outmux213,
- PC_out => adr
- );
-
- ins_mem :instruction_memory
- PORT MAP(
- ADDR => adr(15 DOWNTO 0),
- clock => clockin,
- INSTR => inst
- );
-
- reg_f :reg_file
- PORT MAP(
- clock => clockin,
- WR_EN => s_regw,
- ADDR_1 => inst(25 DOWNTO 21),
- ADDR_2 => inst(20 DOWNTO 16),
- ADDR_3 => adr3,
- WR_Data_3 => inwrd3,
- RD_Data_1 => rd1,
- RD_Data_2 => rd2
- );
-
- controlUnit :cu
- PORT MAP(
- OP_In => inst(31 DOWNTO 26),
- FUNCT_In => inst(5 DOWNTO 0),
- Sig_Jmp => s_jump,
- Sig_Bne => s_bne,
- Sig_Branch => s_branch,
- Sig_MemtoReg => s_mreg,
- Sig_MemRead => s_memr,
- Sig_MemWrite => s_memw,
- Sig_RegDest => s_regd,
- Sig_RegWrite => s_regw,
- Sig_ALUSrc => s_alusrc,
- Sig_ALUCtrl => s_aluctrl
- );
-
- ALU1 :ALU
- PORT MAP(
- OPRND_1 => rd1,
- OPRND_2 => outmux412,
- OP_SEL => s_aluctrl,
- RESULT => alu_rst
- );
-
- dat_mem :data_memory
- PORT MAP(
- ADDR => alu_rst(7 DOWNTO 0),
- WR_EN => s_memw,
- RD_EN => s_memr,
- clock => clockin,
- RD_Data => rd0,
- WR_Data => rd2(7 DOWNTO 0)
- );
-
- cmp :comparator
- PORT MAP(
- D_1 => rd1,
- D_2 => rd2,
- EQ => s_eq
- );
-
- ls2628 :lshift_26_28
- PORT MAP(
- D_IN => inst(25 DOWNTO 0),
- D_OUT => ls28out
- );
-
- ls3232 :lshift_32_32
- PORT MAP(
- D_IN => se_out,
- D_OUT => ls32out
- );
-
- sign_ex :sign_extender
- PORT MAP(
- D_In => inst(15 DOWNTO 0),
- D_Out => se_out
- );
-
- bus_mer :bus_merger
- PORT MAP(
- DATA_IN1 => add1(31 DOWNTO 28),
- DATA_IN2 => ls28out,
- DATA_OUT => bm_out
- );
-
- with outmux212(7) select -- Mux Reset
- inwrd3 <= x"000000" & outmux212 WHEN '0',
- x"FFFFFF" & outmux212 WHEN '1';
-
 - blank1 <= (others => '0');
- blank2 <= (others => '0');
- s_bnb <= (s_bne AND (NOT s_eq)) OR (s_branch AND s_eq);
- PC_in_test <= outmux411;
- PC_out_test <= adr;
- adder1_test <= add1;
- adder2_test <= add2;
- INSTR_test <= inst;
- ADDR1_test <= inst(25 DOWNTO 21);
- ADDR2_test <= inst(20 DOWNTO 16);
- ADDR3_test <= adr3;
- OP_In_test <= inst(31 DOWNTO 26);
- FUNCT_In_test <= inst(5 DOWNTO 0);
- Sig_Jmp_test <= s_jump;
- Sig_Bne_test <= s_bne;
- Sig_Branch_test <= s_branch;
- Sig_Bnb_rst_test <= s_bnb;
- Sig_MemtoReg_test <= s_mreg;
- Sig_MemRead_test <= s_memr;
- Sig_MemWrite_test <= s_memw;
- Sig_RegDest_test <= s_regd;
- Sig_RegWrite_test <= s_regw;
- Sig_ALUsrc_test <= s_alusrc;
- Sig_ALUCtrl_test <= s_aluctrl;
- WR_Data_3_test <= inwrd3;
- RD_Data_test <= rd0;
- RD_Data_1_test <= rd1;
- RD_Data_2_test <= rd2;
- Bus_merge_test <= bm_out;
- Sign_extend_test <= se_out;
- lshift_32_32_test <= ls32out;
- lshift_26_28_test <= ls28out;
- ALU_test <= alu_rst(7 DOWNTO 0);
-
- END behavior;
- mux_2to1_8bit.vhd
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
-
- --- Multiplexer n-BIT
- ENTITY mux_2to1_8bit IS
- GENERIC(n:INTEGER:=8); --- Mengatur jumlah bit
- PORT( S : IN STD_LOGIC;
- D1,D2 : IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
- Y : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0)
- );
- END mux_2to1_8bit;
 -
- ARCHITECTURE behavior OF mux_2to1_8bit IS
- BEGIN
- --- Cara kerja Multiplexer, ketika Sel = '0' Memilih A dan Ketika
Sel = '1' Memilih B
- Y <= D1 WHEN (S = '0') ELSE D2;
- END behavior;
- mux_2to1_32bit.vhd
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
-
- --- Multiplexer n-BIT
- ENTITY mux_2to1_32bit IS
- GENERIC(n:INTEGER:=32); --- Mengatur jumlah bit
- PORT( S : IN STD_LOGIC;
- D1,D2 : IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
- Y : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0)
- );
- END mux_2to1_32bit;
-
- ARCHITECTURE behavior OF mux_2to1_32bit IS
- BEGIN
- --- Cara kerja Multiplexer, ketika Sel = '0' Memilih A dan Ketika
Sel = '1' Memilih B
- Y <= D1 WHEN (S = '0') ELSE D2;
- END behavior;
- mux_4to1_5bit
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
-
- --- Multiplexer n-BIT
- ENTITY mux_4to1_5bit IS
- GENERIC(n:INTEGER:=5); --- Mengatur jumlah bit
- PORT( S : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
- D1,D2,D3,D4 : IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
- Y : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0)
- );
- END mux_4to1_5bit;
-
- ARCHITECTURE behavior OF mux_4to1_5bit IS
- BEGIN
- --- Cara kerja Multiplexer, ketika Sel = '0' Memilih A dan Ketika
Sel = '1' Memilih B
- WITH S SELECT
- Y <= D1 WHEN "00",
- D2 WHEN "01",
- D3 WHEN "10",
 - D4 WHEN "11",
- (others => '0') WHEN OTHERS;
- END behavior;
- mux_4to1_32bit.vhd
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
-
- --- Multiplexer n-BIT
- ENTITY mux_4to1_32bit IS
- GENERIC(n:INTEGER:=32); --- Mengatur jumlah bit
- PORT( S : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
- D1,D2,D3,D4 : IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
- Y : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0)
- );
- END mux_4to1_32bit;
-
- ARCHITECTURE behavior OF mux_4to1_32bit IS
- BEGIN
- --- Cara kerja Multiplexer, ketika Sel = '0' Memilih A dan Ketika
Sel = '1' Memilih B
- WITH S SELECT
- Y <= D1 WHEN "00",
- D2 WHEN "01",
- D3 WHEN "10",
- D4 WHEN "11",
- (others => '0') WHEN OTHERS;
- END behavior;
- program_counter.vhd
-
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
-
- --- Pogram Counter
- ENTITY program_counter IS
- GENERIC(n:INTEGER:=32); --- Mengatur jumlah bit
- PORT( clk : IN STD_LOGIC;
- PC_IN : IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
- PC_OUT : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0)
- );
- END program_counter;
-
- ARCHITECTURE behavior OF program_counter IS
- BEGIN
-
- PROCESS (clk)
- BEGIN
 - IF (Clk'event AND Clk='1') THEN -- bila rising edge maka
register bekerja
- PC_OUT <= PC_IN;
- END IF;
- END PROCESS;
- END behavior;
- reg_file.vhd
-
- LIBRARY ieee;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.STD_LOGIC_ARITH.ALL;
- USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
- ENTITY reg_file IS
- PORT (
- clock : IN STD_LOGIC; -- clock
- WR_EN : IN STD_LOGIC; -- write enable
- ADDR_1 : IN STD_LOGIC_VECTOR (4 DOWNTO 0); -- Input 1
- ADDR_2 : IN STD_LOGIC_VECTOR (4 DOWNTO 0); -- Input 2
- ADDR_3 : IN STD_LOGIC_VECTOR (4 DOWNTO 0); -- Input 3
- WR_Data_3 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);-- write data
- RD_Data_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);-- read data 1
- RD_Data_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- read data 2
- );
- END ENTITY ;
-
- ARCHITECTURE behavior OF reg_file IS
- TYPE ramtype IS ARRAY (31 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO
0);
- SIGNAL mem : ramtype;
-
- BEGIN
- PROCESS (clock)
- BEGIN
- IF clock'EVENT AND clock='0' THEN
- RD_Data_1 <= mem(conv_integer (ADDR_1));
- RD_Data_2 <= mem(conv_integer (ADDR_2));
- ELSIF clock'EVENT AND clock='1' AND WR_EN='1' THEN
- mem(conv_integer (ADDR_3)) <= WR_Data_3;
- END IF;
- END PROCESS;
-
- END behavior;
- sign_extender.vhd
-
- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
-
- ENTITY sign_extender IS
- PORT
- (
- D_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
- D_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
- );
- END sign_extender;
-
- ARCHITECTURE behavioral OF sign_extender IS
-
- BEGIN
- D_OUT(31 DOWNTO 16) <= (others => D_IN(15));
- D_OUT(15 DOWNTO 0) <= D_IN;
- END behavioral;