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`timescale 1ns / 1ps

module
adc(clk,clkout,spi_sck,enable,amp_cs,adc_conv,spi_miso,spi_mosi,amp_shdn,spi_ss_b,
sf_ce0,fpga_init_b,dac_cs);

input clk,enable;
input spi_miso;
output reg clkout;
output reg spi_sck;
output reg amp_cs;
output reg adc_conv;
output reg spi_mosi;
output reg amp_shdn;
output reg spi_ss_b,sf_ce0,fpga_init_b,dac_cs;

reg conversion=0;
reg adc_sent=0;

reg [3:0]clk_10_count=0;
reg [5:0]adc_clk_count=0;
reg [4:0]adc_bit_count=5'b10001;
reg [3:0]gain_count=8;
reg [2:0]count=0;

reg [13:0]adc_data1;
reg [13:0]adc_data2;
reg [7:0]data_gain=8'b00100010;

reg [3:0]state=4'b0000;
parameter idle=4'b0000,amp_gain=4'b0001,amp_start=4'b0010,adc_idle=4'b0011,
adc_start=4'b0100,adc_result=4'b0101,adc_done=4'b0110;

always@(posedge clk)
begin

if((count>2)&&(count<=5))
begin
clkout<=1;
count<=count+1;
end
else
begin
clkout<=0;
count<=count+1;
end
if(count>=6)
begin
count<=1;
end
end

always@(posedge clkout)
begin

if (enable)
begin
//amp_shdn<=1;
//amp_cs<=0;

spi_ss_b<=0;
sf_ce0<=1;
fpga_init_b<=1;
dac_cs<=1;

end

else

begin

case(state)

idle:begin

spi_sck<=1;
amp_shdn<=1;
adc_conv<=0;
amp_cs<=1;
spi_mosi<=0;
state<=amp_gain;
conversion<=0;
end

amp_gain:begin

spi_sck<=0;
amp_shdn<=0;
amp_cs<=0;
spi_mosi<=data_gain[gain_count-1];
gain_count<=gain_count-1;
state<=amp_start;
end

amp_start:begin

amp_cs<=0;
if(gain_count>0)
begin
spi_sck<=1;
state<=amp_gain;
end

else
begin
spi_sck<=1;
amp_shdn<=0;
//amp_cs<=1;
state<=adc_idle;
end
end
adc_idle:begin
amp_cs<=1;
adc_conv<=1;
spi_sck<=0;
state<=adc_start;
end

adc_start:begin

spi_sck<=1;
adc_conv<=0;
adc_clk_count<=adc_clk_count+1;
adc_bit_count<=adc_bit_count-1;
state<=adc_result;
end

//adc_convert:begin

//spi_sck<=0;
//adc_conv<=0;
//state<=adc_result;
//end

adc_result:begin

if(adc_clk_count==34)
begin
adc_sent<=1;
adc_conv<=1;
spi_sck<=0;
state<=adc_done;
end

else if(adc_clk_count<=2)
begin
spi_sck<=0;
state<=adc_start;
end

else if((adc_clk_count>2) && (adc_clk_count<=16))


begin
spi_sck<=0;
adc_data1[adc_bit_count-1]<=spi_miso;
state<=adc_start;
end

else if((adc_clk_count>16) && (adc_clk_count<=18))


begin
spi_sck<=0;
adc_bit_count<=15;
state<=adc_start;
end

else if((adc_clk_count>18) && (adc_clk_count<=32))


begin
spi_sck<=0;
adc_data2[adc_bit_count-1]<=spi_miso;
state<=adc_start;
end

else if(adc_clk_count==33)
begin
conversion<=1;
spi_sck<=0;
state<=adc_start;

end
end

adc_done:begin

adc_conv<=1;
spi_sck<=1;
amp_shdn<=1;
amp_cs<=1;
state<=amp_gain;
end

endcase
end
end

endmodule