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FDSOI Process Technology for Subthreshold-

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Article in ECS Transactions · January 2011

DOI: 10.1149/1.3570794

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 ECS Transactions, 35 (5) 179-188 (2011)
10.1149/1.3570794 © The Electrochemical Society

FDSOI Process Technology for Subthreshold-Operation Ultra-Low Power

Electronics

S. A. Vitale, P. W. Wyatt, N. Checka, J. Kedzierski, C. L. Keast1

MIT Lincoln Laboratory, Lexington, Massachusetts 02420, USA

Ultralow-power electronics will expand the technological

capability of handheld and wireless devices by dramatically
improving battery life and portability. In addition to innovative
low-power design techniques, a complementary process
technology is required to enable the highest performance devices
possible while maintaining extremely low power consumption.
Transistors optimized for subthreshold operation at 0.3 V may
achieve a 97% reduction in switching energy compared to
conventional transistors. The process technology described in this
article takes advantage of the capacitance and performance benefits
of thin-body silicon-on-insulator devices, combined with a
workfunction engineered mid-gap metal gate.

Introduction

Ultra-low-power transistors are an enabling technology for many proposed applications.

Ubiquitous sensor networks, RFID tags, implanted medical devices, portable biosensors,
handheld devices, and space-based applications are among those which would benefit
from extremely low power circuits (1-3). Other applications include energy-harvesting
devices which recharge batteries by scavenging power from motion or solar cells, such as
a recently demonstrated wristwatch design requiring a maximum 50nA of on-current at
0.42 V operation (4-5). In general, low standby power (LSTP) applications require less
than 100 pA/μm leakage current, while maximizing the on-current at a modest power
supply voltage.

Subthreshold operation transistors hold great promise for integration into ultra-low-
power designs. The most efficient way to reduce power is to reduce the operating voltage
(6). With an operating voltage of 0.3 V, and an on-current of less than 1 μA/μm,
subthreshold transistors use orders of magnitude less power than transistors operated in
strong inversion. Subthreshold operation also provides the highest transconductance (gm)
for a given drain current (7). In subthreshold conduction is by diffusion rather than drift,
which implies that it is possible to have equal NMOS and PMOS drive currents per
micrometer of transistor width. This allows equal sizing of NMOS and PMOS transistors
(in contrast to the typical 2x wider PMOS transistor size for conventional devices) which
would then allow reduced circuit area and device capacitance.

1
This work was sponsored by the Air Force under contract #FA8721-05-C-0002. Opinions, interpretations,
conclusions, and recommendations are those of the author and are not necessarily endorsed by the United
States Government.

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 ECS Transactions, 35 (5) 179-188 (2011)

Simply lowering the operating voltage of a conventional high-performance transistor

will not produce very good device performance in subthreshold operation. Conventional
transistors will have comparatively high off-state leakage and overlap capacitance, as
well as poorer subthreshold slope. By designing a fabrication process from the substrate
material through the interconnect metal, optimized for subthreshold transistor
performance, it is possible to realize a device with the minimum switching energy and
off-state current without significant impact to the energy-delay product. This paper
explores advantages of SOI technology in ultra-low power applications, and details the
processing techniques used to optimize the devices for subthreshold operation.

Bulk silicon vs. SOI

SOI-based CMOS is commonly used today in high performance applications, such as

gaming consoles (5). Though double gate designs (including FinFETs) can provide
improved channel control and lower leakage, (8) the high cost associated with the
significant increase in process integration complexity makes them less desirable for ultra-
low-power electronics. To introduce ultra-low-power process technology in the shortest
practical timeframe, it is appropriate to consider planar architectures.

The benefits and disadvantages of SOI vs. bulk silicon technology have been
discussed many times (2,4,9-10). Compared to bulk silicon, SOI provides up to 90%
lower junction capacitance, near-ideal subthreshold swing, reduced device cross-talk,
lower junction leakage, no latch-up, increased radiation hardness, and full dielectric
isolation of the transistor. The low junction capacitance is extremely valuable to ultra-
low-power devices, as it allows reduction of the CV2 switching energy of the transistor.
Another significant advantage for low-power operation is that SOI devices do not suffer
from substrate reverse bias effects, in that the depletion charge does not increase when a
source potential is applied. Thin-body SOI also provides better electrostatic channel
control, leading to reduced source-to-drain leakage and reduced short channel effects
(SCE) (8). In contrast, it has been suggested that bulk silicon is now facing GIDL limits
with device scaling, making it inappropriate for ultra-low-power applications (5).

SOI technology can be fully depleted (FDSOI) or partially depleted (PDSOI). The
depletion depth is given by:

4εΦ f
Tdep = (1)
qN ch

where Φf = kTln(Nch/ni)/q is the Fermi potential, Nch is the channel doping concentration,
and ni is the intrinsic carrier concentration (6). When the depletion depth is larger than
the physical silicon thickness, a neutral region no longer exists between the source and
drain, and the silicon becomes fully depleted (4). For a highly doped channel where Nch =
1x1018 cm-3, Tdep = 32nm by Equation (1).

FDSOI is more difficult to fabricate than PDSOI, as the silicon channel must be
reduced to a very small and well-controlled thickness. Another disadvantage is that
series resistance in thin FDSOI can be a significant issue (11). Further, unlike a PDSOI
device, the FDSOI device is very susceptible to charge in the BOX layer, which can

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 ECS Transactions, 35 (5) 179-188 (2011)

capacitively couple through the depleted silicon of the body, changing the front channel
threshold voltage. However, FDSOI also has many important advantages over PDSOI,
such as higher gm and reduction of floating body effects including transient Vt shifts and
the kink effect (4,7,11).

For subthreshold transistors, the most important FDSOI advantage is the near-ideal
subthreshold swing. The drive current in the subthreshold regime is given by:

I sub = I o x10([Vgs +ηVds ] / S ) x(1 − e −Vds / Uth ) (2)

where Io is a function of the transistor L and W, η is the DIBL factor, S is the

subthreshold swing, and Uth is the thermal voltage (1). Note that subthreshold transistor
performance is a strong function of η and S in Equation (2), and will be very sensitive to
short channel effects (SCE) since both η and S increase as gate length decreases. Buried
oxide (BOX) thickness can be varied to achieve a tradeoff between on-current and off-
current; thinner BOX improves DIBL but degrades S (1). Simulations using the Atlas
device simulator predict that at low operating voltages (Vdd = 0.3 V), FDSOI devices still
provide a superior subthreshold slope to bulk silicon devices, as shown in Figure 1.
Therefore an optimized ultra-low-power process technology will greatly benefit from the
lower subthreshold swing and capacitances provided by FDSOI.

Channel Doping

The threshold voltage is a strong function of silicon film thickness when using FDSOI
with highly doped channels. Vt changes by approximately 4 mV per 1 nm silicon
thickness when the doping level is 1x1017 cm-3 (12). By comparison, when the channel
doping is extremely low, below ~5x1015 cm-3, Vt is effectively independent of silicon
film thickness. Since Vt control is critical for subthreshold transistors, it is highly
desirable to use undoped (or more precisely, lightly doped) FDSOI, particularly for
highly scaled designs (11).

An undoped channel has additional benefits, including no Vt variation due to random

dopant fluctuations, as well as higher carrier mobility. Unlike bulk silicon which requires
higher channel doping to control the SCEs as gate length scales, thin-body FDSOI is less
sensitive to SCEs, and enables the use of undoped channels (8). In addition, the depletion
thickness given by Equation (1) is large when the channel is undoped, which allows a
more manufacturable silicon thickness to be used while maintaining the benefits of a
FDSOI as opposed to a PDSOI device. Furthermore, low channel doping will reduce
band-to-band tunneling and increase the S/D breakdown voltage, which could be
important when integrating 3.3V I/O transistors on the same chip as the subthreshold
transistors (2,11).

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 ECS Transactions, 35 (5) 179-188 (2011)

10-3
VDS=300 mV

10-5

ID (A/µm)
10-7

10-9
Bulk
FDSOI
10-11
0 0.1 0.2 0.3 0.4 0.5
VGS (V)

Figure 1: Simulation of ultra low power transistors, for 65nm gate length. FDSOI exhibits
improved subthreshold slope and thus a 2.5x improvement in Ion/Ioff ratio at 0.3V
operating voltage compared to bulk silicon.

Gate Materials

When simplified to ignore back-channel and short channel effects, the threshold voltage
of an SOI transistor is given by:

Vt = φms + 2Φ f −
1
Cox
(
Qit + q ∫o ρ ( x )dx − qN ch t soi
t
) (3)

where Φms is the gate-to-semiconductor workfunction difference, Cox is the gate dielectric
capacitance, Qit is the dielectric interface charge, ρ(x) is the charge density in the
dielectric, and tsoi is the silicon thickness. When Nch is high, Vt is a sensitive function of
tsoi, which is a drawback for thin FDSOI. However, when the channel is undoped, the
Fermi potential and the depletion charge are approximately zero, and the expression for
the threshold voltage becomes:

Qf
Vt = φms − (4)
Cox

where Qf is the total charge in the gate dielectric. Thus the threshold voltage of the
transistor is essentially set by the gate workfunction.

Figure 2 shows a graphical representation of Equation (3), illustrating Vt as a

function of Nch for N+ poly, P+ poly, and mid-gap gates (10). There are two solutions for
achieving a threshold voltage of ~0.35 V, band-edge gate materials with high channel
doping (1x1018 cm-3), or a mid-gap gate material with very low channel doping (1x1015
cm-3). As described in Section III, the undoped channel solution is preferred for
subthreshold optimized transistors.

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 ECS Transactions, 35 (5) 179-188 (2011)

1.5 1.0

PMOS Threshold Voltage (V)

NMOS Threshold Voltage (V)
1.0 P+ poly Si 0.5

0.5 Midgap 0.0

Target
0.0 -0.5
N+ poly Si

-0.5 -1.0
NMOS
PMOS
-1.0 -1.5
1014 1015 1016 1017 1018 1019
Channel Doping (cm-3)

Figure 2: Threshold voltages of FDSOI NMOS and PMOS with mid-gap, N+ poly, and P+
poly gates as a function of SOI doping concentration. 10-nm thick SOI and 5-nm gate
oxide are assumed. From Shimada (10).

Therefore, a workfunction-engineered mid-gap metal gate material should be used

to provide symmetric threshold voltages for NMOS and PMOS. There are several
literature examples of successful integration of mid-gap metal gate transistors, including
SiGe, Ta , and TiN. (12-17) A metal gate stack typically consists of a thin metal layer
sandwiched between a thicker polysilicon layer above, and the gate dielectric below. The
gate dielectric may be a conventional SiO2 or SiON gate oxide, or a high-k gate dielectric
such as HfSiON. To prevent GOI issues, it is important that there is little diffusion of
metal into the gate dielectric, or reaction between the metal and the dielectric. It is also
important to minimize trapped charges in the gate dielectric during plasma sputtering of
the metal gate material, which can shift the Vt of the transistor according to Equation 4.
Such charging effects have been noted after Ta gate deposition by Ar+ sputtering, where
an oxide charge density of 5x1011 cm-2 caused a 0.1 V shift in Vt (10).

TiN is a suitable mid-gap metal gate material, with the advantage of being already
commonplace in the backend of fabrication flows. A gate stack was fabricated using
4nm-thick SiO2, 20nm-thick TiN, and 200nm-thick polysilicon. Large (1 mm2) capacitors
were then phosphorous doped and capped with 250nm Al. Figure 3 shows C-V curves
comparing poly and two TiN gates with different N2 flow during TiN PVD. The curves
are fit with a quantum-corrected capacitor model from NCSU (18) to extract
workfunction, equivalent oxide thickness (EOT), and other parameters. The workfunction
of the TiN gates increases toward mid-gap compared to the N+ poly gates, with Φm =
4.45eV and 4.60 eV for 100% N2 flow and 66% N2 flow (balance Ar) during TiN
deposition. To increase Φm further, several post-deposition TiN anneal experiments were
performed. A sub-atmospheric 626oC N2 anneal after TiN deposition increases Φm by
0.10-0.15eV, enabling tuning of the effective workfunction across the mid-gap range.

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 ECS Transactions, 35 (5) 179-188 (2011)

10000
Polysilicon
8000 TiN - 100% N2

Capacitance (pF)
TiN - 67% N2
6000

4000

2000

0
-4 -3 -2 -1 0 1 2 3
Gate Voltage (V)

Figure 3: MOS capacitors with TiN metal gates under two different TiN deposition
conditions, and a polysilicon gate. TiN gates show an increase in flatband voltage, and
thus Φms, toward the silicon mid-gap, as well as increased capacitance due to elimination
of poly depletion. Lines are quantum-corrected model fits to the data.

Etching the TiN gate metal without damaging the polysilicon above the TiN or
the gate dielectric below requires a delicate balance of plasma processing conditions.
Lateral etching or notching of the overlying polysilicon could lead to undesirable
penetration of implant species into the active channel beneath the gate, causing severe
SCE’s. Notching of the metal gate may lead to similar implant issues, as well as
delamination of the narrower gates. A large foot on the metal must be avoided, as this
will cause an undesirable increase in Cgd. Plasma etching selectivity to the underlying
gate dielectric material is crucial, as punch-through of the thin gate dielectric will cause
severe leakage or complete failure of the thin FDSOI device. Microloading effects must
be minimized, to ensure that both dense and isolated gates have similar critical dimension
(CD) and profile, in order to reduce variation in the transistor parametrics across the chip.

Source/ Drain Underlap Optimization

Eliminating the S/D extension implants (LDD implants) and increasing the spacer
thickness results in a gate-to-S/D underlap which provides several benefits for ultra low
power operation. Most importantly, reduced overlap capacitance will allow lower CV2
switching energy. In addition, increased spacer thickness will reduce subthreshold
leakage, gate leakage, and DIBL. Simulations have shown that an optimized underlap can
yield a 70% reduction in SRAM cell leakage and 200x lower cell read failure probability
(8). Since channel hot carrier (CHC) effects are not significant at low Vdd, the LDD
implants are not required to mitigate gate oxide integrity (GOI) issues.

Simulations of NMOS and PMOS Id-Vg curves for an xLP device at various gate-to-
S/D underlap distances demonstrate that an optimized subthreshold slope and off-current
occur for a 60 nm underlap. Figure 5 compares experimental C-V curves from
conventional devices, and subthreshold-optimized devices with a 60 nm gate-to-S/D
underlap. The capacitance for the underlapped devices is reduced by 71%. Connelly has
also described the use of an underlapped S/D technology for ultra-low-power FDSOI,
though in that case the underlap was only 4 – 9 nm (19). That work also proposed the use
of Schottky S/D to reduce the parasitic resistance of thin-body SOI.

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 ECS Transactions, 35 (5) 179-188 (2011)

3.0
Experimental
2.5 Simulation

Capacitance (fF/μm)
2.0

1.5

Conventional
1.0 0.89 fF/μm

0.5 xLP
0.26 fF/μm

0.0
-2.0 -1.5 -1.0 -0.5 0.0
Vg (V)

Fig. 5. Comparison of total gate-to-S/D overlap capacitance of conventional and ultra-

low power (xLP) PMOS transistors. Lg = 180 nm, W = 100 μm. Solid lines: Measured
data, dashed lines: Atlas model simulation. xLP underlap design reduces capacitance by
71% compared to the standard transistor design

Because of the gate-to-S/D underlap, carrier injection into the channel relies on
diffusion from the source. Simulations provided in Figure 6 predict that heavy channel
doping causes the drive current to collapse under these conditions, so the channel doping
must be kept very light, which is consistent with the requirements for threshold voltage.

10-5

10-7
ID (A/µm)

10-9
1015
1016
10-11 1017
2x1017
3x1017
5x1017
10-13
-0.5 -0.3 -0.1 0.1 0.3 0.5
VG (V)

Figure 6: Model NMOS transistor I-V characteristics for 150nm polysilicon gate xLP
FDSOI device as a function of body doping (atoms/cm3). Increasing body doping causes
a strong decrease in drive current.

To summarize, a schematic comparison between conventional and subthreshold-

optimized ultra-low-power transistors is shown in Figure 7, illustrating the undoped body,
elimination of S/D extension implants, and wide spacers.

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 ECS Transactions, 35 (5) 179-188 (2011)

Poly-Si Poly-Si
Gate Wide
spacer TiN

No Undoped
Extensions Doped body extensions body Underlap

Standard FDSOI xLP FDSOI

Figure 7: Schematic of standard FDSOI and subthreshold-optimized (xLP) ultra-low-

power FDSOI transistors.

Interconnect Optimization

The current through the interconnect routing will be relatively small for ultra-low-power
circuits, and the standard interconnect metallization will be significantly oversized. At
low current densities, electromigration is not a serious issue, nor is ohmic heating. It is
therefore possible to reduce the capacitance of the circuit further by reducing the
thickness of the interconnect metal. The increase in interconnect resistance is not
significant, since the resistance of the transistor will be much larger than that of the
interconnects due to the subthreshold operation.

Though the maximum possible reduction in interconnect thickness will depend on the
details of the individual circuit design, a 50% reduction is conservative for most cases.
Device simulations have been performed on a transistor driving a given length of
interconnect to calculate the CV2 switching energy and the characteristic switching time
of the device, given by tc = (Rd + Rm)(Cd + Cm), where d and m indicate the device and
interconnect metal, respectively. A 50% reduction in interconnect metal thickness
reduces tc by 40%. The simulation predicts that the total CV2 switching energy of the
optimized FDSOI ultra-low-power device is reduced by 97% compared to a traditional
1.2V transistor.

Subthreshold Optimized Transistor Performance

FDSOI ultra-low-power transistors were fabricated with the integration optimized for
subthreshold operation as outlined above. NMOS and PMOS Id-Vg characteristics are
shown in Figure 8, for mid-gap metal gate transistors with Lg = 150 nm and W = 8 μm.
Nitride spacer thickness is 90 nm, yielding a 60 nm gate-to-S/D underlap after a 10 s,
1000oC activation anneal. The TiN gate workfunction tuning provides closely matched
NMOS and PMOS Ion (Vg = +/- 0.3 V) and Ioff (Vg = 0 V) performance. It has been
proposed that a suitable leakage limit for ultra-low-power handheld electronics is 20-50
pA/μm, (5) which is well above the 4 pA/μm off-current of these FDSOI subthreshold-
optimized transistors.

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 ECS Transactions, 35 (5) 179-188 (2011)

10-4

10-6

Ids (A/um)
10-8

10-10
Vdd = 0.05 V
Ioff = 4 pA/µm Vdd = 0.3 V
10-12
-2.0 -1.0 0.0 1.0 2.0
Vg (V)

Figure 8. Representative xLP transistor I-V curves with a 150 nm TiN metal gate (W = 8
μm), showing good subthreshold performance, and nearly ideal workfunction tuning.

The subthreshold swing (S) for long-channel mid-gap gate ultra-low-power

transistors (Lg = 500 nm) nearly ideal at 64 mV/decade. As the gate length decreases, S
increases to 80 mV/decade due to SCE. The subthreshold swing is smaller for PMOS
than for NMOS due to the difference in effective channel length for these underlapped
devices; under the current process conditions, the As implant used for NMOS apparently
diffuses farther than the B PMOS implant resulting in a shorter NMOS channel for a
given gate length.

Conclusions and Future Directions

Scaling gate length while maintaining reliable device performance is as challenging for
ultra-low-power transistor design as it is for high-performance transistors. For gate
lengths below 100nm, SCE’s will increase DIBL and subthreshold swing unless the
silicon channel thickness is also scaled reduced to ultra-thin values below 15 nm (11). At
very thin silicon thicknesses, quantization effects have significant effects and Vt is again
a function of tSi. Mobility is also degraded, due to higher phonon and surface scattering.
If a practical silicon thickness limit of 5 nm is assumed, the minimum gate length which
allows acceptable ultra-low-power performance is 25 – 30 nm (11). Beyond this, non-
planar devices with enhanced channel control such as FinFETs may be required. Dual- or
tri- gate designs will provide better electrostatic control of the channel, minimizing
SCE’s. Looking forward to these double gate designs, it has been shown that a mid-gap
double gate will have lower subthreshold leakage and gate leakage than designs with
band-edge gates (8).

The performance of subthreshold-optimized transistors has been demonstrated to

meet ultra-low-power performance requirements. By designing the transistor from the
substrate through the interconnect levels for subthreshold operation, the switching energy
of the device is decreased by 97% with modest impact to the energy-delay product. SOI-
based devices have significant advantages over bulk silicon devices for sub-threshold
operation. Widespread adoption of FDSOI technology will require significant
performance advantage over bulk silicon to justify the higher cost of the SOI substrate
and the additional processing steps associated with thinning and control of the active
silicon thickness. The processing technology for subthreshold-optimized transistors

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 ECS Transactions, 35 (5) 179-188 (2011)

described in this paper has enabled the verification of some of the performance advantage
of FDSOI devices necessary for ultra-low power designs.

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