ARM Cortex M

5/1/2018 ARM Cortex-M - Wikipedia
ARM Cortex-M
The ARM Cortex-M is a group of 32-bit RISC ARM
processor cores licensed by Arm Holdings. The cores
are intended for microcontroller use. The cores consist
of the Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3,
Cortex-M4, Cortex-M7, Cortex-M23, Cortex-
M33.[1][2][3][4][5][6][7] The Cortex-M4 / M7 / M33 cores
have an FPU option, and these cores are known as
ARM Cortex-M0 and Cortex-M3 microcontroller ICs from
"Cortex-Mx with FPU" or Cortex-MxF, where 'x' is the
NXP and Silicon Labs (Energy Micro)
core number. ARM Cortex-M cores have been shipped
in tens of billions of devices.[8]
Contents
Overview
License
Silicon customization
Instruction sets
Deprecations
Cortex-M0
Chips
Cortex-M0+
Chips Die from a STM32F100C4T6B IC.
24 MHz ARM Cortex-M3
Cortex-M1 microcontroller with 16 KB flash
Chips memory, 4 KB RAM. Manufactured
Cortex-M3 by STMicroelectronics.
Chips
Cortex-M4
Chips
Cortex-M7
Chips
Cortex-M23
Chips
Cortex-M33
Chips
Development tools
Documentation
See also
References
Further reading
External links
https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M0+ 1/21
Overview
The ARM Cortex-M family are ARM microprocessor cores which are designed for use in
microcontrollers, ASICs, ASSPs, FPGAs, and SoCs. Cortex-M cores are commonly used as Announced
dedicated microcontroller chips, but also are "hidden" inside of SoC chips as power Year Core
management controllers, I/O controllers, system controllers, touch screen controllers, smart 2004 Cortex-M3
battery controllers, and sensors controllers.
2007 Cortex-M1
Though 8-bit microcontrollers were very popular in the past, Cortex-M has slowly been 2009 Cortex-M0
chipping away at the 8-bit market as the prices of low-end Cortex-M chips have moved
2010 Cortex-M4(F)
downward. Cortex-M have become a popular replacements for 8-bit chips in applications that
2012 Cortex-M0+
benefit from 32-bit math operations, and replacing older legacy ARM cores such as ARM7 and
ARM9. 2014 Cortex-M7(F)
2016 Cortex-M23
2016 Cortex-M33(F)
License
Arm Holdings neither manufactures nor sells CPU devices based on its own designs, but rather
licenses the processor architecture to interested parties. Arm offers a variety of licensing terms, varying in cost and
deliverables. To all licensees, Arm provides an integratable hardware description of the ARM core, as well as complete
software development toolset and the right to sell manufactured silicon containing the ARM CPU.
Silicon customization
Integrated device manufacturers (IDM) receive the ARM Processor IP as synthesizable RTL (written in Verilog). In this
form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to
achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions,
optimizations for size, debug support, etc. To determine which components have been included in a particular ARM CPU
chip, consult the manufacturer datasheet and related documentation.
Some of the most important options for the Cortex-M cores are:
SysTick timer: A 24-bit system timer that extends the functionality of both the processor and the Nested Vectored
Interrupt Controller (NVIC). When present, it also provides an additional configurable priority SysTick interrupt.[9][10][11]
Though the SysTick timer is optional, it is very rare to find a Cortex-M microcontroller without it. If a Cortex-M33
microcontroller has the Security Extension option, then it has two SysTicks, one Secure and one Non-secure.
Bit-Band: Maps a complete word of memory onto a single bit in the bit-band region. For example, writing to an alias
word will set or clear the corresponding bit in the bit-band region. This allows every individual bit in the bit-band region
to be directly accessible from a word-aligned address, and individual bits to be toggled from C/C++ without performing
a read-modify-write sequence of instructions.[9][10][11] Though the bit-band is optional, it is less common to find a
Cortex-M3 and Cortex-M4 microcontroller without it. Some Cortex-M0 and Cortex-M0+ microcontrollers have bit-
band.
Memory Protection Unit (MPU): Provides support for protecting regions of memory through enforcing privilege and
access rules. It supports up to eight different regions, each of which can be split into a further eight equal-size sub-
regions.[9][10][11]
Tightly-Coupled Memory (TCM): Low-latency RAM that is used to hold critical routines, data, stacks. It is typically the
fastest memory in the microcontroller.
ARM Cortex-M optional components

Cortex Cortex Cortex Cortex Cortex Cortex Cortex Cortex
ARM Core
M0[1] M0+[2] M1[3] M3[4] M4[5] M7[6] M23[7] M33[12]
SysTick 24-bit Optional Optional Optional Yes Yes Yes Optional Yes
Timer (0,1) (0,1) (0,1) (1) (1) (1) (0,1,2) (1,2)
Single-cycle I/O
No Optional No No No No Optional No
port
Bit-Band memory No[13] No[13] No* Optional Optional No No No
Memory Protection Optional Optional Optional Optional Optional Optional

No No
Unit (MPU) (0,8) (0,8) (0,8) (0,8,16) (0,4,8,12,16) (0,4,8,12,16)
Security Attribution Optional Optional
No No No No No No
Unit (SAU) (0,4,8) (0,4,8)
Instruction TCM No No Optional No No Optional No TBD
Data TCM No No Optional No No Optional No TBD
Instruction Cache No[14] No[14] No[14] No[14] No[14] Optional No TBD
Data Cache No[14] No[14] No[14] No[14] No[14] Optional No TBD
Vector Table Offset Optional Optional Optional Optional Optional Optional Yes
No
Register (VTOR) (0,1) (0,1) (0,1) (0,1) (0,1) (0,1,2) (1,2)
Note: Most Cortex-M3 and M4 chips have bit-band and MPU. The bit-band option can be added to the M0/M0+ using
the Cortex-M System Design Kit.[13]
Note: Software should validate the existence of a feature before attempting to use it.[11]
Additional silicon options:[9][10]
Data endianness: Little-endian or big-endian. Unlike legacy ARM cores, the Cortex-M is permanently fixed in silicon
as one of these choices.
Interrupts: 1 to 32 (M0/M0+/M1), 1 to 240 (M3/M4/M7/M23), 1 to 480 (M33).
Wake-up interrupt controller: Optional.
Vector Table Offset Register: Optional. (not available for M0).
Instruction fetch width: 16-bit only, or mostly 32-bit.
User/privilege support: Optional.
Reset all registers: Optional.
Single-cycle I/O port: Optional. (M0+/M23).
Debug Access Port (DAP): None, SWD, JTAG and SWD. (optional for all Cortex-M cores)
Halting debug support: Optional.
Number of watchpoint comparators: 0 to 2 (M0/M0+/M1), 0 to 4 (M3/M4/M7/M23/M33).
Number of breakpoint comparators: 0 to 4 (M0/M0+/M1/M23), 0 to 8 (M3/M4/M7/M33).
Instruction sets
The Cortex-M0 / M0+ / M1 implement the ARMv6-M architecture,[9] the Cortex-M3 implements the ARMv7-M
architecture,[10] and the Cortex-M4 / Cortex-M7 implements the ARMv7E-M architecture.[10] The architectures are
binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available for the
Cortex-M0 / Cortex-M0+ / Cortex-M1 can execute without modification on the Cortex-M3 / Cortex-M4 / Cortex-M7.
Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4 / Cortex-M7 / Cortex-
M33.[9][10] Only Thumb-1 and Thumb-2 instruction sets are supported in Cortex-M architectures, but the legacy 32-bit
ARM instruction set isn't supported.
All six Cortex-M cores implement a common subset of instructions that consists of most Thumb-1, some Thumb-2,
including a 32-bit result multiply. The Cortex-M0 / Cortex-M0+ / Cortex-M1 / Cortex-M23 were designed to create the
smallest silicon die, thus having the fewest instructions of the Cortex-M family.
The Cortex-M0 / Cortex-M0+ / Cortex-M1 include Thumb-1 instructions, except new instructions (CBZ, CBNZ, IT) which
were added in ARMv7-M architecture. The Cortex-M0 / Cortex-M0+ / Cortex-M1 include a minor subset of Thumb-2
instructions (BL, DMB, DSB, ISB, MRS, MSR). The Cortex-M3 / M4 / M7 / M33 have all base Thumb-1 and Thumb-2
instructions. The Cortex-M3 adds three Thumb-1 instructions, all Thumb-2 instructions, hardware integer divide, and
saturation arithmetic instructions. The Cortex-M4 adds DSP instructions and an optional single-precision floating-point
unit (VFPv4-SP). The Cortex-M7 adds an optional double-precision FPU (VFPv5).[9][10]
ARM Cortex-M instruction variations

Cortex Cortex Cortex Cortex Cortex Cortex Cortex Cortex
Arm Core
M0[1] M0+[2] M1[3] M3[4] M4[5] M7[6] M23[7] M33[12]
ARMv6- ARMv6- ARMv6- ARMv7- ARMv7E- ARMv7E- ARMv8- ARMv8-
ARM architecture
M[9] M[9] M[9] M[10] M[10] M[10] M[15] M[15]
Computer Von Von Von Von
Harvard Harvard Harvard Harvard
architecture Neuman Neumann Neumann Neumann
Instruction
3 stages 2 stages 3 stages 3 stages 3 stages 6 stages 2 stages 3 stages
pipeline
Thumb-1
Most Most Most Entire Entire Entire Most Entire
instructions
Thumb-2
Some Some Some Entire Entire Entire Some Entire
instructions
32-bit 32-bit 32-bit 32-bit
Multiply 32-bit 32-bit 32-bit result result result 32-bit result
instructions result result result 64-bit 64-bit 64-bit result 64-bit
result result result result
Divide
No No No Yes Yes Yes Yes Yes
instructions
Saturated
No No No Some Yes Yes No Yes
instructions
DSP instructions No No No No Yes Yes No Optional
Optional:
Floating-point Optional: SP Optional:
No No No No No
instructions SP or SP & SP
DP
TrustZone
No No No No No No Optional Optional
instructions
Note: The Cortex-M0 / M0+ / M1 doesn't include these 16-bit Thumb-1 instructions: CBZ, CBNZ, IT.[9][10]
Note: The Cortex-M0 / M0+ / M1 only include these 32-bit Thumb-2 instructions: BL, DMB, DSB, ISB, MRS,
MSR.[9][10]
Note: The Cortex-M0 / M0+ / M1 / M23 only has 32-bit multiply instructions with a lower-32-bit result (32bit × 32bit =
lower 32bit), where as the Cortex-M3 / M4 / M7 / M33 includes additional 32-bit multiply instructions with 64-bit results
(32bit × 32bit = 64bit). The Cortex-M4 / M7 / M33 also include DSP instructions for (16bit × 16bit = 32bit), (32bit ×
16bit = upper 32bit), (32bit × 32bit = upper 32bit) multiplications. If a smaller silicon die is required, the Cortex-M0 /
M0+ / M1 has an option to be a much slower instruction, though it is rarely implemented in the M0 or M0+.[9][10]
Note: The Cortex-M4 and M33 has a silicon FPU option of single-precision (SP). The Cortex-M7 has silicon FPU
options of single-precision (SP), or both single-precision (SP) and double-precision (DP). If the Cortex-M4 / M7 / M33
has a FPU, then it is known as the Cortex-M4F / Cortex-M7F / Cortex-M33F.[9][10]

Note: The Cortex-M series includes three new 16-bit Thumb-1 instructions for sleep mode: SEV, WFE, WFI.
ARM Cortex-M instruction groups

Instr Cortex Cortex Cortex Cortex Cortex Cortex Cortex Cortex
Group Instructions
bits M0 M0+ M1 M3 M4 M7 M23 M33
ADC, ADD,
ADR, AND,
ASR, B,
BIC, BKPT,
BLX, BX,
CMN, CMP,
CPS, EOR,
LDM, LDR,
LDRB,
LDRH,
LDRSB,
LDRSH,
LSL, LSR,
MOV, MUL,
MVN, NOP,
Thumb-1 16 Yes Yes Yes Yes Yes Yes Yes Yes
ORR, POP,
PUSH, REV,
REV16,
REVSH,
ROR, RSB,
SBC, SEV,
STM,
STMIA,
STR, STRB,
STRH, SUB,
SVC, SXTB,
SXTH, TST,
UXTB,
UXTH, WFE,
WFI, YIELD
Thumb-1 16 CBNZ, CBZ No No No Yes Yes Yes Yes Yes
Thumb-1 16 IT No No No Yes Yes Yes No Yes
BL, DMB,
Thumb-2 32 DSB, ISB, Yes Yes Yes Yes Yes Yes Yes Yes
MRS, MSR
Thumb-2 32 ADC, ADD, No No No Some Yes Yes No Yes
ADR, AND,
ASR, B,
BFC, BFI,
BIC, CDP,
CLREX,
CLZ, CMN,
CMP, DBG,
EOR, LDC,
LDMA,
LDMDB,
LDR, LDRB,
LDRBT,
LDRD,
LDREX,
LDREXB,
LDREXH,
LDRH,
LDRHT,
LDRSB,
LDRSBT,
LDRSHT,
LDRSH,
LDRT, MCR,
LSL, LSR,
MLS,
MCRR,
MLA, MOV,
MOVT,
MRC,
MRRC,
MUL, MVN,
NOP, ORN,
ORR, PLD,
PLDW, PLI,
POP, PUSH,
RBIT, REV,
REV16,
REVSH,
ROR, RRX,
RSB, SBC,
SBFX, SEV,
SMLAL,
SMULL,
SSAT, STC,
STMDB,
STR, STRB,
STRBT,
STRD,
STREX,
STREXB,
STREXH,
STRH,
STRHT,
STRT, SUB,
SXTB,
SXTH, TBB,
TBH, TEQ,
TST, UBFX,
UMLAL,
UMULL,
USAT,
UXTB,
UXTH, WFE,
WFI, YIELD
Thumb-2 32 SDIV, UDIV No No No Yes Yes Yes Yes Yes
DSP 32 PKH, No No No No Yes Yes No Optional
QADD,
QADD16,
QADD8,
QASX,
QDADD,
QDSUB,
QSAX,
QSUB,
QSUB16,
QSUB8,
SADD16,
SADD8,
SASX, SEL,
SHADD16,
SHADD8,
SHASX,
SHSAX,
SHSUB16,
SHSUB8,
SMLABB,
SMLABT,
SMLATB,
SMLATT,
SMLAD,
SMLALBB,
SMLALBT,
SMLALTB,
SMLALTT,
SMLALD,
SMLAWB,
SMLAWT,
SMLSD,
SMLSLD,
SMMLA,
SMMLS,
SMMUL,
SMUAD,
SMULBB,
SMULBT,
SMULTT,
SMULTB,
SMULWT,
SMULWB,
SMUSD,
SSAT16,
SSAX,
SSUB16,
SSUB8,
SXTAB,
SXTAB16,
SXTAH,
SXTB16,
UADD16,
UADD8,
UASX,
UHADD16,
UHADD8,
UHASX,
UHSAX,
UHSUB16,
UHSUB8,
UMAAL,
UQADD16,
UQADD8,
UQASX,
UQSAX,
UQSUB16,
UQSUB8,
USAD8,
USADA8,
USAT16,
USAX,
USUB16,
USUB8,
UXTAB,
UXTAB16,
UXTAH,
UXTB16
SP Float 32 VABS, No No No No Optional Optional No Optional
VADD, SP FPU SP FPU SP FPU
VCMP,
VCMPE,
VCVT,
VCVTR,
VDIV,
VLDM,
VLDR,
VMLA,
VMLS,
VMOV,
VMRS,
VMSR,
VMUL,
VNEG,
VNMLA,
VNMLS,
VNMUL,
VPOP,
VPUSH,
VSQRT,
VSTM,
VSTR,
VSUB
VCVTA,
VCVTM,
VCVTN,
VCVTP,
VMAXNM,
VMINNM,
VRINTA, Optional
DP Float 32 No No No No No No No
VRINTM, DP FPU
VRINTN,
VRINTP,
VRINTR,
VRINTX,
VRINTZ,
VSEL
BLXNS,
TrustZone 16 No No No No No No Optional Optional
BXNS
SG, TT, TTT,
TrustZone 32 No No No No No No Optional Optional
TTA, TTAT
Note: The single-precision (SP) FPU instructions are valid in the Cortex-M4/M7/M33 only when the SP FPU option
exists in the silicon.
Note: The double-precision (DP) FPU instructions are valid in the Cortex-M7 only when the DP FPU option exists in
the silicon.
Deprecations
The ARM architecture for ARM Cortex-M series removed some features from older legacy cores:[9][10]
The 32-bit ARM instruction set is not included in Cortex-M cores.

Endianness is chosen at silicon implementation in Cortex-M cores. Legacy cores allowed "on-the-fly" changing of the
data endian mode.
Co-processors aren't supported on Cortex-M cores.
The capabilities of the 32-bit ARM instruction set is duplicated in many ways by the Thumb-1 and Thumb-2 instruction
sets, but some ARM features don't have a similar feature:
The SWP and SWPB (swap) ARM instructions don't have a similar feature in Cortex-M.
The 16-bit Thumb-1 instruction set has evolved over time since it was first released in the legacy ARM7T cores with the
ARMv4T architecture. New Thumb-1 instructions were added as each legacy ARMv5 / ARMv6 / ARMv6T2 architectures
were released. Some 16-bit Thumb-1 instructions were removed from the Cortex-M cores:
"BLX <immediate>" instruction doesn't exist because it was used to switch from Thumb-1 to ARM instruction set. The
"BLX <register>" instruction is still available in the Cortex-M.
SETEND doesn't exist because on-the-fly switching of data endian mode is no longer supported.
Co-processor instructions are not supported.
SWI instruction was renamed to SVC instruction, though the instruction binary coding is the same. However, the SVC
handler code is different than SWI handler because of changes to the exception models.
Cortex-M0
The Cortex-M0 core is optimized for small silicon die size and use in the lowest
Cortex-M0
price chips.
Instruction set Thumb-1
Key features of the Cortex-M0 core are:[1] (most),
Thumb-2
ARMv6-M architecture[9]
(some)
3-stage pipeline.
Instruction sets: Microarchitecture ARMv6-M
Thumb-1 (most), missing CBZ, CBNZ, IT.

Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.
32-bit hardware integer multiply with 32-bit result.
1 to 32 interrupts, plus NMI.
Silicon options:
Hardware integer multiply speed: 1 or 32 cycles.
Chips
The following microcontrollers are based on the Cortex-M0 core:
Cypress PSoC 4, 4M, 4L

Infineon XMC1000
Nordic nRF51
NXP LPC1100, LPC1200
nuvoTon NuMicro M0 Family
Sonix SN32F700
STMicroelectronics STM32 F0
Toshiba TX00
Vorago VA10800 (extreme temperature), VA10820 (radiation hardened)
The following chips have a Cortex-M0 as a secondary core:
NXP LPC4300 (one Cortex-M4F + one Cortex-M0)

Texas Instruments SimpleLink Wireless MCUs CC1310 and CC2650 (one programmable Cortex-M3 + one Cortex-M0
network processor + one proprietary Sensor Controller Engine)
Cortex-M0+
The Cortex-M0+ is an optimized superset of the Cortex-M0. The Cortex-M0+ Cortex-M0+

has complete instruction set compatibility with the Cortex-M0 thus allowing
the use of the same compiler and debug tools. The Cortex-M0+ pipeline was
(most),
reduced from 3 to 2 stages, which lowers the power usage. In addition to debug
Thumb-2
features in the existing Cortex-M0, a silicon option can be added to the Cortex-
(some)
M0+ called the Micro Trace Buffer (MTB) which provides a simple instruction
Microarchitecture ARMv6-M
trace buffer. The Cortex-M0+ also received Cortex-M3 and Cortex-M4
features, which can be added as silicon options, such as the memory protection
unit (MPU) and the vector table relocation.[2]
Key features of the Cortex-M0+ core are:[2]
ARMv6-M architecture[9]
2-stage pipeline (one fewer than Cortex-M0).
Instruction sets: (same as Cortex-M0)
NXP (Freescale) FRDM-KL25Z
Thumb-1 (most), missing CBZ, CBNZ, IT. Board with KL25Z128VLK (Kinetis
Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR. L)
Silicon options:

8 region memory protection unit (MPU) (same as M3 and M4).
Vector table relocation (same as M3, M4).
Single-cycle I/O port (available in M0+/M23).
Micro Trace Buffer (MTB) (available in M0+/M23/M33).
Chips
The following microcontrollers are based on the Cortex-M0+ core:
Microchip (Atmel) SAMD, SAMR, SAML, SAMC

Cypress PSoC 4S, FM0+
Holtek HT32F52xxx
NXP LPC800, LPC11E6x, LPC11U6x
NXP (Freescale) Kinetis E, EA, L, M, V1, W0
Renesas Synergy (https://www.renesas.com/en-us/products/synergy/features.html) S1 (https://www.renesas.com/en-
us/products/synergy/microcontrollers/s1-series.html)
Silicon Labs (Energy Micro) EFM32 Zero, Happy
STMicroelectronics STM32 L0
The smallest ARM microcontrollers are of the Cortex-M0+ type (as of 2014, smallest at 1.6 mm by 2 mm is Kinetis
KL03)[16]
Cortex-M1
The Cortex-M1 is an optimized core especially designed to be loaded into FPGA
Cortex-M1
chips.
Key features of the Cortex-M1 core are:[3] (most),
ARMv6-M architecture[9] Thumb-2

3-stage pipeline. (some)
Instruction sets:
Thumb-1 (most), missing CBZ, CBNZ, IT.
Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.
Silicon options:

Optional Tightly-Coupled Memory (TCM): 0 to 1 MB instruction-TCM, 0 to 1 MB data-TCM, each with optional ECC.
External interrupts: 0, 1, 8, 16, 32.
Debug: none, reduced, full.
Data endianness: little-endian or BE-8 big-endian.
OS extension: present or absent.
Chips
The following vendors support the Cortex-M1 as soft-cores on their FPGA chips:
Altera Cyclone-II, Cyclone-III, Stratix-II, Stratix-III

Microsemi (Actel) Fusion, IGLOO/e, ProASIC3L, ProASIC3/E
Xilinx Spartan-3, Virtex-2, Virtex-3, Virtex-4
Cortex-M3
Key features of the Cortex-M3 core are:[4][17]
Cortex-M3
ARMv7-M architecture[10] Instruction set Thumb-1,
3-stage pipeline with branch speculation. Thumb-2,
Instruction sets:
Saturated
Thumb-1 (entire). (some)
Thumb-2 (entire).
32-bit hardware integer multiply with 32-bit or 64-bit result, signed or
unsigned, add or subtract after the multiply. 32-bit
multiply is 1 cycle, but 64-bit multiply and MAC
instructions require extra cycles.
32-bit hardware integer divide (2-12 cycles).
saturation arithmetic support.
12 cycle interrupt latency.
Integrated sleep modes.
Silicon options:
Optional Memory Protection Unit (MPU): 0 or 8 regions. Arduino Due board with Atmel ATSAM3X8E
(ARM Cortex-M3 core) microcontroller
Chips
Actel SmartFusion, SmartFusion 2

Analog Devices ADuCM3xx
Microchip (Atmel) SAM3A, SAM3N, SAM3S, SAM3U,
SAM3X
Cypress PSoC 5, 5LP, FM3
Holtek HT32F NXP LPCXpresso Development Board with
NXP LPC1300, LPC1700, LPC1800 LPC1343
ON Semiconductor Q32M210
Realtek RTL8710[18]
Silicon Labs Precision32
Silicon Labs (Energy Micro) EFM32 Tiny, Gecko, Leopard, Giant
STMicroelectronics STM32 F1, F2, L1, W
Texas Instruments F28, LM3, TMS470, OMAP 4
Texas Instruments SimpleLink Wireless MCUs (CC1310 Sub-GHz and CC2650 BLE+ZigBee+6LoWPAN)
Toshiba TX03
The following chips have a Cortex-M3 as a secondary core:
Apple A9 (Cortex-M3 as integrated M9 motion Co-Processor)

CSR Quatro 5300 (Cortex-M3 as co-processor)
Samsung Exynos 7420 (Cortex-M3 as a DVS microcontroller)[19]
Texas Instruments F28, LM3, TMS470, OMAP 4470 (one Cortex-A9 + two Cortex-M3)
XMOS XS1-XA (seven xCORE + one Cortex-M3)
The following FPGAs include a Cortex-M3 core:
Microsemi SmartFusion2 SoC
Cortex-M4
Conceptually the Cortex-M4 is a Cortex-M3 plus DSP instructions, and
Cortex-M4(F)
optional floating-point unit (FPU). If a core contains an FPU, it is known as a
Cortex-M4F, otherwise it is a Cortex-M4. Instruction set Thumb-1,
Thumb-2,
Key features of the Cortex-M4 core are:[5] Saturated,
DSP,
ARMv7E-M architecture[10]
FPU (SP)
3-stage pipeline with branch speculation.
Instruction sets: Microarchitecture ARMv7E-M
Thumb-1 (entire).
Thumb-2 (entire).
32-bit hardware integer multiply with 32-bit or 64-bit result, signed or
unsigned, add or subtract after the multiply. 32-bit Multiply and MAC
are 1 cycle.
Saturation arithmetic support.
DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit Silicon Labs (Energy Micro) Wonder
MAC, 8/16-bit SIMD arithmetic. Gecko STK Board with
1 to 240 interrupts, plus NMI. EFM32WG990
Silicon options:
Optional floating-point unit (FPU): single-precision only IEEE-754 compliant. It is

called the FPv4-SP extension.
Optional memory protection unit (MPU): 0 or 8 regions.
Chips
Analog Devices CM4xx Mixed-Signal Control Processors

Microchip (Atmel) SAM4L, SAM4N, SAM4S
NXP (Freescale) Kinetis K, W2
Texas Instruments SimpleLink Wi-Fi CC3200 and CC3200MOD (FCC, IC, CE
pre-certified module) TI Stellaris Launchpad Board
with LM4F120
The following microcontrollers are based on the Cortex-M4F (M4 + FPU) core:
Microchip (Atmel) SAM4C (dual core), SAM4E, SAMG, SAM E5x, SAM D5x[20]
Cypress PSoC6 (http://www.cypress.com/psoc6), FM4
Infineon XMC4000
Microchip CEC1302
Nordic nRF52
NXP LPC4000, LPC4300 (one Cortex-M4F + one Cortex-M0)
NXP (Freescale) Kinetis K, V3, V4
Renesas Synergy (https://www.renesas.com/en-us/products/synergy/features.html) S3 (https://www.renesas.com/en-
us/products/synergy/microcontrollers/s3-series.html), S5 (https://www.renesas.com/en-us/products/synergy/microcont
rollers/s5-series.html), S7 (https://www.renesas.com/en-us/products/synergy/microcontrollers/s7-series.html)
Silicon Labs (Energy Micro) EFM32 Wonder
STMicroelectronics STM32 F3, F4, L4
Texas Instruments LM4F, TM4C (http://www.ti.com/lsds/ti/microcontroller/tiva_arm_cortex/c_series/overview.page),
MSP432
Toshiba TX04
The following chips have either a Cortex-M4 or M4F as a secondary core:
NXP (Freescale) Vybrid VF6 (one Cortex-A5 + one Cortex-M4F)

NXP (Freescale) i.MX 6 SoloX (one Cortex-A9 + one Cortex-M4F)
NXP (Freescale) i.MX 7 Solo/Dual (one or two Cortex-A7 + one Cortex-M4F)
Texas Instruments OMAP 5 (two Cortex-A15s + two Cortex-M4)
Texas Instruments Sitara AM57xx (one or two Cortex-A15s + two Cortex-M4s as image processing units + two
Cortex-M4s as general purpose units)
Cortex-M7
The Cortex-M7 is a high-performance core with almost double the power
Cortex-M7(F)
efficiency of the older Cortex-M4. It features a 6-stage superscalar pipeline
with branch prediction and an optional floating-point unit capable of single- Instruction set Thumb-1,
precision and optionally double-precision operations.[21][22] The instruction Thumb-2,
and data buses have been enlarged to 64-bit wide over the previous 32-bit Saturated,
buses. If a core contains an FPU, it is known as a Cortex-M7F, otherwise it is a DSP,
Cortex-M7. FPU (SP & DP)
Microarchitecture ARMv7E-M
Key features of the Cortex-M7 core are:[6]
ARMv7E-M architecture.
6-stage pipeline with branch speculation.

Instruction sets:
Thumb-1 (entire).
Thumb-2 (entire).
32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply.
32-bit Multiply and MAC are 1 cycle.
Saturation arithmetic support.
DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.
Silicon options:
Optional Floating-Point Unit (FPU): (single precision) or (single and double-precision), both IEEE-754-2008 compliant.
It is called the FPv5 extension.
Optional CPU cache: 0 to 64 KB instruction-cache, 0 to 64 KB data-cache, each with optional ECC.
Optional Tightly-Coupled Memory (TCM): 0 to 16 MB instruction-TCM, 0 to 16 MB data-TCM, each with optional ECC.
Optional Memory Protection Unit (MPU): 8 or 16 regions.
Optional Embedded Trace Macrocell (ETM): instruction-only, or instruction and data.
Optional Retention Mode (with Arm Power Management Kit) for Sleep Modes.
Chips
Microchip (Atmel) SAME70 (http://www.atmel.com/products/microcontrollers/arm/sam-e.aspx), SAMS70 (http://www.a

tmel.com/products/microcontrollers/arm/sam-s.aspx), SAMV70 (http://www.atmel.com/products/microcontrollers/arm/s
am-v-mcus.aspx)
NXP (Freescale) Kinetis KV5x[23]i.MX RT [1] (http://www.nxp.com/products/microcontrollers-and-processors/arm-bas
ed-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series:IMX-RT-SERIES)
STMicroelectronics STM32 F7,[24] STM32 H7
Cortex-M23
The Cortex-M23 core was announced in October 2016[25] and based on the
Cortex-M23
newer ARMv8-M architecture that was previously announced in November
2015.[26] Conceptually the Cortex-M23 is similar to a Cortex-M0+ plus integer Instruction set Thumb-1
divide instructions and TrustZone security features, and also has a 2-stage (most),
instruction pipeline. Thumb-2
(some),
As of April 2018, the "Arm Cortex-M23 Arm Generic User Guide" is not yet Divide,
available from Arm Holdings, though the "Arm Cortex-M23 Technical TrustZone
Reference Manual" is available.
Key features of the Cortex-M23 core are:[7][25]
ARMv8-M architecture.[15]
2-stage pipeline (similar to Cortex-M0+).
TrustZone security instructions. (available only in M23/M33)
32-bit hardware integer divide (17 or 34 cycles). (not available in M0/M0+/M1) (slower than M3/M4/M7/M33)
TBD.
Silicon options:

Hardware integer divide speed: 17 or 34 cycles maximum. Depending on divisor, instruction may complete in fewer
cycles.
Optional Memory Protection Unit (MPU): 0, 4, 8, 12, 16 regions.
Optional Security Attribution Unit (SAU): 0, 4, 8 regions.
Single-cycle I/O port (available in M0+/M23).
TBD.
Chips
No chips available yet.

Nuvoton M2351 (announced, not yet generally available).[2] (https://www.cnx-software.com/2017/03/21/numicro-m23
51-trustzone-enabled-arm-cortex-m23-mcu-is-designed-for-fingerprint-applications/)
Expected future chips from Microchip, Nuvoton, NXP, Renesas, Silicon Labs, STMicroelectronics.[25]
Cortex-M33
The Cortex-M33 core was announced in October 2016[25] and based on the
Cortex-M33(F)
newer ARMv8-M architecture that was previously announced in November
2015.[26] Conceptually the Cortex-M33 is similar to a cross of Cortex-M4 and Instruction set Thumb-1,
Cortex-M23, and also has a 3-stage instruction pipeline. Thumb-2,
Saturated,
Key features of the Cortex-M33 core are:[12][25] DSP,
Divide, FPU
ARMv8-M architecture.[15]
(SP),
3-stage pipeline.
TrustZone security instructions. (available only in M23/M33) TrustZone
32-bit hardware integer divide (11 cycles maximum). (not available in Microarchitecture ARMv8-M
M0/M0+/M1)
Stack limit register.
TBD.
Silicon options:
Optional Floating-Point Unit (FPU): single-precision only IEEE-754 compliant. It is called the FPv5 extension.
Optional Memory Protection Unit (MPU): 0, 4, 8, 12, 16 regions.
Optional Security Attribution Unit (SAU): 0, 4, 8 regions.
TBD.
Chips
Nordic nRF91 (announced, not yet generally available)[27]

Expected future chips from Analog Devices, NXP, Renesas, Silicon Labs, STMicroelectronics.[25]
Development tools
Documentation
The amount of documentation for all Arm chips is daunting, especially for
newcomers. The documentation for microcontrollers from past decades would
easily be inclusive in a single document, but as chips have evolved so has the
documentation grown. The total documentation is especially hard to grasp for
all Arm chips since it consists of documents from the IC manufacturer and
documents from CPU core vendor (Arm Holdings).
A typical top-down documentation tree is:
Documentation tree (top to bottom)

Segger J-Link PRO. Debug probe
1. IC manufacturer website
with SWD or JTAG interface to
2. IC manufacturer marketing slides
target ARM chip, and USB or
3. IC manufacturer datasheet for the exact physical chip Ethernet interfaces to host
4. IC manufacturer reference manual that describes common peripherals computer.
and aspects of a physical chip family
5. ARM core website
6. ARM core generic user guide
7. ARM core technical reference manual that describes the instruction set(s)
8. ARM architecture reference manual
IC manufacturers have additional documents, such as: evaluation board user manuals, application notes, getting started
guides, software library documents, errata, and more. See External Links section for links to official Arm documents.
See also
ARM architecture
List of ARM architectures and cores
JTAG, SWD
Interrupt, Interrupt handler
Real-time operating system, Comparison of real-time operating systems
References
1. Cortex-M0 r0p0 Technical Reference Manual; Arm Holdings. (http://infocenter.arm.com/help/topic/com.arm.doc.ddi04
32c/DDI0432C_cortex_m0_r0p0_trm.pdf)
2. Cortex-M0+ r0p0 Technical Reference Manual; Arm Holdings. (http://infocenter.arm.com/help/topic/com.arm.doc.ddi0
484b/DDI0484B_cortex_m0p_r0p0_trm.pdf)
13d/DDI0413D_cortexm1_r1p0_trm.pdf)
37i/DDI0337I_cortexm3_r2p1_trm.pdf)
39d/DDI0439D_cortex_m4_processor_r0p1_trm.pdf)
89b/DDI0489B_cortex_m7_trm.pdf)

550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf)
8. ARM Cortex-M website; arm.com (http://www.arm.com/products/processors/cortex-m)
9. ARMv6-M Architecture Reference Manual; Arm Holdings. (https://silver.arm.com/download/download.tm?pv=110251
3)
10. ARMv7-M Architecture Reference Manual; Arm Holdings. (https://silver.arm.com/download/download.tm?pv=111193
2)
11. Cortex-M3 Embedded Software Development; App Note 179; Arm Holdings. (http://infocenter.arm.com/help/topic/co
m.arm.doc.dai0179b/AppsNote179.pdf)
12. Cortex-M33 r0p3 Technical Reference Manual; Arm Holdings. (http://infocenter.arm.com/help/topic/com.arm.doc.1002
30_0003_00_en/cortex_m33_trm_100230_0003_00_en.pdf)
13. Cortex-M System Design Kit; Arm Holdings. (http://www.arm.com/products/processors/cortex-m/cortex-m-system-desi
gn-kit.php)
14. ARM Cortex-M Programming Guide to Memory Barrier Instructions; Section 3.6 System implementation
requirements; AppNote 321; arm.com (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHEA
DII.html)
15. ARMv8-M Architecture Reference Manual; Arm Holdings. (http://infocenter.arm.com/help/topic/com.arm.doc.ddi0553
a.d/index.html)
16. Fingas, Jon (25 February 2014). "Freescale makes the world's smallest ARM controller chip even tinier" (https://www.
engadget.com/2014/02/25/freescale-kinetis-kl03/). Retrieved 2 October 2014.
17. Sadasivan, Shyam. "An Introduction to the ARM Cortex-M3 Processor" (https://web.archive.org/web/2014072621252
8/http://www.arm.com/files/pdf/IntroToCortex-M3.pdf) (PDF). Arm Holdings. Archived from the original on July 26,
2014.
18. http://datasheets.gpio.dk/dl/RTL8710%20wifi%20module%20specification.pdf#page=11 (http://datasheets.gpio.dk/dl/
RTL8710%20wifi%20module%20specification.pdf)
19. "The Samsung Exynos 7420 Deep Dive - Inside A Modern 14nm SoC" (http://www.anandtech.com/show/9330/exynos
-7420-deep-dive/). AnandTech. Retrieved 2015-06-15.
20. "Microchip Launches Two New SAM Microcontroller Families with Extensive Connectivity Interface Options" (http://w
ww.microchip.com/pressreleasepage/microchip-launches-sam-d5x-e5x-microcontroller-families). www.microchip.com.
Retrieved 2018-02-01.
21. "Cortex-M7 Processor" (http://arm.com/products/processors/cortex-m/cortex-m7-processor.php). Arm Holdings.
Retrieved 2014-09-24.
22. Press Release - ARM Supercharges MCU Market with High Performance Cortex-M7 Processor; arm.com; September
24, 2014; (http://arm.com/about/newsroom/arm-supercharges-mcu-market-with-high-performance-cortex-m7-process
or.php)
23. "KV5x: Kinetis KV5x - 240 MHz, ARM® Cortex®-M7, Real-Time Control, Ethernet, Motor Control and Power
Conversion, High-Performance Microcontrollers (MCUs)" (http://www.freescale.com/webapp/sps/site/prod_summary.j
sp?code=KV5x). Freescale Semiconductor. Retrieved 2015-04-09.
24. "STM32 F7 series of very high performance MCUs with ARM® Cortex®-M7 core" (http://www.st.com/web/en/catalog/
mmc/FM141/SC1169/SS1858). STMicroelectronics. Retrieved 2014-09-24.
25. New ARM Cortex-M processors offer the next industry standard for secure IoT; Arm Holdings; October 25, 2016. (http
s://www.arm.com/files/pdf/cortex_m23_and_cortex_m33.pdf)
26. ARMv8-M Architecture Simplifies Security for Smart Embedded Devices; Arm Holdings; November 10, 2015. (https://
www.arm.com/about/newsroom/armv8-m-architecture-simplifies-security-for-smart-embedded-devices.php)
27. https://www.nordicsemi.com/News/News-releases/Product-Related-News/Nordic-nRF91-low-power-cellular-IoT-
sneak-peek-cellular-made-easy-cellular-for-everything-else
Further reading
Designer's Guide to the Cortex-M Processor Family; 2nd Edition; Trevor Martin; 490 pages; 2016; ISBN 978-
0081006290.
ARM Assembly for Embedded Applications; 3rd Edition; Daniel Lewis; 318 pages; 2017; ISBN 978-1543908046.
Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C; 2nd Edition; Yifeng Zhu, 660
pages; 2015; ISBN 978-0982692639.
Definitive Guide to the ARM Cortex-M0 and Cortex-M0+ Processors; 2nd Edition; Joseph Yiu; 784 pages; 2015;
ISBN 978-0128032770.
Definitive Guide to the ARM Cortex-M3 and Cortex-M4 Processors; 3rd Edition; Joseph Yiu; 600 pages; 2013;
ISBN 978-0124080829.
Embedded Systems with ARM Cortex-M3 Microcontrollers in Assembly Language and C; 1st Edition; Yifeng Zhu; 542
pages; 2014; ISBN 978-0982692622.
Digital Signal Processing and Applications Using the ARM Cortex-M4; 1st Edition; Donald Reay; 250 pages; 2014;
ISBN 978-1118859049.
Embedded Systems: Introduction to ARM Cortex-M Microcontrollers; 5th Edition; Jonathan Valvano; 506 pages;
2012; ISBN 978-1477508992.
Assembly Language Programming: ARM Cortex-M3; 1st Edition; Vincent Mahout; 256 pages; 2012; ISBN 978-
1848213296.
Introduction To Reverse Engineering for Beginners including ARM assembly; Dennis Yurichev; online book (http://yuri
chev.com/writings/RE_for_beginners-en.pdf).
External links
ARM Cortex-M official documents
ARM Cortex-M official website (http://www.arm.com/products/processors/cortex-m)

Cortex-M for Beginners (https://community.arm.com/cfs-file/__key/telligent-evolution-components-attachments/01-214
2-00-00-00-00-52-96/White-Paper-_2D00_-Cortex_2D00_M-for-Beginners-_2D00_-2016-_2800_final-v3_2900_.pdf) -
arm.com
ARMv8-M Security Extensions (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8
m_security_extensions_reqs_on_dev_tools_1_0.pdf) - arm.com
Cortex-M Software Interface Standard (CMSIS) (http://www.arm.com/products/processors/cortex-m/cortex-microcontr
oller-software-interface-standard.php) - arm.com
ARM Bit ARM ARM Generic ARM Technical ARM Architecture

Core Width Website User Guide Reference Manual Reference Manual
Link (https://
Link (http://infocenter.
developer.ar Link (http://infocenter.ar ARMv6-M (http://infocen
arm.com/help/topic/co
m.com/prod m.com/help/topic/com.a ter.arm.com/help/topic/c
Cortex- m.arm.doc.dui0497a/
32 ucts/process rm.doc.ddi0432c/DDI04 om.arm.doc.ddi0419d/D
M0 DUI0497A_cortex_m0
ors/cortex- 32C_cortex_m0_r0p0_t DI0419D_armv6m_arm.
_r0p0_generic_ug.pd
m/cortex-m rm.pdf) pdf)
f)
0)
Link (https://
developer.ar Link (http://infocenter. Link (http://infocenter.ar
m.com/prod arm.com/help/topic/co m.com/help/topic/com.a
Cortex-
32 ucts/process m.arm.doc.dui0662b/ rm.doc.ddi0484c/DDI04 ARMv6-M
M0+
ors/cortex- DUI0662B_cortex_m0 84C_cortex_m0p_r0p1
m/cortex-m0 p_r0p1_dgug.pdf) _trm.pdf)
-plus)
Link (https:// Link (http://infocenter.
Link (http://infocenter.ar
www.arm.co arm.com/help/topic/co
m.com/help/topic/com.a
Cortex- m/products/ m.arm.doc.dui0395b/
32 rm.doc.ddi0413d/DDI04 ARMv6-M
M1 processors/c DUI0395B_cortex_m1
13D_cortexm1_r1p0_tr
ortex-m/cort _fpga_dk_user_guide
m.pdf)
ex-m1.php) _altera.pdf)
Link (https://
Link (http://infocenter.ar ARMv7-M (https://silver.
developer.ar Link (http://infocenter.
m.com/help/topic/com.a arm.com/download/ARM
m.com/prod arm.com/help/topic/co
Cortex- rm.doc.100165_0201_0 _and_AMBA_Architectur
32 ucts/process m.arm.doc.dui0552a/
M3 0_en/arm_cortexm3_pr e/AR580-DA-70000-r0p
ors/cortex- DUI0552A_cortex_m3
ocessor_trm_100165_0 0-05rel0/DDI0403E_B_a
m/cortex-m _dgug.pdf)
201_00_en.pdf) rmv7m_arm.pdf)
3)
Link (https://
developer.ar Link (http://infocenter.
m.com/help/topic/com.a
m.com/prod arm.com/help/topic/co
Cortex- rm.doc.100166_0001_0
32 ucts/process m.arm.doc.dui0553a/ ARMv7E-M
M4(F) 0_en/arm_cortexm4_pr
ors/cortex- DUI0553A_cortex_m4
ocessor_trm_100166_0
m/cortex-m _dgug.pdf)
001_00_en.pdf)
4)
Link (https://
developer.ar Link (http://infocenter. Link (http://infocenter.ar
m.com/prod arm.com/help/topic/co m.com/help/topic/com.a
Cortex-
32 ucts/process m.arm.doc.dui0646b/ rm.doc.ddi0489d/DDI04 ARMv7E-M
M7(F)
ors/cortex- DUI0646B_cortex_m7 89D_cortex_m7_trm.pd
m/cortex-m _dgug.pdf) f)
7)
Link (https://
developer.ar
m.com/help/topic/com.a ARMv8-M (http://infocen
m.com/prod
Cortex- rm.doc.ddi0550c/cortex ter.arm.com/help/topic/c
32 ucts/process N/A
M23 _m23_r1p0_technical_r om.arm.doc.ddi0553a.d/
ors/cortex-
eference_manual_DDI0 index.html)
m/cortex-m2
550C_en.pdf)
3)
Link (https://
Link (http://infocenter. Link (http://infocenter.ar
developer.ar
arm.com/help/topic/co m.com/help/topic/com.a
m.com/prod
Cortex- m.arm.doc.100235_0 rm.doc.100230_0003_0
32 ucts/process ARMv8-M
M33(F) 003_00_en/arm_corte 0_en/cortex_m33_trm_
ors/cortex-
x_m33_dgug_100235 100230_0003_00_en.p
m/cortex-m3
_0003_00_en.pdf) df)
3)
Quick Reference Cards
Instructions: Thumb-1 (1 (http://infocenter.arm.com/help/topic/com.arm.doc.qrc0006e/QRC0006_UAL16.pdf)), ARM

and Thumb-2 (2 (http://infocenter.arm.com/help/topic/com.arm.doc.qrc0001m/QRC0001_UAL.pdf)), Vector Floating-
Point (3 (http://infocenter.arm.com/help/topic/com.arm.doc.qrc0007e/QRC0007_VFP.pdf)) - arm.com
Opcodes: Thumb-1 (1 (http://re-eject.gbadev.org/files/ThumbRefV2-beta.pdf), 2 (http://www.mechcore.net/files/docs/T
humbRefV2-beta.pdf)), ARM (3 (http://re-eject.gbadev.org/files/armref.pdf), 4 (http://www.mechcore.net/files/docs/arm
ref.pdf)), GNU Assembler Directives (5 (http://re-eject.gbadev.org/files/GasARMRef.pdf)).
Migrating
Migrating from 8051 to Cortex-M3 (http://infocenter.arm.com/help/topic/com.arm.doc.dai0237a/DAI0237A_migrating_f

rom_8051_to_Cortex_M.pdf) - arm.com
Migrating from PIC to Cortex-M3 (http://infocenter.arm.com/help/topic/com.arm.doc.dai0234a/DAI0234A_migrating_fr
om_pic_to_m3.pdf) - arm.com
Migrating from ARM7TDMI to Cortex-M3 (http://www.arm.com/files/pdf/Cortex-M3_programming_for_ARM7_develop
ers.pdf) - arm.com
Migrating from Cortex-M4(F) to Cortex-M7(F) (http://www.keil.com/appnotes/files/apnt_270.pdf) - keil.com
Other
Bit Banding on STM32 Cortex-M microcontrollers (http://www.micromouseonline.com/2010/07/14/bit-banding-in-the-st

m32/)
Retrieved from "https://en.wikipedia.org/w/index.php?title=ARM_Cortex-M&oldid=838917395#Cortex-M0+"
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ARM Cortex-M optional components

Bit-Band memory No[13] No[13] No* Optional Optional No No No

Memory Protection Optional Optional Optional Optional Optional Optional

Instruction Cache No[14] No[14] No[14] No[14] No[14] Optional No TBD

Data Cache No[14] No[14] No[14] No[14] No[14] Optional No TBD

ARM Cortex-M instruction variations

has a FPU, then it is known as the Cortex-M4F / Cortex-M7F / Cortex-M33F.[9][10]

ARM Cortex-M instruction groups

The 32-bit ARM instruction set is not included in Cortex-M cores.

Thumb-1 (most), missing CBZ, CBNZ, IT.

Hardware integer multiply speed: 1 or 32 cycles.

Cypress PSoC 4, 4M, 4L

NXP LPC4300 (one Cortex-M4F + one Cortex-M0)

The Cortex-M0+ is an optimized superset of the Cortex-M0. The Cortex-M0+ Cortex-M0+

Key features of the Cortex-M0+ core are:[2]

Hardware integer multiply speed: 1 or 32 cycles.

Microchip (Atmel) SAMD, SAMR, SAML, SAMC

ARMv6-M architecture[9] Thumb-2

Hardware integer multiply speed: 3 or 33 cycles.

Altera Cyclone-II, Cyclone-III, Stratix-II, Stratix-III

Actel SmartFusion, SmartFusion 2

Apple A9 (Cortex-M3 as integrated M9 motion Co-Processor)

Microsemi SmartFusion2 SoC

Optional floating-point unit (FPU): single-precision only IEEE-754 compliant. It is

Analog Devices CM4xx Mixed-Signal Control Processors

NXP (Freescale) Vybrid VF6 (one Cortex-A5 + one Cortex-M4F)

6-stage pipeline with branch speculation.

Microchip (Atmel) SAME70 (http://www.atmel.com/products/microcontrollers/arm/sam-e.aspx), SAMS70 (http://www.a

Hardware integer multiply speed: 1 or 32 cycles.

No chips available yet.

Nordic nRF91 (announced, not yet generally available)[27]

A typical top-down documentation tree is:

Documentation tree (top to bottom)

7. Cortex-M23 r1p0 Technical Reference Manual; Arm Holdings. (http://infocenter.arm.com/help/topic/com.arm.doc.ddi0

ARM Cortex-M official website (http://www.arm.com/products/processors/cortex-m)

ARM Bit ARM ARM Generic ARM Technical ARM Architecture

Quick Reference Cards

Instructions: Thumb-1 (1 (http://infocenter.arm.com/help/topic/com.arm.doc.qrc0006e/QRC0006_UAL16.pdf)), ARM

Migrating from 8051 to Cortex-M3 (http://infocenter.arm.com/help/topic/com.arm.doc.dai0237a/DAI0237A_migrating_f

Bit Banding on STM32 Cortex-M microcontrollers (http://www.micromouseonline.com/2010/07/14/bit-banding-in-the-st

Retrieved from "https://en.wikipedia.org/w/index.php?title=ARM_Cortex-M&oldid=838917395#Cortex-M0+"

This page was last edited on 30 April 2018, at 03:02.

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