Switching of the signal in one net can interfere neigbouring net due to cross
coupling capacitance.This affect is known as cros talk. Cross talk may lead setup
or hold voilation
-- --------
#How can you overcome cross talk problem?
-Double spacing=>more spacing=>less capacitance=>less cross talk
-Multiple vias=>less resistance=>less RC delay
-Shielding=> constant cross coupling capacitance =>known value of crosstalk
-Buffer insertion=>boost the victim strength
REDUCING TECHNIQUES
1. VICTIM NET WIDTH INCREASING THEN RESISTANCE DECREASE IT IS USED AT ROUTING ALSO.
2. SPACING BETWEEN AGGRESSOR NET AND VICTIM NET INCREASE.
3. BUFFERING ON CONSTANT NETS (OR) VICTIM NETS.
4. PLACING AN GROUND NETS ON BETWEEN THE AGGRESSOR NET AND VICTIM NET THEN VOLTAGE
DISCHARGE ON GROUND NET THEN NO SIGNAL INTEGRITY PROBLEM.THIS IS CALLED SHIELDING .
5. MAINTAIN STABLE SUPPLY.
6. FAST SLEW RATE.
7. JOGING(INCRAESE HALF TRACK BY HALF ITCH).
8. LAYER JUMPING(JUMP ONE LAYER ABOVE LAYER AND COMES TO SAME LAYER)
9. INCREASE DRIVE STRENTH OF CELL
10. CELL SIZING(UP SIZING)
11. DEEP N-WELL.
12. GUARD RING.
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#what is shielding? how it avoid avoids crosstalk problem?
High frequency noise (or glitch)is coupled to VSS (or VDD) since shilded layers are
connected to either VDD or VSS.
Coupling capacitance remains constant with VDD or VSS.
The IC Compiler tool implements clock shielding using nondefault routing rules. You
can
choose either to shield clock nets before routing signal nets or vice versa. The
methodology
of shielding clock nets before routing signal nets yields better shielding coverage
but can
cause more DRC violations during signal net routing compared to the methodology of
routing signal nets before shielding clock nets.
------------------------------------------------------
#how spacing h reducing crosstalk noise?
width is more=>more spacing between two conductors=>cross coupling capacitance is
less=>less cross talk
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#Why double spacing and multiple vias are used related to clock?
Why clock?-- because it is the one signal which chages it state regularly and more
compared to any other signal. If any other signal switches fast then also we can
use double space.
Double spacing=>width is more=>capacitance is less=>less cross talk
Multiple vias=>resistance in parellel=>less resistance=>less RC delay
-----------------------------------------------------
#where do you insert buffer to avoid crosstalk? how buffer insertion solve the
problem?
Buffer increase victims signal strength; buffers break the net length=>victims are
more tolerant to coupled signal from aggressor
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#Difference between Chip Design and Block level design?
Chip design has I/O pads; block design has pins.
Chip design uses all metal layes available; block design may not use all metal
layers.
Chip is generally rectangular in shape; blocks can be rectangular, rectilinear.
Chip design requires several packaging; block design ends in a macro.
------------------------------------------------------
#What are the ways to place macros in a full chip design?
First check flylines i.e. check net connections from macro to macro and macro to
standard cells.
If there is more connection from macro to macro place those macros nearer to each
other preferably nearer to core boundaries.
If input pin is connected to macro better to place nearer to that pin or pad.
If macro has more connection to standard cells spread the macros inside core.
Avoid criscross placement of macros.
Use soft or hard blockages to guide placement engine
----------------------------------------------------
#what are the differences between Hierarchical Design and flat design?
Hierarchial design has blocks, subblocks in an hierarchy; Flattened design has no
subblocks and it has only leaf cells.
Hierarchical design takes more run time; Flattened design takes less run time.
----------------------------------------------------
#Why 500 MHz clock design is complex than 48Mhz design?
500 MHz; because it is more constrained (i.e.lesser clock period) than 48 MHz
design.
----------------------------------------------------
#What all tools used in physical verification?
Herculis from Synopsys, Caliber from Mentor Graphics.
----------------------------------------------------
#what are the inputs you will give in physical verification
#what all the and inputs and outputs for each step of physical design?
#What is cell delay and net delay, how will you reduce this delays?
Gate delay
Transistors within a gate take a finite time to switch. This means that a change on
the input of a gate takes a finite time to cause a change on the output.[Magma]
Gate delay =function of(i/p transition time, Cnet+Cpin).
Cell delay is also same as Gate delay.
Cell delay
For any gate it is measured between 50% of input transition to the corresponding
50% of output transition.
Intrinsic delay
Intrinsic delay is the delay internal to the gate. Input pin of the cell to output
pin of the cell.
It is defined as the delay between an input and output pair of a cell, when a near
zero slew is applied to the input pin and the output does not see any load
condition.It is predominantly caused by the internal capacitance associated with
its transistor.
This delay is largely independent of the size of the transistors forming the gate
because increasing size of transistors increase internal capacitors.
what is powerplanning, How you use to do i. Power estimation ii. power pads
estimation (core & IO) iii. core ring width calculation iv. EMIR v. SSO
What are preroutes in your design?
How to power route multiVDD design?
Power domains, partitioning, power routing for multi domains, placement of power
switches?
What are the various views of a macro or a cell?
What is the macro placement guidelines?
What all checks will you perform after Floor planning?
What if you allow the cell to be placed in the halo region around macro? Can you
do that? Why?
If you import a LEF for a macro and you find out that the macro pins are moved from
boundary to center, what will be your approach?
How did you define your power structure for full chip?
How will you start power planning for your design?
EMIR & low power:
How power is related with clock frequency?
Can we achieve lower power with more than one voltage supply?
Different low power techniques?
methods of leakage reduction?
What are the vectors of dynamic power?
How can you reduce dynamic power?
If you have both IR drop and congestion how will you fix it?
Is increasing power line width and providing more number of straps are the only
solution to IR drop?
Why higher metal layers are preferred for Vdd and Vss?
What is IR drop? How it affects timing?
What is EM and it effects? how to resolve EM?
Techniques to avoid IR problems? Dynamic & Static
Do we have inactive blocks that we can shut off to reduce leakage power?
What are Retention registers?
Give the various techniques you know to minimize power consumption for CMOS logic?
Give the expression for CMOS switching power dissipation?
List out the factors affecting power consumption on a chip?
Any custom routes of analog/power? What were the requirements of custom routes?
Any experience in low power techniques?
Any experience with multi Vt libraries?
What is total Static & dynamic power consumption in your design?
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Questions Related to Clock Tree Synthesis