IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO.
6, JUNE 2005
On the Feasibility of Nanoscale Triple-Gate
CMOS Transistors
Ji-Woon Yang and Jerry G. Fossum, Fellow, IEEE
Abstract—The feasibility of triple-gate MOSFETs (TGFETs) for
nanoscale CMOS applications is examined with regard to short-
channel effects (SCEs) and gate-layout area. Three-dimensional
numerical simulations of TGFETs reveal that much more strin-
gent body scaling for SCE control is needed for undoped bodies
relative to doped ones (which are not viable for nanoscale devices)
due to the suppression of corner current conduction (which is tech-
nologically advantageous) in the former. When the undoped body
is scaled for adequate SCE control, further analysis shows that the
generic TGFET suffers from severe layout-area inefficiency rela-
tive to the fully depleted single-gate SOI MOSFET (FDFET) and
the double-gate (DG) FinFET, and the inefficiency can be improved
only by evolving the TGFET into a virtual FDFET or a virtual
DG FinFET. We suggest then that the TGFET is not a feasible
nanoscale CMOS transistor, and thus the DG FinFET, which is
more scalable than the FDFET, seems to be the most promising
candidate for future CMOS applications.
Index Terms—Gate layout area, multigate MOSFETs, nanoscale
CMOS, short-channel effects (SCEs).
I. INTRODUCTION
C ONVENTIONAL scaling of classical bulk-Si and par-
tially depleted SOI CMOS has become very challenging
because control of short-channel effects (SCEs) for accept-
able ratios requires precise channel doping levels
and gradients [1] that are, ultimately, impossible to achieve.
Promising alternatives for continued CMOS scaling are the
nonclassical devices having ultrathin bodies (UTBs), i.e., the
planar fully depleted single-gate SOI MOSFET (FDFET) [2]
and the quasi-planar double-gate (DG) FinFET [3], which
give good SCE control via the UTB whether it is doped or
not. The undoped UTB is the proper choice since it avoids
the doping challenges noted for the classical devices, and the
implied threshold-voltage variations [4]. Further, it avoids
source/drain junction-tunneling leakage currents and can yield
higher carrier mobilities [5] due to less surface scattering and
negligible impurity scattering.
However, the good SCE control in the nonclassical nanoscale
devices requires that the UTB thickness be considerably
thinner than the gate length , as well as being uniform
across the device and circuit. For the FDFET shown in Fig. 1(a),
, which is the height of the Si film, should be scaled
down to [6]. For the DG FinFET shown in Fig. 1(b),
, which is the width of the Si fin, should be scaled
Manuscript received August 20, 2004; revised March 8, 2005. This work was
supported in part by Freescale Semiconductor. The review of this paper was
arranged by Editor M.-C. Chang.
The authors are with the Department of Electrical and Computer Engineering,
University of Florida, Gainesville, FL 32611-6130 USA.
Digital Object Identifier 10.1109/TED.2005.848109
0018-9383/$20.00 © 2005 IEEE
1159
down to [7]. (Note that the effective channel length
of nonclassical devices with undoped bodies will probably be
longer than [7].) A triple-gate MOSFET (TGFET) has been
proposed [8], [9] as a means to alleviate the stringent thin- re-
quirements of UTB FDFETs and DG FinFETs, enabling “flex-
ible and relaxed” Si-body dimensions as illustrated in Fig. 1(c).
With a lower comparable to a wider , the planar-like
TGFET is easier to fabricate than the DG FinFET, and the exper-
imental and simulation results in [8] and [9] suggest that excel-
lent short-channel device performance can be achieved. These
results, however, were obtained for TGFETs with heavily doped
bodies, which, as noted above, are not desirable. Further, such
devices can show problematic corner effects [9], which do not
occur in undoped TGFETs [10]. And, the layout area of the
TGFET is an issue for nanoscale CMOS [9]. The feasibility of
the TGFET is thus not yet clear.
In this paper, we examine the feasibility of the TGFET for
nanoscale CMOS applications with regard to SCEs and layout
area. We check the SCEs for varying dimensions of the body,
with and without doping, using Davinci [11], a three-dimen-
sional (3-D) numerical device simulator. Then, with the SCEs
adequately controlled via body scaling in accord with the 3-D
simulation results, we analyze the gate-layout area of the inte-
grated TGFET needed for current drive, and compare it with
those of the FDFET and DG FinFET.
II. SHORT-CHANNEL EFFECTS
Following [8], we first assume that a reasonable TGFET de-
sign could, with reference to Fig. 1(c), be .
For nm devices, we let the gate-oxide thickness
be 1.1 nm and the SOI buried-oxide thickness
be 200 nm. For the 3-D device simulations, we assume
abrupt source/drain junctions with 10-nm gate overlaps (i.e.,
nm with nm being the metallurgical channel
length), meaning that fringing fields outside the intrinsic device
are negligible. We also assume rectangular body cross sections,
i.e., 90 corners. Generally, the default physical modeling in
Davinci [11] was used. This modeling, e.g., that for carrier mo-
bility, is not crucial in our study of SCEs here. The geometrical,
or 3-D, modeling is crucial, and it was validated by proper def-
inition of the device-domain mesh for the discretization of the
underlying partial-differential equations.
Fig. 2 shows Davinci-predicted – characteristics of
the TG nMOSFET, with both doped and undoped bodies. For
the doped device, cm and the gate material
is polysilicon. This device exhibits excellent subthreshold
characteristics; the drain-induced barrier lowering (DIBL) is 35
mV/V and the subthreshold slope (S) is 75 mV/dec, both of
1160 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 6, JUNE 2005

Fig. 3. Davinci-predicted current–voltage characteristics of doped-body

(N = 8 0 2 10
: cm with n polysilicon gate) n-channel TGFETs
with varying fin-body dimensions; t = 11 : nm, t = 200 nm, and
L = 28 nm. (The numerical simulation of the largest body device was
done using larger mesh-point spacings, which could yield slightly erroneous
solutions in the corner regions and hence underlie the noticeably lower current
in the subthreshold region).

thought of as nanotubes with a very small radius, or effective

body thickness .
To examine more closely the doped-body TGFET, we per-
formed 3-D numerical simulations of devices with varying body
dimensions. As shown in Fig. 3, the predicted subthreshold
– characteristics are virtually independent of the body
dimensions, which solidifies our insight that the subthreshold
characteristics are governed by the corner regions having lower
Fig. 1. Schematic illustrations of (a) the FDFET, (b) the DG FinFET, and than that of the bulk-body device [10]. Note in Fig. 3, how-
(c) the TGFET. All devices are typically fabricated in SOI material, with the
buried oxide (BOX) providing isolation.
ever, that the strong inversion current varies with the effective
gate width of the devices, reflecting three surface
channels with higher conductance than the corners.
The noted insights concerning the doped-body TGFET seem
to imply an optimal device. Predominant corner conduction in
weak inversion yields good control of SCEs and a relatively low
off-state current , whereas the three surface channels in
strong inversion imply good on-state current , as shown
in [8] and [9]. In an actual TGFET, however, and the
corner conduction depend on the finite radius of the curvature
of the corners [9], which could be difficult to control. Further,
any controlled doping of nanoscale Si bodies, be it via angled
or halo implants, is virtually impossible; the fluctuation in the
number of channel dopants and their spacial randomness render
unacceptable variations in [4]. Hence, the doped TGFET is
not technologically feasible for nanoscale , not unlike the
classical MOSFETs.
For the undoped cm TGFET in Fig. 2,
Fig. 2. Davinci-predicted current–voltage (per W h= 2 w ) + we assumed a midgap metal gate V) for threshold
characteristics of doped-body (N = 8 0 2 10
: cm with n polysilicon control. Note that the predicted subthreshold characteristics are
gate) and undoped-body (midgap gate) n-channel TGFETs; t : = 11
nm, much worse than those of the doped device (and are prohibitive),
t = 200 nm, and h = w = = 28
L nm. even though both devices have the same body dimensions. In this
device, the corner conduction is eliminated [10], and the sub-
which are comparable to corresponding results in [8]. However, threshold current flows throughout the entire body. Obviously,
as we have previously explained [10], the good SCE control of however, the body is too large to control the SCEs. Nonetheless,
the doped TGFET results from the predominant subthreshold the undoped body is the viable design, and hence the body di-
current flowing in the corner regions of the body, which can be mensions needed to suppress the SCEs must be checked.
YANG AND FOSSUM: FEASIBILITY OF NANOSCALE TRIPLE-GATE CMOS TRANSISTORS 1161

Fig. 4. Davinci-predicted TGFET body dimensions needed (below and left of the curves) to suppress SCEs as noted; L = 28 nm, t = 1:1 nm, and
V = 1:0 V. For the extreme cases, w and h represent the required UTB thinness of the DG FinFET and the planar FDFET, respectively, to
suppress the SCEs. The points A and B represent the body dimensions for h = L and w = L , respectively, showing that TGFETs have negligible scaling
advantage over the DG FinFET and the FDFET. Point C is an “optimal” TGFET design, having w and h equal to about 1.4 times w and h ,
respectively. Note that the design with h = w = L (point X) is clearly not feasible.

To check SCE control in the undoped-body TGFET, we per- This means that the undoped TGFET has no scaling advantage
formed 3-D simulations of the generic structure in Fig. 1(c), still over the DG FinFET at all. Clearly then, should be made as
assuming V, nm, nm, abrupt high as possible to maximize the effective gate width, creating in
source/drain-body junctions, and a rectangular body cross sec- essence the DG FinFET with gate width . Also, we note
tion. (We note that our simulation results and the conclusions we in Fig. 4 (point B) that with , the required for the
draw based on them apply strictly only to this assumed generic TGFET is less than 20% larger than that needed for the FDFET
TGFET structure.) Several sets of body dimensions were tried in . This means that the undoped TGFET has very little
the simulations to obtain reasonable subthreshold characteristics, scaling advantage over the FDFET.
i.e., DIBL mV/V and mV/dec. Required combina- Our results and conclusions regarding the TGFET versus the
tions of and for the TGFET with nm are shown FDFET are inconsistent with recently reported experimental re-
in Fig. 4; in fact, the dimensions needed are about the same for sults [13], which suggest that TGFETs with show
both the DIBL and S specifications. Due to absence of the corner excellent subthreshold characteristics down to nm,
effects now, the body dimensions needed to suppress the SCEs even for . Our results in Fig. 4 show that
are much smaller than those intimated in [8], e.g., would be needed to get the SCE results reported in [13].
indicated by point X in Fig. 4, which yields the poor sub- Whereas there could be uncertainty in versus , and/or in
threshold characteristics shown in Fig. 2. Note also the extreme , in [13], the authors of the paper suggest that local
cases: For large , the results give the required thin for the strain in the Si body due to the metal (NiSi) gate and/or the SOI
virtual DG FinFET to get the spec- mesa isolation benefits the SCE control (as well as carrier mo-
ified DIBL and S, and for large , they give the required thin bility and ) in their devices. Strained TGFETs might then be
for the virtual FDFET . These feasible, but understanding and controlling the strain constitute
UTB requirements are consistent with results in [6] and [7]. a formidable task.
(We note that our 3-D device-simulation results in Fig. 4 are
consistent with the numerical predictions of S in [12], although III. LAYOUT AREA
the results in [12] are for longer and are not presented as
a – locus corresponding to a particular value of S. This With the required body dimensions for SCE control given in
consistency supports the validity of our simulations.) the preceding section, we now examine the CMOS layout area
To stress the much more stringent body scaling needed for of TGFETs, and compare it with those of planar FDFETs and
the nanoscale TGFETs relative to that DG FinFETs. We focus on gate areas, assuming that the pe-
implied in [8] and [9], we note in Fig. 4 (point A) that with ripheral areas of the three devices scale proportionally. Mul-
, is required to suppress the SCEs. tifinger structures as illustrated in Fig. 5, with their pertinent
1162 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 6, JUNE 2005

Fig. 5. (a)Top view and (b) cross-sectional view A–A , as indicated in (a), of the multigate/finger transistor. The effective gate width of each finger (per pitch in
the layout) is noted for the TGFET, the DG FinFET, and the planar FDFET in (b).

dimensions, will generally be required. The two-dimensional

cross-sectional view – of the multigate/finger transistor, in-
dicated in Fig. 5(a), is shown in Fig. 5(b) to relate the effec-
tive gate width of each finger (per pitch in the layout) to
the pitch (P). In order to calculate the gate layout areas of the
TGFET and the DG FinFET needed to achieve the same total
drive current, we assume per unit width of each device is
the same, and equal to that of the FDFET, which will be used as
a reference. With this assumption, gate layout areas for multi-
gate/finger TGFETs and DG FinFETs are expressed as

(1)

(2)

where is the total gate width needed (i.e., the required

number of fingers equals ). Note that (1) and (2) de- Fig. 6. Calculated layout area ratios (R ) of the TGFET with w =
pend on the assumed for each device; i.e., as indicated in 1:4w and h = 1 :4 h and the DG FinFET with R =
h =w = 5 relative to the planar FDFET, versus gate length; L (= L )
Fig. 5(b), for the TGFET and and P for the calculations were obtained from the ITRS projections for HP and
for the DG FinFET. For the planar FDFET, the gate layout area LSTP CMOS technologies [14].
is simply , and .
Based on the simulation results in Fig. 4, we assume, for SCE
control, for the DG FinFET and restricted due to SCEs as illustrated in Fig. 4. In order to relax
for the FDFET. The purported advantage of the TGFET is the re- and at the same rate while maintaining the same SCEs,
laxation of the Si-body dimensions required, relative to the DG the body dimensions of an “optimal” TGFET are chosen to be
FinFET and the FDFET. However, this advantage is severely about 1.4 times and , as indicated by point C
YANG AND FOSSUM: FEASIBILITY OF NANOSCALE TRIPLE-GATE CMOS TRANSISTORS 1163

Fig. 7. Davinci-predicted body dimensions of the TGFET needed for S = 80 mV=dec; L = 28 nm, t = 1:1 nm, and V = 1:0 V , with lines A and B
representing W = P (= 140 nm) for the TGFET and the DG FinFET, respectively. The arrows indicate possible design-optimization paths, which, however,
lead to virtual DG FinFET and planar FDFET structures.

in Fig. 4. Then, using (1) and (2), we show in Fig. 6 calcu- The layout area comparisons in Fig. 6 reflect the smaller
lated ratios of and to versus for the TGFET structure assumed. To check its optimization, the
(assumed to equal ) at different technology nodes, with all 3-D simulation results for mV/dec in the TGFET with
body dimensions set as noted for SCE control. For the calcula- nm in Fig. 4 are replotted in Fig. 7. Lines A and
tions, and were obtained from the ITRS [14] CMOS pro- B there represent for the TGFET and DG FinFET,
jections for the high-performance (HP) logic technology and the respectively, as for the planar FDFET. To get equal to or
low standby-power (LSTP) technology. We assumed maximum wider than , the respective body dimensions must be above
fin-aspect ratios of 5 for the DG FinFET. Since the lines A and B. For the TGFET, our “optimal” design (point
of the DG FinFET is inversely proportional to , it would C in Fig. 4) is well below line A. We could redesign it as in-
increase in Fig. 6 by a factor of 5/3–5/4 for smaller , dicated in Fig. 7 for wider and smaller . However, it is
which is perhaps more technologically reasonable for the scaled evident that moving toward line A with the same SCE control
device. would require either decreasing (path in Fig. 7), which
As evident in Fig. 6, of the TGFET is much higher than yields a virtual DG FinFET (for which , or , should be
that of the DG FinFET, which can be for higher . At maximized), or decreasing (path in Fig. 7), which yields
the nm nodes of the HP logic technology, the TGFET a virtual FDFET. The undoped TGFET structure is inferior, un-
would require almost four times the gate area required for the less it is transformed into a DG FinFET or a FDFET. Note also
DG FinFET; and this severe layout-area disadvantage worsens, in Fig. 7 that the DG FinFET would be made more area efficient
for the same TGFET body-dimension factor of 1.4, all the way to than the FDFET, i.e., have a wider , if could be above
the end of the ITRS where nm. Note also in Fig. 6 that line B; this would require .
is better for both devices in the LSTP technology because, at From the 3-D device simulation results in Fig. 4, we have
a given node for specified , is scaled less aggressively. (For noted the requirement of body thickness for SCE control to be
a specific , the HP versus LSTP differences in Fig. 6 reflect for the DG FinFET and for
different values of .) However, the severe TGFET layout-area the FDFET. Hence, if we set the pragmatic lower limit of body
disadvantage remains. We note that all the ratios plotted in Fig. 6 thickness ( or ) at 5 nm due to manufacturing burden and
would be reduced by a factor of two if the multigate/finger de- quantization effects from the structural confinement [6], we note
vices were defined by spacer lithography [9], thereby substan- that the FDFET cannot be scaled down below nm
tially enhancing the relative layout-area advantage of DG Fin- (where we are still assuming .). However, the DG
FETs. We also note though that bulk strong inversion in undoped FinFET can be scaled down to nm. Indeed, this su-
FinFETs [15] can render the TG-DG ratio for a given fin perior scalability of the undoped-body DG FinFET seems to
less than , meaning that the relative TGFET layout render it, with technologically defined maximum , the most
area disadvantage could actually be worse than shown in Fig. 6. promising candidate for future nanoscale CMOS.
1164
IV. CONCLUSIONS
Focusing on viable undoped bodies, we examined the UTB
dimensions needed to control SCEs in nanoscale planar-like
TGFETs by 3-D numerical simulations. The results showed that
much more stringent body scaling is needed for the undoped
TGFET (which has no corner effects), relative to the doped one
(which is technologically and electrically infeasible). When the
comparable body dimensions of the undoped, generic TGFET
are scaled for adequate SCE control, we find that it suffers from
a significant layout-area disadvantage relative to the DG FinFET
and the planar, single-gate FDFET. We hence suggest that the
TGFET, without some benefit from strain [13] or other tech-
nology boost not considered herein, is not feasible because,
when adequately scaled for SCE control, its gate layout-area ef-
ficiency is relatively poor and can be improved only by evolving
it into a virtual DG FinFET with or a virtual
FDFET with . Further, our insights imply that this
layout disadvantage is not peculiar only to the TGFET, but is
characteristic of any multigate nanoscale MOSFET with more
than two gates and comparable body dimensions, for example,
the gate-all-around device [16] and the surrounding-gate tran-
sistor [17]. Such multigate devices would also require extremely
scaled body, e.g., nanotube, dimensions, and thus would have
very small like the TGFET. We thus argue that the undoped
DG FinFET, which is more scalable than the FDFET, is the
nonclassical device with the most potential for future nanoscale
CMOS applications.
ACKNOWLEDGMENT
The authors would like to thank L. Mathew for useful discus-
sions of FinFET technology.
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Ji-Woon Yang was born in Kwangju, Korea. He re-
ceived the B.S. and M.S. degrees in electrical engi-
neering from the Korea University, Seoul, Korea, in
1991 and 1995, respectively, and the Ph.D. degree
from the University of Florida, Gainesville, in 2004.
From 1995 to 1999, he was a Member of the
research staff of the Advanced Device Devel-
opment Group at the Hynix Semiconductor Inc.
(formerly Hyundai Electronics Industries Company),
Ichon, Korea, working on design, characterization,
optimization, and process integration of deep sub-mi-
crometer bulk and SOI MOSFET for 1-Gb DRAM. He and his team developed
the world’s first fully functional -Gb DRAM using partially depleted SOI
technology in 1997. He is presently working as a Post-Doctoral Researcher in
the Department of Electrical and Computer Engineering, University of Florida.
His research interests include design, analysis, simulation, and modeling of
high-scaled CMOS technology with emphasis on fully depleted SOI transistor
and double-gate FinFETs.
Jerry G. Fossum (S’69–M’71–SM’79–F’83) was
born in Phoenix, AZ. He received the B.S., M.S.,
and Ph.D. degrees in electrical engineering from
the University of Arizona, Tucson. His doctoral
research was in the area of semiconductor device
and integrated circuit (IC) modeling and simulation.
During his graduate program, he was a NASA Pre-
doctoral Trainee, a Graduate Teaching and Research
Associate, and an Industrial Consultant.
In 1971, he joined the Technical Staff of Sandia
Laboratories, Albuquerque, NM, where he was
engaged in various semiconductor device design and modeling activities,
including the development of silicon solar cells. In 1978, he moved to the
University of Florida, Gainesville, where he is now a Professor of Electrical
and Computer Engineering. His general area of interest is semiconductor
device theory, modeling, and design; his current research concerns physical,
process-based device modeling for IC simulation and technology CAD, with
emphasis on nonclassical SOI and multigate CMOS. He is the author or coau-
thor of more than 250 papers published in technical journals and conference
proceedings, and he has directed the research of 30 Ph.D. students.
Dr. Fossum is a Member of the Honorary Editorial Advisory Board of Solid
State Electronics. He was an Associate Editor for the IEEE TRANSACTIONS ON
COMPUTER-AIDED DESIGN from 1988 to 1991 and a Guest Editor for the IEEE
TRANSACTIONS ON ELECTRON DEVICES in 1998. In 1992, he and two of his stu-
dents received the Best Paper Award at the IEEE International SOI Conference.
He served on the Executive Committee of that conference from 1994 to 1997.
In 2004, he won the IEEE/Electron Devices Society J. J. Ebers Award for “out-
standing contributions to the advancement of SOI CMOS devices and circuits
through modeling.”