LAB Assignment 2

Subject: VLSI Design

Name: Anisha Nayak
ID: 2017H1230073G

Important points:

 Below are the voltage values used for the pre-layout and post-layout simulation of all the
circuits mentioned in this assignment.
High voltage – 1.8v
Low Voltage – 0v
Period – varying period for different inputs (a value between 50ns to 70ns)
Rise time, fall time, delay time – 1ns
Simulation time – 500ns

 First circuits of CMOS full adder and the third circuit for the custom equation given in the question are
scaled with the scaling factor 1.167:1. Transmission gate circuit is not scaled.

 The layout of all the circuits are drawn with minimum area.

 There will be many combinations of inputs for which output will change from high to low or low to
high. Based on the analysis, only few cases are considered for finding out the worst and best case of
delay. The delay values for other cases lie between the worst and best case delays.
1. Schematic of 1-bit full adder using CMOS technology.
Pre layout simulation results:
Layout of 1 bit full adder:
Post Layout simulation:
Delay values of Sum:
tpHL:
A B C Pre layout Post layout
Delay(in ps) Delay(in ps)
1 1 1→0 70.44 111.56
1→0 0 0 78.7 115
0→1 1 0 79.3 82.2
0→1 0→1 1→0 38.6 17.4
0→1 0 1 24.4 31.7
0 0 1→0 33.3 63.439

tpLH:
A B C Pre layout Post layout
Delay(in ps) Delay(in ps)
0 0→1 0 33.75 20.45
0→1 0 0 9.055 0.9
0 1 1→0 91.7 130.52
1→0 0 1 107.53 147.34
1→0 1→0 0→1 116.6606 178.93
1 1 0→1 7.101 0.41

Pre layout Propagation Delay of Sum= (79.3 + 116.6606)/2 = 97.9803ps

Pre layout Contamination delay of Sum= (24.4 + 7.101)/2 = 15.6005ps

Post layout Propagation Delay of Sum= (115 + 178.93)/2 = 146.965ps

Post layout Contamination delay of Sum= (17.4 + 0.41)/2 = 8.905ps
Delay values for Carry:
tpHL:
A B C Pre layout Post layout
Delay(in ps) Delay(in ps)
1→0 1→0 1 150.72 189.36
1 1→0 1→0 138.968 176
1→0 1→0 0 48.3 17.2
1→0 1 0 36.8 73.9
1→0 0 1→0 19.82 14.486
0 1→0 1→0 31.0775 2.7

tpLH:
A B C Pre layout Post layout
Delay(in ps) Delay(in ps)
0 0→1 0→1 120.237 114.4
0→1 0→1 0 134.1 131.7
0→1 0→1 0→1 24.54 3.66
0→1 0 1 8.84 9.7
0→1 1→0 0→1 21.446 0.66
1→0 0→1 0→1 21.546 7.5

Pre layout Propagation Delay of Carry= (150.72 + 134.1)/2 = 142.41ps

Pre layout Contamination delay of Carry= (19.82 + 8.84)/2 = 14.33ps

Post layout Propagation Delay of Carry= (189.36 + 131.7)/2 = 160.53ps

Post layout Contamination delay of Carry= (2.7 + 0.66)/2 = 1.68ps
Schematic for adder using transmission gate:
Pre layout simulation of adder using transmission gate:
Layout of adder using transmission gate:
Post Layout simulation of adder using transmission gate:
Delay values of Sum for adder implemented using transmission gate:
tpHL:
A B C Pre layout Post layout
Delay(in ps) Delay(in ps)

tpLH:
A B C Pre layout Post layout
Delay(in ps) Delay(in ps)

Pre layout Propagation Delay of Sum=

Pre layout Contamination delay of Sum=

Post layout Propagation Delay of Sum=

Post layout Contamination delay of Sum=
Delay values for Carry for adder implemented using transmission gate:
tpHL:
A B C Pre layout Post layout
Delay(in ps) Delay(in ps)

tpLH:
A B C Pre layout Post layout
Delay(in ps) Delay(in ps)

Pre layout Propagation Delay of Carry=

Pre layout Contamination delay of Carry=

Post layout Propagation Delay of Carry=

Post layout Contamination delay of Carry=
3. Schematic for F = (A(D + E) + BC)'
Pre layout simulation:
Layout:
Post Layout simulation:
Delay values:

tpLH:
A B C D E Pre layout Post layout
Delay(in ps) Delay(in ps)
0 1→0 1 0 0 9.967 31.158
1 1 0 1→0 0 30.88 50.5
1 1 1→0 1→0 1→0 153.82 178.49
1 1 1→0 1→0 0 124.326 148.86
0 1 1→0 0 0 35.821 57.93
1→0 1 0 1 1 60.25 76.07
1 1→0 1 1→0 0 112.58 138.03

tpHL:
A B C D E Pre layout Post layout
Delay(in ps) Delay(in ps)
1 0 0 0→1 0 57.421 51.54
0 0→1 0→1 0 0 92.48 81.42
0→1 0 0 0→1 0 134.8 131.17
0 0→1 1 0 0 36.72 24.26
0 1 0→1 0 0 14.58 0.07
0→1 0→1 0→1 0→1 0→1 0.33 8.58

Pre layout Propagation delay = (134.8 +153.82)/2 = 144.31ps

Pre layout Contamination delay= (9.967 + 0.33)/2 = 5.1485ps

Post layout Propagation delay= (131.17 + 178.49)/2 = 154.83ps

Post layout Contamination delay= (31.158 + 0.07)/2 = 15.614ps