Benq 8700 Service Manual PDF

DLP PROJECTOR
SERVICE MANUAL
MODEL：PE8700
CAUTION
BEFORE SERVICING THE PROJECTOR,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Contents
1. Safety Precautions 2
2. Servicing Precautions 2
3. Engineering Specification 3
4. Spare Parts List 23
5. Block Diagram 24
6. Packing Description 25
7. Appearance Description 26
8. Alignment Procedure 28
9. Trouble Shooting Guide 39
10. Factory OSD Operation 49
11. Firmware upgrade procedure 56
12. RS232 Codes 58
13. Schematics 69
1
1. Safety Precautions
1. Be sure to read this manual before servicing and save it for future reference.
2. The lamp becomes extremely hot during operation. Allow the projector to cool for
approximately 45 minutes prior to removing the lamp assembly for replacement. Do not
operate lamps beyond the rated lamp life. Excessive operation of lamps beyond the
rated life could cause them to explode on rare occasions.
3. Never replace the lamp assembly or any electronic components unless the projector is
unplugged.
4. To reduce the risk of electric shock, do not disassemble this appliance. Take it to a
qualified technician when service or repair is required. Incorrect re-assembly can cause
electric shock when the appliance is subsequently used.
5. Do not place this product on an unstable cart, stand, or table. The product may fail,
sustaining serious damage.
2. Servicing Precautions
1. When replace the lamp, be sure to avoid burns your fingers because the lamp becomes
too hot.
2. Never touch the lamp bulb with a finger or anything else. Never drop it or give it a shock.
They may cause bursting of the bulb.
3. This projector is provided with a high voltage circuit for the lamp. Do not touch the
electric parts of power unit when turn on the projector.
4. Do not touch the exhaust fan during operation.
2
3. Engineering Specification
Superscripts indicate the method in Appendix B used for a given measurement, unless otherwise
noted.
1.0 Image Quality All tests must adhere to the assumptions in Appendix A
1.1 Brightness (In ‘optical test’ mode)
1.1.1 Typical 660 ANSI Lumens
1.1.2 Minimum 450 ANSI Lumens
1.2 Brightness Uniformity (In ‘optical test’ mode)
1.2.1 Typical 73 %
1.2.2 Minimum 60 %
1.3 Contrast Ratio (In ‘optical test’ mode)
1.3.1 Peak Contrast 1400:1 (Minimum)
1.4 Light Leakage
1.4.1 Blue Edge Procedure: Test @ distance 3m with 100% white pattern
Criteria: Color coordinateΔx,Δy≦0.015 (compared with the
center)
1.4.2 Light Leakage out of < 1 lux @ diagonal 60”
Active Area
1.4.3 Reflective Edge Condition: distance 3m or image of 100” wide
Test Pattern: without connecting any source to projector
Criteria: No horizontal and vertical lines outside of the image
1.4.4 Blemish / Dust Test Pattern: Blue 90 with linear de-gamma / Gray 6
Criteria: Follow HD2 DMD image quality specifications

1.5 Color All Color Measurements must adhere to the assumptions in
Appendix A
TBD --PPR final
X Y
1.5.1 100% Gray (White) .274 ± .04 .318 ± .04
1.5.4 Red .647 ± .04 .341 ± .04
1.5.5 Green .304 ± .04 .566 ± .04
1.5.6 Blue .129 ± .04 .080 ± .04
20
1.6 Color Uniformity x y
1.6.1 100% Gray (White)
1.6.2.1 L1->L9 ±.04 ±.04
1.6.2.2 E10->E13 ±.04 ±.04
1.7 Mirror Defects / Dot Defects Dark pixels<=2, bright pixels =0 (See Appendix D)
1.8 Image Distortion Pincushion 1.0%
3
Keystone 1.0%
1.9 Descriptive Image Quality There should be no streaks or jitter, good saturated colors, and
crisp resolution. Must adhere to Appendix E
1.10 Lateral Color 1 Pixel
1). 52” Diagonal for OPT test;
2). Distance 3.0m for Focus test. ( Tele @ the same Throw
1.11 Screen Size for Testing
Distance. )
Criteria: Pixel clear ( same as test chart )
2.0 Optical
2.1 Optical Structure Single Chip 0.8” 12° tilt DMD ( HD2 ) from Texas Instruments
(HD2 Front Projection Image Quality Specification described in
Appendix D)
2.2 Projection Lens Manual Zoom & Focus
2.2.2 F/# 2.8
2.2.3 Throw Ratio 100” Diagonal at 3m ( Wide )
2.2.4 Zoom Ratio 1.2 : 1
2.2.5 Focus and flare As following chart:
2.3 Lamp
2.3.1 Maker Ushio
2.3.2 Model NSH 210 MD
2.3.3 Type DC lamp
2.3.4 Lamp Wattage 210 watts
2.3.5 Lamp life 1000 Hours ( Typical )
2.4 Focus Distance 1.5 – 5m
2.5 Keystone Correction
2.5.1 Electronic ± 12°
2.6 Colors 24-bit color
2.7 Native Resolution
4
2.7.1 PC Mode 1280 x 720 pixels
1280 x 720 pixels
2.7.2 Video Mode
3.0 Mechanical & Cosmetic
3.1 Dimensions 400L x 347W x 116H
3.2 Weight 16.7 lbs (7581 g)
3.3 Security Slot Kensington compatible slot 150N break away force
3.4 Feet 4 adjustable feet
3.5 Lamp Replace Position Front
4.0 Compatibility Supporting timing: see appendix E
4.1 RGB PC Compatible VGA, SVGA, XGA
4.2 Video Signal Composite, S-Video, Y/CB/CR
4.3 HDTV DTV Y/PB/PR , DTV RGBHV ,DTV DVI-I ( 480P, 1080i, 720P,
576P, 540P)
4.4 Image Inversion Mirror, Upside-down, Mirror Upside-down
4.5 Scaling Scaling from other resolutions to native by O-plusTM scaling
chip
4.6 Aspect ratio ANAMORPHIC, 4x3, LETTER BOX, VIRTUAL WIDE.
5.0 Interface Connectors
5.1 RGB Input DVI x 1 (include 5.2.5)
5.2 Video Input
5.2.1 Composite RCA x 1

5.2.2 S-Video S-Video x 1
5.2.3 Component RCA x 3
5.2.4 Progressive component BNC x 5
and DTV RGBHV
5.2.5 Digital Video DVI x 1 with HDCP
5.3 RS232C Input Telephone jack
6.0 Electrical
6.1 RGB
6.1.1 Input
6.1.1.1 Amplitude 0.7 ± 0.1 VPP at 75Ω termination, positive bright
6.1.1.2 Input 75Ω
Impedance
6.1.1.3 Synch TTL compatible
6.1.2 Computer The unit should be compatible with normal computer formats
Compatibility ranging from VGA to XGA.
6.1.3 Video Compatibility Don’t use BUBUKAU DVD for test equipment.
5
6.2 Control
6.2.1 IR Receivers
6.2.1.1 Location 2receiver, located on the front and rear of this projector
6.2.1.2 Range 8m ( front ) / 5m ( rear ) with 30 degree horizontal Angle and 15
degree vertical angle
7.0 Power Requirements
7.1 Power Supply VAC 100 – 240 Full range switch (50/60Hz), 3 Wire Grounded
7.2 Power Consumption 310W max.
7.3 Power Connector IEC
8.0 Audible Noise Level 34 dB ( Max) @ 25℃ sea level
9.0 Thermal
9.1 Surface Metal 60°C
9.2 Surface Plastic 65°C
9.3 Exhaust Air 80°C
9.4 Screws, Terminals 70°C
10.0 Contamination
10.1 Prevention Optical system is closed
10.2 Dust in Optical Path No noticeable dust
11.0 Included Accessories
11.1 Cables Power Cord Set (US, UK, Euro) x 1, VGA Cable (1.8m) x 1,
Projector Common Cable x 1
11.2 Printed Matter User’s manual
11.3 Remote Control IR Remote x 1, AAA Batteries x 2
12.0 User Interface
12.0 Backlight NO
12.1 Operator Panel YES
12.2 Indicators Power Status LED, Lamp Status LED
12.3 Remote Control Front IR receiver , Rear IR receiver
12.4 Onscreen Menu Should be in 3 languages (English, French, Spanish )
12.8 User’s Manual Should be in 3 languages (English, French, Spanish )
13.0 Reliability
13.1 General Failure Def. See Appendix B
13.2 MTBF 20000 hours except for DMD chip , lamp , fans and color wheel.
14.0 Environmental
14.1 Operating 10 – 35°C, 20 – 90%RH, without condensation
14.2 Storage -10 – 70°C, 20 – 90%RH, without condensation
14.3 Altitude 0 – 6000 feet above sea level, ambient 30 ℃
14.4 Shock
6
14.4.1 Straight Drop 50mm
14.4.2 Tilt Over Should be able to fall over from tilting without taking any
damage. Must Adhere to Appendix B
14.5 Gas No corrosive, toxic, or combustible gas should be emitted
14.6 Electrostatic Discharge comply to the acceptance criteria as specified in EN
61000-4-2/1995
15.0 Regulatory UL, CE, FCC Class B. Must Adhere to Appendix B Section 10.0
15.1 Safety Requirements UL compliance: UL6500 (2th Version)
CSA compliance: E60065-00
TUV compliance: IEC60065:2001
CCC: GB8898; GB13837; GB17625.1: 1998
15.1 EMI Requirements 1. CE Mark compliance: EMC: 89/336/EEC
EN 55013:1990+A12 :1994+A13 :1996+A14 :1999
EN 61000-3-2:1995+A1 :1998+A2 :1998+A14 :2000
EN 61000-3-3:1995+A1 :2001
EN 55020:1994+A1 :1996+A12/A13/A14 :1999
IEC 61000-4-2/2001
IEC 61000-4-3/2001
IEC 61000-4-4/1995+A1:2000+A2:2001
2. FCC
FCC Part 15B
3. C-Tick
ASIN2S 1053:1996
4. VCCI
VCCI/2002(15th Edition)
16.0 Packaging
16.1 Packaging Form Must adhere to attached file
16.1.1 Dimensions 537 x 520 x 260 mm
16.1.2 Weight TBD
16.1.3 Palletization 1140 x 1050 x 120 mm
16.1.4 Carton Labeling Must adhere to attached file
16.2 Vibration Must adhere to Appendix B
16.3 Drop Test Must adhere to Appendix B
7
Appendix A Optical Measurement
This part of the Optical Test Instruction describes those measurements to be executed
during the production of the optical engines.
Content:
A1 BRIGHTNESS
A2 BRIGHTNESS UNIFORMITY
A3 BRIGHTNESS DIFFERENCE
A4 ANSI CONTRAST
A5 PEAK CONTRAST
A6 LIGHT LEAKAGE
A7 IMAGE DISTORTION
A8 THROW RATIO
A9 ZOOM RATIO
A10 FOCUS RANGE
A11 COLOR
A12 COLOR UNIFORMITY
A13 OPTICAL KEYSTONE (FIXED)
General requirements
1. The unit shall be allowed to stabilize without further adjustment for a
minimum of 10 minutes, at nominal ambient room temperature of 25°C,
before making measurements.
2. Measurements shall take place in a light proof room, where the only source of
illumination is the projector. Less than 1% of the light on the screen shall be
from any source other than the projector.
3. All measurements shall be made on flat screens that do not provide any
advantage to the performance of the unit
4. All measurements shall be made at standard color temperature setting, 100%
white image (per ANSI IT7.228-1997), except where noted
8
Practical consideration
1. When measuring contrast manually, operators should not wear white
clothing since light reflected from white clothing can influence the
measurement.
2. Unless otherwise specified the projection lens is set in the widest zoom
position since zoom function can influence the measurement.
3. Measurement should be performed with Minolta Chromameter, Model
CL-100, or equivalent.
A1. BRIGHTNESS
Unit: Lumen
Brightness: Default
Contrast: Default
W: width of projected image; H: height of projected image
A (Area) = W * H (in meters)
L1 + L2 + L3 + L4 + L5 + L6 + L7 + L8 + L9
ANSI Lumens = (lux ) ∗ A( m 2 )
9
1 1
W W
3 6
1
H
6
1
H
3
9
A2. BRIGHTNESS UNIFORMITY
Unit: %
Brightness: Default
Contrast: Default
Uniformity = MIN ( E10, E11, E12, E13)

L1 + L2 + L3 + L4 + L5 + L6 + L7 + L8 + L9
9
1/20w
E10 E11 1/20h
L5
E12 E13
A3. BRIGHTNESS DIFFERENCE

Unit: %
Brightness: Default
Contrast: Default
Brightness Difference=
( MAX ( E 10 , E 11, E 12 , E 13 ) − MIN ( E 10 , E 11, E 12 , E 13 ))
L1 + L 2 + L 3 + L 4 + L 5 + L 6 + L 7 + L 8 + L 9
9
A4. ANSI CONTRAST

Unit: Contrast : 1
Brightness: Default
Contrast: Default
Contrast Ratio shall be determined from illuminance values obtained from a
black-and-white ”chessboard” pattern consisting of 16 equal rectangles. The
white rectangles shall be at 100% gray and the black rectangles at 0% gray.
Illuminance measurements shall be made at the center of each of the rectangles.
Contrast Ratio = Average lux value of the white rectangles/Average lux value
of the black rectangles
10
A5. PEAK CONTRAST
Unit: Contrast : 1
Brightness: Default
Contrast: Default
Contrast Ratio = Lux value at the center of a solid white screen/the lux value
of a solid black screen
A6. LIGHT LEAKAGE

Unit: Lux
Brightness: Default
Contrast: Default
Leakage = The maximum light leakage of a solid black screen outside the
projected image
A7. IMAGE DISTORTION

Unit: %
Brightness: Default
Contrast: Default
Measurement procedure:
Measure the dimensions H1, H2 and H3, with H3 at the half image width, as
shown above for both zoom settings. For each the distortion is defined as:
H1 + H 2 − 2 * H 3
TV − dist = *100%
2* H3
All should be within the absolute specification tolerance.
A8. THROW RATIO

Unit: Ratio : 1
Brightness: Default
Contrast: Default
Throw ratio = projection distance / the width of the projected image
11
A9. ZOOM RATIO
Unit: Ratio : 1
Brightness: Default
Contrast: Default
Zoom ratio = maximum / minimum image diagonal size at a fixed projection
distance.
A10. FOCUS RANGE
Unit: m (Max~Min)
Brightness: Default
Contrast: Default
The minimum/maximum focus distance is the minimum/maximum projection
distance (front side projection lens and the image lane), expressed in meter,
at which the image is still at its best for focus.
A11. COLOR
Unit: x, y
Measurements at the center (except in the case of color uniformity
measurements) of a screen which is entirely of the color being measured and
at default brightness and contrast settings.
A12. COLOR UNIFORMITY
Unit: x, y
Difference between any two points out of Lx and Ex should not exceed the
specification for the given color.
A13. OPTICAL KEYSTONE (FIXED)
Unit: %
Brightness: Default
Contrast: Default
Measure the dimensions W1, W2 and W3 at the half image height, as shown
above. The distortion is defined as:
W1 − W 3 W 2 −W3
TV − dist = *100% & TV − dist = *100%
W3 W3
12
Appendix B Design Verification Test Procedure
1.Purpose
This standard establishes the environmental specification for projector related
products, which defines the level of product performance and reliability in the field. It is not
necessary the intent of these specification to simulate a typical user environment, but rather
to provide for a level of product robustness that when applied over a wide range of
manufacturing variability and environmental usage conditions.
2.Test Summary
Dynamic Testing Specification

Package Drop 76cm, 1 drop per orientation, all 6 primary surfaces, plus a selected
corners, and three selected edges, total of 10 drops
Package Vibration Random , 0.01g2/Hz, 5~100Hz, all primary axis, 20 min per orientation,
total of 60min
Sine, 0.5g, 5~200Hz, 1 octave/min, 15 min dwell on each resonant
frequency, all primary axis, one sweep (30min minimum) per orientation,
total of 90+min
Shock, non-operating 50g, 20ms half-sine, all primary axis, 1 shock per orientation, total of 3
shocks
Security Lock 150N break away force
Fragility Shock, 50g, 20ms half-sine, all primary axis, 1 shock per orientation, total
of 3 shocks
Accelerate Life Test (operating), 65 oC, 72hr
Thermal shock(bare board), -65~125 oC, 48hr
Input Voltage, 90~264V
Input RGB signal, 0.7V±0.1
Atmospherics
Temperature/Humidity, 10~35oC/10~80RH, 48hr
operating
Temperature/Humidity, -10~70oC/10~80RH, 48hr
non-operating
Altitude, operation 0~6000ft@30oC, 4hr
Safety/EMC
UL/cUL
TUV Rheinland
Fcc/CE/C-Tick
13
3.Definition
3.1 Failure Criteria:
The product is expected to perform to its full potential without loss of function,
performance, critical parametric changes, and other undesirable anomalies, over the
applied boundaries of this specification. The following product failure are not allowed within
the boundaries defined in this specification:
1.Failure including permanent damage, critical parametic changes (optical
performance defined in Appendix A), and latent defects.
2.Failure requiring operator intervention.
3.Failure violating external laws, regulatory agency standards, and government
directives.
4.Failure resulting in a safety, potential safety, issue.
3.2 EUT: Equipment under Test
3.3 Q: Peak Acceleration Response divided by acceleration input peak
4.Test Order
Atmospherics, Dynamic, and Safety test sets require separate units and can be
processed in parallel. EUT testing shall be performed serially within each set.
Set 1 (3 units) Set 2 (3 units) Set 3

Dynamics: Atmospherics: Safety/EMC:
Package Drop Temperature/Humidity, Operating EFT
Package Vibration Temperature/Humidity, ESD
Non-operating
Shock Altitude, Operating EMI-Radiated
Bench Drop Aging EMI-Conducted
EMI-Susceptibility
14
Appendix C Drawings and Attachments
Drawing 1: Top view of BENQ PE8700 video projector
15
16
Appendix D HD2 Front Projection Image Quality Specification
1. SCOPE
This document specifies the image quality requirements applicable to the HD2 Component
Set for Front Projection image display. The HD2 Component Set provides digital imaging
functionality based on Digital Micromirror Device (DMD) technology.
2. DEFINITIONS
2.1 Blemish
A blemish is an obstruction (dark blemish), reflection, or refraction of light (light blemish)
that is visible, but out of focus in the projected image under specified conditions of
inspection (see Table 1). It is caused by a particle, scratch, or other artifact located in the
image illumination path.
2.2 Dark pixel

A dark pixel is a single pixel or mirror that is non-functional (stuck) in the OFF position.
2.3 Bright pixel

A bright pixel is a single pixel or mirror that is non-functional (stuck) in the ON position.
2.4 Unstable pixel

An unstable pixel is a single pixel or mirror that does not operate in sequence with
parameters loaded into memory. The unstable pixel appears to be flickering
asynchronously with the image.
2.5 Adjacent pixels

Adjacent pixels are defined as sharing a common border or common point.
2.6 Border defects

Border defects are bright blemishes (see 2.1) or bright pixel defects (see 2.3) in the
non-active area that may be visible in front projection mode.
2.7 Blue test screen

This screen is used to test for major dark blemishes and dark pixels. All areas of the screen
are colored at a specific blue level, based on MS Paint 0-255 RGB scale:
Major Dark Blemish
Blue Value 90
Red Value 0
Green Value 0
17
2.8 Gray 6 test screen
This screen is used to test light blemishes and bright pixels. All areas of the screen are
colored at a specific gray level, based on MS Paint 0-255 RGB scale:
Major Light Blemish

Blue Value 6
Red Value 6
Green Value 6
2.9 Gray 10 test screen

This screen is used to test light blemishes and bright pixels. All areas of the screen are
colored at a specific gray level, based on MS Paint 0-255 RGB scale:
Major Light Blemish

Blue Value 10
Red Value 10
Green Value 10
2.10 White test screen

This screen is used to test light border blemishes and bright pixels. All areas of the active
area are colored at a specific gray level, based on MS Paint 0-255 RGB scale:
Major Dark Blemish

Blue Value 255
Red Value 255
Green Value 255
2.11 black test screen
Major Dark Blemish

Blue Value 0
Red Value 0
Green Value 0
18
2.12 Red Ramp test screen
Major Dark Blemish

Blue Value 0
Red Value Start 0,end 255
Green Value 0
3. ACCEPTANCE REQUIREMENTS
3.1 Test Conditions (as tested in OEM projector)

· Projector degamma correction shall be linear. Using HD Control “Curtain” Mode is
equivalent.
· Image noise reduction algorithms “Blue Noise STM” and “Boundary Dispersion” shall be
set to “off”.
· Projector shall be used in front projection mode using a customer-specified screen, and
OEM optical system.
· The diagonal size of the projected image shall be 52 inches (132cm).
· The projected image shall be inspected from a 60 inches (1.52 meter) minimum viewing
distance.
· Projector will be properly focused on the DMD array as shown on the screen.
· Testing time is limited to 20seconds per screen.
· Refer to Table 1 for acceptance criteria, in specified order:
TEST TEST SCREEN ACCEPTANCE CRITERIA

ORDER
1 Major Dark Blemish Blue 90 No dark blemishes visible on Blue 90
2 Dark Pixel Blue 90 0 dark pixels allowed in Zone A
Zoned Screen (see <=2 dark pixels allowed in Zone B
below figure 1) No adjacent dark pixels
3 Border Defects Gray 10 No border defects visible
4 Major Light Blemish Gray 6 No light blemishes visible on Gray 6
19
5 Light Pixel Gray 6 No light pixels visible on Gray 6
6 Minor Blemishes White or Black Total of Dark and Light Blemishes ≦

4
(See Test 4 , 5)
7 Unstable Pixel Red Ramp No unstable pixels
Screen(or any
other
TABLE 1. Image Quality Specification
Notes:
1. The acceptance basis for all cosmetic DMD defects will be the projected image tests
referenced in Table 1.
2. Projected blemish numbers include the shadow of the artifact in addititon to the artifact
itself.(Count=4)
4. The projected image shall not contain any blemish more than 15 cm long, measured on
a 1.32m diagonal screen.
20
Appendix E Supporting Timings
Table 1: Support Timings by DVI-I Input (Analog or Digital PC signals)
Resolution Vert. Freq Hori. Freq Pixel freq Digital (D)/ Polarity
(Hz) (kHz) (MHz) Analog (A)
1 VGA 640 x 400 70.089 31.470 25.167 D/A -/+
2 VGA 640 x 480 59.590 31.470 25.167 D/A -/-
3 VGA 640 x 480 85.008 43.269 36.0 D/A -/-
4 SVGA 800 x 600 60.317 37.879 40.0 D/A +/+
5 SVGA 800 x 600 75.000 46.875 49.5 D/A +/+
6 SVGA 800 x 600 85.061 53.674 56.25 D/A +/+
7 XGA 1024 x 768 60.004 48.363 65.0 D/A -/-
8 XGA 1024 x 768 75.029 60.023 78.75 D/A +/+
9 XGA 1024 x 768 84.997 68.677 94.5 D/A +/+
Table 2: Support Timing by DVI-I Input
Index Format Line Pixel Frame Line Line Frame Frame H back H sync V back V sync
name Rate Rate Rate active total active total porch width porch width
(kHz) (MHz) (HZ) (pixel) (pixel) (line) (line) (pixel) (pixel) (line) (line)
1 480p59 31.469 27 59.94 720 858 480 525 59 63 30 6
2 576p50 31.25 27 50 720 864 576 625 68 64 39 5
3 720p50 37.5 74.25 50 1280 1980 720 750 260 40 20 5
4 720p59 44.955 74.176 59.94 1280 1650 720 750 260 40 20 5
5 720p60 45 74.25 60 1280 1650 720 750 260 40 20 5
6 1080i25 28.125 74.25 25 1920 2640 1080 1125 148 44 15 5
7 1080i29 33.716 74.176 29.97 1920 2200 1080 1125 192 44 15 5
8 1080i30 33.75 74.25 30 1920 2200 1080 1125 192 44 15 5
21
Table 3: EDTV and HDTV Timing supported by component (YPBPR) and RGBHV Input
Index Format Line Pixel Frame Line Line Frame Frame H back H sync V back V sync
name Rate Rate Rate active total active total porch width porch width
(kHz) (MHz) (HZ) (pixel) (pixel) (line) (line) (pixel) (pixel) (line) (line)
1 480i 15.734 13.5 59.94 720 858 480 525 59 63 30 6
2 576i 15.625 13.5 50 720 864 576 625 68 64 39 5
3 480p 31.469 27 59.94 720 858 480 525 59 63 30 6
4 576p 31.25 27 50 720 864 576 625 68 64 39 5
5 720p50 37.5 74.25 50 1280 1980 720 750 260 40 20 5
6 720p59 44.955 74.176 59.94 1280 1650 720 750 260 40 20 5
7 720p60 45 74.25 60 1280 1650 720 750 260 40 20 5
8 1080i25 28.125 74.25 25 1920 2640 1080 1125 148 44 15 5
9 1080i29 33.716 74.176 29.97 1920 2200 1080 1125 192 44 15 5
10 1080i30 33.75 74.25 30 1920 2200 1080 1125 192 44 15 5
22
Chapter 4 Spare Parts List
Projector PE8700 99.J5877.B21
NO Parts NO Description
1 55.J2003.001 IR BD HT480W MI
2 55.J5801.011 PCBA MAIN/BD FOR BENQ
3 55.J5824.001 PCBA DMD BOTTOM/BD HT720G
4 55.J1313.001 PCB 1L SENSOR-B BD SL700 X MI
5 65.J2004.001 COLOR WHEEL SIX SEGMENT UNAXI
6 55.J5802.001 PCBA DMD/BD HT720G
7 65.J5801.001 ASSY LENS ZOOM HT720G PROT
8 71.00HD2.A00 IC MUSTANG DMD PREMIUM CLGA
9 65.J3403.001 ASSY BALLAST210W/USHIO DX660
10 55.J2006.010 PCBA KEYPAD/BD HT720G BENQ
11 55.J5817.001 PCBA TRANSLATION/BD HT720G
12 60.J2020.021 ASSY CVR BASE HT720W/BENQ
13 60.J2023.022 ASSY L/C HT720W/BENQ
14 60.J2037.011 ASSY CVR FRONT HT720W/BENQ
15 60.J2038.011 ASSY CVR BACK CONTOR HT720W
16 60.J2112.001 ASSY CVR LENS HT720W BENQ
17 55.J2013.001 PCBA THERMAL SENSOR/B HT480W
18 55.J2021.001 PCB FPC/BD FOR HT480W
19 55.J5810.011 PCBA CONNECTOR/BD FOR BENQ
20 55.J2005.001 PCBA POWER BD HT480W MI
21 55.J5811.001 PCBA PFC/BD HT720G
22 44.J2003.021 CTN AB 455X500X228 HT720G/BEN
23 47.J2008.001 CUSHION FRONT EPE HT480W
24 47.J5804.001 CUSHION REAR EPE HT720G BENQ
25 50.J2103.501 CABLE RGA/DVI-A (WHDDC) 1.8M
26 50.L2508.501 SIGNAL/C DUAL DVI-D/DVI-D 200
27 60.J2028.R01 ASSY AV CABLE RUNCO CL-500
28 98.J2032.B01 HT480W BENQ REMOTE CONTROL
29 60.J2104.CG1 ASSY CSD LAMP MODULE PE8700
23
5. Black Diagram
Conntctor Board Main Board DMD Board
RGB DVI Sil169

(U17)
DMD
MUX
RGB PC
(U2,U3,U4)
RGB/YPbPr ADC AD9883
Color
HD2
BNC (U7) Scaler Cheel
RM1-A
(U5)
YCbCr Reset IC
MUX De-interlace Blaster Lamp
(U18)
YPbPr (U5) SII504 Video Port
(U2)
SDRAM
S-video Video Decoder (U19,U20,
Video 400V
U21)
SAA7118
YCbCr
IR Board (U10) SDRAM MCU503
PFC
(U3) (U4)
Board
RS232
RS232 RJ11 Download SRAM
(U14) (U9)
3.3V
CPU RDC8820 Frash
IR Power
IR (TOP) (U12)
(U10) (U12)
Board 5V
RS232
12V
Hardware
12V Monitor
12V Trigger O/P (Q2,Q3) (U14)
IR
IR (front) IR BoardBoard Translation Board
Keyboard
Fan Protection
Driver Circuit
(U1,U3) (U4)
Thermal Thermal
Fans
Sensor Break
24
6. Packaging Description
25
7. Appearance Description
26
27
8. Alignment Procedure
1. DMD Bias Voltage Alignment

Equipment:
- None
Procedure:
1. Watch DMD chip Label
2. Switch the DIP switch on DMD board according to the character on the DMD chip
B C D E
1 of SW H1 1 0 1 0
2 of SW H2 1 1 0 0
0: Left; 1:Right
2.Color Wheel Delay Alignment
Equipment:
- Battery Biased Silicon PIN Detector
- Oscilloscope
- Probe
OSD Default value used for color delay alignment
Item Value Item Value

USER>DVI-A> Factory>DLP>
Brightness 0 Brightness 0
Contrast 30 Contrast 49
Color 60 CW delay 20
Tint 15 User>Setup>Whit
Sharpness 0 Red Gamma 66
Filter 2 Green Gamma 66
Color Temp 0 Blue Gamma 66
R gain 512
G gain 512
B gain 512
R Offset 0
G Offset 0
B Offset 0
The default values let optical engine to get maximum contrast and brightness.
28
Procedure:
1. Probe impedance matches 50 ohm
2. Change Timing and pattern of pattern generator :
Timing : 800x600@60Hz (H:37.879Khz,V:60.317Hz)
pattern : full white
3. Adjust user & factory OSD values to default.
4. Open Factory OSD, and select color wheel delay item.
5. The image will become white.
6. Put the detector on the screen that white image was projected.
7. Watch the oscilloscope and notice the square waveform
8. Use the “ ” and “ ” key to increment or decrement the color wheel delay value
9. No matter the waveform is square or not, let the waveform was lagged first
Lag Exact
10. Then increment or decrement the value to let the waveform to be square
11. Do not adjust too much, let the signal get ahead, if it happens, go back to step 7 and do
it again.
Ahead
12. Select “Save Setting” at “Factory OSD>Factory>”.
29
3. DVI-Analog Color Alignment Procedure
Default valve(User menu)
contrast color Sharpness
Video 17 23 3
S-Video 17 23 1
Comp 17 30 0
Comp-HD 17 30 3
RGBHV 17 30 3
DVI-I 17 30 1
The Gamma(RED ,GREEN,BLUE) is 66 for temperature 0,1,2,3,4.
Equipment:
- Pattern generator (Chroma 2250)
- Lux meter ( CL-100)
OSD Default value used for DVI-Analog color alignment

USER>Picture> Factory>HDADJ>RG
Brightness 30 R offset 55
Contrast 17 G offset 63
Color 30 B offset 62
Tint 15 R Gain 89
Sharpness 1 G Gain 89
Filter 1 B Gain 89
Color Temp 2
Factory>DLP
Brightness 0
Contrast 49
User>Setup>White
Gamma Red, Green, 66
Gamma Red, Green, 0
30
Procedure:
A. Black Level Adjustment: (DLP brightness)
1. Change pattern of pattern generator :
Pattern : Black (Gray 0)
2. Adjust DLP Brightness to let the black picture to just distinguish.
B. White Level Adjustment: (AD contrast---R,G,B gain)

1. Change pattern of pattern generator :
pattern : White (100% Gray)
2. Use Lux meter to measure the white level. Adjust the contrast value of AD9883 (RGB)
to let the light output to just max.
3. Change to 32-gray (0 ~ 100%) pattern. All steps must appear,
C. Offset adjustment at low brightness (AD R, G, B offset)

pattern : 10% Gray
2. Set user color temp to 6500K.
3. Adjust AD9883 Red and Blue Offset to meet 6500K color spec.
D. Color Temperature at high brightness (Scalar Gamma R, G, B Gain)

Timing : 800x600@60Hz (H:37.879Khz,V:60.317Hz)
Pattern : 80% gray
2 Color temperature spec: CIE 1976 u’, v’ chromaticity)
Color temperature 5400°K 6500°K 7500°K
27u ' 0.333 0.312 0.296
x=
18u ' − 48v ' + 36
12v ' 0.333 0.329 0.316
y=
18u ' − 48v ' + 36
4x 0.210 0.197 0.190
u' =
− 2 x + 12 y + 3
9y 0.473 0.468 0.459
v' =
− 2 x + 12 y + 3
Deviation: <=0.010 <=0.010 <=0.010
2 2
　u’v’= ( ∆u ' + ∆v '
Color Temp 4 = color temp is the same as that of 6500K
31
3 The variance of color coordinate via R,G,B gains:
x Y
R↓ X↓ -
G↓ - y↓
B↓ X↑ y↑
4. Adjust 6500K temperature color by changing Gamma-Rgain, Ggain, and Bgain.

5. Open Factory OSD and set the factory default value :
user>setup>white C0 C1(5400k C2(6500k C3(7500k

Gamma-Rgain 512 512 512 512
Gamma-Ggain 512 412 467 479
Gamma-Bgain 512 398 452 490
User the lux meter and adjust Gamma-Rgain, Gamma-Ggain, & Gamma-Bgain to
meet the spec.
6. Press “Save Graphics Color Temp” to save current setting into memory.
8.Change pattern to 10% gray pattern and measure the color temp. If 6500K color spec is
not met, repeat all procedures in C and D.
9. Follow step 1 to 8 to adjust 5400K, 7500K color temperature.
10. For auto-alignment, use Command Y31/Y32/Y33 to save 5400K/6500K/7500K
temperature
11. For auto alignment, use Command to reset Temp4 color temp to 6500K
4. YPBPR Color Alignment

(A) YPbPr Component:
Equipment:
- Pattern generator (VG-828)
OSD Default value used for YPBPR color alignment

USER>Picture>
Brightness 30
Contrast 17
Color 30
Tint 15 Factory>HD ADJ>YPbPr>
Sharpness 3 Brightness 60
32
Filter 1 Contrast 76
Color Temp 2 Saturation 49
Pb offset 60
Pr offset 60
Procedure:
(a). PBPR Offset adjustment: (AD PB, PR Offset)
1. The variance of color coordinate via Pb offset and Pr offset:

x y
Pb offset ↓ x↓ y↓
Pb offset ↑ x↑ y↑
Pr offset ↓ x↑ y↓
Pr offset ↑ x↓ y↑
If we line the x and y, then the Pb offset is the shift action and the Pr offset is the
rotational action.
2. Connect power, YPbPr Video into projector.
Timing : 480P(H:31.54 KHz,V:60.08 Hz)
pattern : 10gray Pattern
4. Turn on projector
5. Set user OSD values to default.
6. Enter factory mode.
7. Set Factory values to default.
8. Follow the Pb, Pr offset adjustment flow chart to adjust color temperature to 6500K
b). Gray Level: (AD YPBPR Contrast, Brightness)

Timing : 480P(H:31.54 KHz,V:60.08 Hz)
pattern : gray 32( or gray16 only for overscan)
2. Adjust the Brightness of AD9883 (RGB) to let the black level of the gray
32 to just distinguish. Use Lux meter to measure the white level of the gray 32. Adjust
the contrast value of AD9883 (RGB) to let the light output to just max.
3. Check the 32 levels of gray. All steps must appear,
33
(c). Saturation Level: (Scalar)
Timing : 480P(H:31.54 KHz,V:60.08 Hz)
pattern : 100% blue
2. Adjust saturation and use lux meter to measure to let the light output just max.
Use Lux meter to

read the coordinate of
black and the value
note (x1,y1).
Case Case Case Case

x1>x0 & y1>y0 x1<x0 & y1<y0 x1>x0 & y1<y0 x1<x0 & y1>y0
Decrease Pb offset Increase Pb offset

Increase Pr offset until Decrease Pr offset
until x<=x0 or until x>=x0 or
x<=x0 or y>=y0 until x>=x0 or y<=y0
y<=y0 y>=y0
A B C D
Case x<=x0: Case y<=y0: Case x>=x0: Case y>=y0:

Case x<=x0: Case y>=y0: Case x>=x0: Case y>=y0:
The value note (x2,y2). The value note (x2,y2). The value note (x2,y2). The value note (x2,y2).
Dy = y2 - y0. Dx = x2 - x0. Dy = y0 - y2. Dx = x0 - x2.
Decrease Pb offset until the y Decrease Pb offset until the x Increase Pb offset until the y Increase Pb offset until the x
C B A D
value <= y2 - 1/2Dy . Now, the value <= x2 - 1/2Dx . Now, the value >= y2 + 1/2Dy . Now, the value >= x2 + 1/2Dx . Now, the
reading of the Lux meter = reading of the Lux meter = reading of the Lux meter = reading of the Lux meter =
(x3,y3) and x3 will < x0, y3 will (x3,y3) and x3 will > x0, y3 will (x3,y3) and x3 will > x0, y3 will (x3,y3) and x3 will < x0, y3 will
> y0. < y0. < y0. > y0.
Decrease Pr offset the x value Increase Pr offset the x value will Increase Pr offset the x value will Decrease Pr offset the x value
will increase and y value will decrease and y value will increase decrease and y value will increase will increase and y value will
decrease to meet the spec. to meet the spec. to meet the spec. decrease to meet the spec.
34
Case x1>x0 & y1 > y0 :
y =.331
dy=.01
1/2dy=0.005
x =.291 x =.281 y =.321 dec. Pb y =.316
dec. Pb dec. Pr
x0 =.281 y0 =.311 x0 =.281 y0 =.311 x0 =.281 y0 =.311 x =.281 y =.311
x =.276
x =.301
dx=.01
1/2dx=0.005
y =.321 x =.291 y =.311 dec. Pb x =.286
dec. Pb inc. Pr
x0 =.281 y0 =.311 x0 =.281 y0 =.311 x0 =.281 y0 =.311 x =.281 y =.311
y =.306
Case x1<x0 & y1 < y0 :

dy=.01
1/2dx=0.005
inc. Pb x =.286
inc. Pb inc. Pr
x0 =.281 y0 =.311 x0 =.281 y0 =.311 x0 =.281 y0 =.311 x =.281 y =.311
x =.281 y =.306
x =.271 y =.301
y =.291
dx=.01
1/2dx=0.005 y =.316
dec. Pb inc. Pb dec. Pr
x0 =.281 y0 =.311 x0 =.281 y0 =.311 x0 =.281 y0 =.311 x =.281 y =.311
y =.311 x =.276
y =.301
x =.271
x =.261
Case x1>x0 & y1 < y0 :

dy=.01
1/2dx=0.005
x =.291 inc. Pb x =.286
inc. Pr x =.281 inc. Pr
x0 =.281 y0 =.311 x0 =.281 y0 =.311 x0 =.281 y0 =.311 x =.281 y =.311
y =.306
y =.301
y =.291
x =.301 dx=.01
1/2dx=0.005
x =.291 y =.311 dec. Pb x =.286
inc. Pr inc. Pr
x0 =.281 y0 =.311 x0 =.281 y0 =.311 x0 =.281 y0 =.311 x =.281 y =.311
y =.306
y =.301
Case x1<x0 & y1>y0

y =.331
dy=.01
1/2dy=0.005
y =.321 dec. Pb y =.316
dec. Pr dec. Pr
x0 =.281 y0 =.311 x0 =.281 y0 =.311 x0 =.281 y0 =.311 x =.281 y =.311
x =.281 x =.276
x =.271
dx=.01
y =.321 1/2dx=0.005
inc. Pb y =.316
dec. Pr dec. Pr
x0 =.281 y0 =.311 x0 =.281 y0 =.311 x0 =.281 y0 =.311 x =.281 y =.311
y =.311 x =.276
x =.271
x =.261
35
5. TV Color Alignment Procedure
5.1 TV Color Temp Alignment
Equipment:
OSD Default value used for YCBCR color temp alignment

USER>Picture>
Brightness 30
Contrast 17
Color 30
Tint 15 Factory>SD
Sharpness 0 Brightness 180
Filter 3 Contrast 92
Color Temp 2 Saturation 90
User>Setup>White
Gamma Red, Green, 66
Gamma Red, Green, 0
1. Connect the signal to YCBCR component connector, and change Timing and pattern of
pattern generator :
Timing : NTSC(H:15.73 KHz,V:29.96 Hz)
pattern : 80% Gray
2. Color temperature spec:
Color temp. 4 is the same as that of 6500K
3. The variance of color coordinate via R,G,B gains:
4. Adjust 5400K / 6500K / 7500K temperature color.
5. Open Factory OSD and set the factory default value :
User>setup>white C0 C1(5700k C2(6500k C3(9300k

Gamma-Rgain 512 512 512 512
Gamma-Ggain 512 416 467 490
Gamma-Bgain 512 408 460 508
36
6. User the lux meter and adjust Gamma-Rgain, Gamma-Ggain, & Gamma-Bgain to meet
the spec.
7. Press “Save Color Temp. Videos > AS Color Temp 5400” to save into memory.
8. Repeat 6~7 to perform the 6500K and 7500K color temperature.
10. For auto-alignment, use Command Y80/Y81/Y82 to save 5700K/6500K/9300K
temperature.
5.2 Gray Level for YCBCR Component
Procedure:
(a). Gray Level:
1. Connect power, YCbCr Video into projector.
3. Light on projector
7. Adjust the Brightness and Contrast to let the black level to just distinguish, and the
light output of white level to just max.
(b). Saturation Level:
pattern : 100% blue
10. Adjust saturation and use the Lux meter to measure to let the light output just max.
37
5.3 Gray Level for Composite Video & S-Video
Equipment:
OSD Default value:
USER>Picture>
Brightness 30 Factory>SD
Contrast 17 Brightness 158
Color 23 Contrast 75
Tint 15 Saturation 91
Sharpness 3 Hue 0
Filter 3
Color Temp 2
Procedure:
(a) Gray Level
1. Connect power, Composite video or S-Video, into projector.
3. Light on projector
7. Adjust the Brightness and Contrast to let the black level to just distinguish, and the light
output of white level to just max.
(b). Saturation Level:
pattern : 100% blue
10. Adjust saturation and use lux meter to measure to let the light output just max.
6. Additional Patterns used for color final check
(a). Pattern 1: 0 ~ 14% gray, 2% change per step, (For DVI-A, YPBPR inputs)
Criteria: All gray bars should have the same color. Brightness change should be linear.
(b) Pattern 2: 16-gray (0 ~ 100%), For all input sources
Criteria: All gray bars should have the same color. Brightness change should be linear.
38
9. Trouble Shooting Guide
1. System trouble shooting :
Is LED light when Check door luck 1.Check +3Vs, +5Vs

n n
Main Power Switch switch 2. Check power
on?
Is Orange LED Are fans spinning? Check fans, wire and

n n
active when remote Translation board
power on?
y
Check DMD board
Is lamp turned on? Check ballast
n
Check lamp
Check DMD board

y y
Check DMD
Does starting OSD Does any stripe socket
n
shows normally? shows on screen?
n
Check Main board, DMD
y
board
Does DVI-I signal Check Connector
n
shows normally? board and FPC
board
Does Video signal n Check Main board ,

shows normally? FPC and Connector
board
39
2. Main board trouble shooting:
(1) Main:
1. See CPU trouble shooting

REMOTE U18, reset successful?
POWERON 2. U17, RP25, RP24 OK?
NO
3. CPU (U10) 56pin(IR) signal?
YES
OSD ok? 1. RP19,RP17,RP15,RP13

When no valid ok?
signal 2. U19, U20 OK?
NO 3. Check L8 with 100Mhz ok?
YES 4. check L9 with 40Mhz ok?
OSD ok.
When input PC
1.check J2
signal
NO
YES
1. RP1, RP2, RP3, RP4, R6
OSD ok.
R3, R2, R4 ok? (SIL504
When input
output)
Video signal NO
2. check J2
YES
1.Replace U6 (EEPROM)
Saving data in
2.check R36 R37(IIC pull high
EEPROM
NO resistors)
40
(2) SIL504 trouble shooting: (U4, U2)
X1, 20Mhz? 1. check X1, C41, C42

RESET 2. check U17,RP25
successful?
No
YES
System IIC ok? 1.Q2,Q3 ok? (level shift )

(U4 pin 15,14) 2. RP7 ok? ( IIC Pull high)
No
YES
SIL504 IIC ok? 1. R10,R11ok? ( IIC Pull

(U4 pin 2, 3) high)
No 2. Replace U4
YES
DEINTDONE 1. check SIL504 1.8V ok?

Signal ok? (U4 2. check U2, U3 ok?
pin21) No
41
(3) CPU (U10) trouble shooting guide :
Check +3Vs
(pin92)
YES
Check X1 NO 1. Check C75, C76

crystal 2. replace X1
YES
NO check U18, make sure U18
RESET
pin1 has delayed for certain
Successful?
period of time ,from L go H.
YES
1. Check U9(SRAM), check CPU_LCS_N (pin 58) and

CPU_BHE_N is active?
2. Check U12(Flash), check R68 and CPU_UCS_N (pin
57) is active?
42
3. DMD board trouble shooting guide.
RESETZ And NO 1. No RESETZ check main board and

POWERGOO translation board.
D? 2. No POWERGOOD check main board
YES
Color wheel NO 1. Check Color wheel and CW connector (J4)

Spinning? 2. CW power supply P12V of U13
YES
NO
Color wheel
1. Check CW sensor board and CW tag
Feedback (J3
2. Feedback 150Hz
pin3) ok?
YES
1. Check J1 pin 1 (lampon) , normal status is
Lamp light ok? NO
low
2. Check J1 pin 3(lamp light feedback) should
be low.
YES
Normal Image
DMD pixels always on
on screen ? Check DMD socket.
(32-Gray Pattern
in Factory mode
Horizontal dark/bright lines Check C-spring
is
Check DMD B/D : DAD1000(U1) VCC (5V), VBIAS
recommended)
(23 ~ 26V), VRST (-26V)
Vertical dark/bright lines

Check C-spring
Color missing
Check DMD socket.
43
4. Connector board trouble shooting guide.
S-video is OK? Check L14,L17

No
Check U5
Check U10
Composite is Check L13

No
OK? Check U5
Check U10
Component is Check L15,L16,L18

No
OK? Check U10
DVI- A is No Check L28,,L29,L31,L32,L33

OK? Check U17
DVI-D (HDCP)is Check U18 DDC

No
OK? Check U17
YPbPr is OK? Check L2,L3,L4

Check U2
Check U7
Check L2,L3,L4,L5,L6
BNC-PC is OK?
Check U2,U3,U4
No
No Check F1
J6 12V output?
Check Q2
Check L24
Check Q3
44
Check R61,R62
RS232 is OK?
Check U14
No Check main board
5. Power board trouble shooting guide.
Pow er B D C heck.
D is c o n n e c t th e w ir e
F u se B ro k e n ? No f o r m b u tto m b d . to
pow er bd.
Y es
P r o c e e d to " P r im a r y
C ir c u it C h e c k " .
S h o r t P in 1 2 & P in 9 .
C h e c k o u tp u t
v o lta g e s .( 1 ) + 3 .3 V ( 2 )
+ 1 2 V (3 )+ 5 V (4 )+ 5 V -
F ix ( 5 ) + 3 .3 V - F ix .
N o + 3 .3 V O u tp u t.
P r o c e e d to " N o + 3 .3 V -
C h e c k + 3 .3 V - F ix e x is ts ? No
F ix o u tp u t" .
Y es
C h e c k Q 7 0 2 ,Q 7 0 3 ,
F 7 0 4 B ro k e n ? No Q 7 0 4 w o r k s n o r m a lly ? No
a n d O n /O f f s ig n a l.
Y es Y es
R e p la c e n e w f u s e . C h e c k tr a c e .
45
N o + 1 2 V O u tp u t
P r o c e e d to " N o 1 2 V
C h e c k 1 2 V e x is ts ? N o
O u tp u t" .
Y e s
Q 7 0 3 d a m a g e s a n d
C h e c k Q 7 0 3 w o r k s
N o r e p la c e n e w
n o r m a lly ?( V c e < 0 .2 V )
tr a n s is to r .
Y e s
n o r m a lly ?( V c e > 1 0 V )
tr a n s is to r .
Y e s
C h e c k R 7 3 0 a n d
la y o u t tr a c e .
N o + 5 V o u tp u t.
P r o c e e d to " N o + 5 V -
C h e c k + 5 V - F ix e x is t ? N o
F ix o u tp u t" .
Y e s
n o r m a lly ?( V c e < 0 2 V )
tr a n s is to r .
Y e s
C h e c k Q 7 0 5 w o r k s R e p la c e n e w P -
N o
n o r m a lly ? M O S F E T .
Y e s
C h e c k th e tr a c e o f
+ 5 V .
46
N o 1 2 V o u tp u t
o r N o + 5 V -F ix
o u tp u t
C h e c k D 7 0 1 h a d b e e n
N o S o ld e r it a g a in .
in s e rte d p ro p e rly ?
Y e s
C h e c k IC 7 0 1 d a m a g e s ? Y e s R e p la c e n e w IC 7 0 1 .
N o
C h e c k D 7 0 2 h a d b e e n
N o S o ld e r it a g a in .
in s e rte d p ro p e rly ?
Y e s
P ro c e e d to " C h e c k
p rim a ry c irc u it" .
N o + 3 .3 V -F ix
O u tp u t
C h e c k IC 7 0 5 , IC 6 0 2 ,
R 7 1 8 , R 7 4 2 , R 6 1 7 ,
R 6 1 6 .
p rim a ry c irc u it" .
47
C h e c k p rim a r y
c ir c u it.
F u se B ro k e n ? No
IC 6 0 1 " .
Y es
P r o c e e d to " C h e c k
C heck Q 601 dam ages ? No C heck B D 651 dam ages ? No
IC 6 0 1 " .
Y es Y es
P in D & P in S o f Q 6 0 1
I n s id e d io d e s o f
a re s h o rte d . R e p la c e
B D 6 0 1 a re s h o rte d .
new
R e p la c e n e w b rid g e
R 6 1 2 ,Q 6 0 1 ,R 6 1 1 ,Z D
d io d e .
6 0 2 ,I C 6 0 1 a n d F u s e .
C h e c k IC 6 0 1 .
O p e n R 6 1 2 a n d in je c t
1 2 V to P in 7 o f
IC 6 0 1 .
I s th e P W M w a v e f o r m o f
No R e p la c e I C 6 0 1 .
P in 6 o f I C 6 0 1 is c o r r e c t ?
Y es
R e p la c e Z D 6 0 1 a n d
IC 6 0 3 .
48
10. Factory OSD Operation
There are 10 pages in this OSD, the ways to enter factory OSD are open user OSD, then
press power on button. If you have to return user OSD, open factory OSD and press power
on button again.
Go to \User OSD\Environment\lamp hours\minutes, then press Right, Left, Right, Left,
Enter in a row to switch to factory OSD.
1. Factory
This page is mostly for our factory to use.
Page Items Comment

Return User OSD Quit Factory OSD and return user OSD
Save Settings Save current settings of factory OSD to EEPROM
Load Saved Settings Load previous saved settings from EEPROM

Load Factory Default Load factory default
Restore all settings of user
Load All User Default
OSD and PC/HD timing parameters
Burn In Mode Burn-In mode On/Off
Factory
Burn In Timer Setup hours Set burn-in hours
Burn In Timer Running hours &

Running hours of burn-in mode
minutes
RS232 Baudrate Set baudrate of RS2329600 or 115200
OSD Timer OSD automatic off time

Usage Hour Record total usage hours of this projector
Software version Software version
49
2. HD Adj
This page is the settings of A/D converter. There are 2 sections, one is for RGBHV format
signal (DVI-A input and RGB-HD input), the other is for YPbPr format signal
(Comp-HD input).
Page Items Comment Range
Red Offset A/D converter red offset 0~127
Green Offset A/D converter green offset 0~127
Blue Offset A/D converter blue offset 0~127

RGBHV format
Red Gain A/D converter red gain 0~255
Green Gain A/D converter green gain 0~255
Blue Gain A/D converter blue gain 0~255
Brightness A/D converter green offset 0~127
Contrast A/D converter green gain 0~255
YPbPr format Saturation A/D converter red and blue gain 0~255
Pb-Offset A/D converter blue offset 0~127
Pr-Offset A/D converter red offset 0~127
3. STD Adj
This page is the settings of video decoder. There are 2 sections, one is for Video and
S-Video input, the other is for component input.
Brightness V/D brightness 0~255
Contrast V/D contrast -128~127

Video & S-Video
Saturation V/D saturation -128~127
Hue V/D hue -128~127
50
Brightness V/D brightness 0~255
Component Contrast V/D contrast -128~127
Saturation V/D saturation -128~127
4. Color Balance
For color temperature settings, they are the combination of gamma gain and gamma
offset. This page allows operator to adjust gamma correction to fit the expected color
temperature, and save these settings as one of the color temperature settings. And this
page also provides the function to restore color temperature setting to default gamma
combination.
Red Adjust the shape of RM-1A gamma curve 0~128
Gamma Green Adjust the shape of RM-1A gamma curve 0~128
Blue Adjust the shape of RM-1A gamma curve 0~128
Multiply gamma curve by a gain

Red 1~512
(gain= settings/512)

Gamma Gain Green 1~512

Blue 1~512
Red Add an offset value to gamma curve 0~90

Gamma
Green Add an offset value to gamma curve 0~90
Offset
Blue Add an offset value to gamma curve 0~90
51
Page Items Comment
Save gamma gain and gamm offset For data input (Component >= 480p
as color temp 9300K signal, DVI-A, and DVI-D)
Save Data Temp.
Restore default value of gamma
Restore combination
correction
Page Items Comment
Save gamma gain and gamm offset as For video input (Component < 480p
color temp 9300K signal, Video, and S-Video)
Save Video Temp.
Restore default value of gamma
Restore combination
correction
5. Filter Bypass
Page Items Comment

V-in On/Off status of RM-1A's video input filter
Filter Bypass V-out On/Off status of RM-1A's video output filter
G-in On/Off status of RM-1A's graphics input filter
52
6. DLP
This page allows user to change DLP settings.
Brightness DLP brightness -64~64
Contrast DLP contrast 0~100
DLP CW delay DLP color wheel delay 0~1023
Degamma
DLP degamma table 0~6
Table
7.Pattern1
This page allows user to call up DLP present curtains and RM-1A patterns.
Page Items Comment
Red Curtain DLP present curtain. For CW delay measurement
Green Curtain DLP present curtain. For CW delay measurement
Blue Curtain DLP present curtain. For CW delay measurement
Black Curtain DLP present curtain. For optical experiment.

Patterns 1
Color Bar RM-1A pattern. For checking gray scale.
Checker Board RM-1A pattern. For optical contrast measurement.
13-Points RM-1A pattern. For optical experiment.
Reflective Edge RM-1A pattern. For optical light leakage experiment
53
8.Pattern2
This page allows user to call up DLP DDP1010 series present patterns.
Page Items Comment
Solid Field - Yellow DLP DDP1010 present pattern. For checking color.
Solid Field - Cyan DLP DDP1010 present pattern. For checking color.
Solid Field - Magenta DLP DDP1010 present pattern. For checking color.
DLP DDP1010 present pattern. Monochrome pattern,

Horizontal Ramp
for checking gray scale.
DLP DDP1010 present pattern. Monochrome pattern,

Patterns 2 Vertical Ramp
for checking gray scale.
Horizontal Lines DLP DDP1010 present pattern. Monochrome pattern.
Diagonal Lines DLP DDP1010 present pattern. Monochrome pattern.
Vertical Lines DLP DDP1010 present pattern. Monochrome pattern.
Grid DLP DDP1010 present pattern. Monochrome pattern.
Checker Board DLP DDP1010 present pattern. Monochrome pattern.
9.Pattern3
This page allows user to call up DLP DDP1010 series present patterns, the major goal
of this page is for DMD inspection.
Page Items Comment
DLP DDP1010 present pattern. For inspection of 'major dark blemish' and
Patterns 3 Blue 90
'dark pixel' on DMD chip.
DLP DDP1010 present pattern. For inspection of 'border defects' on DMD

Gray 10
chip.
DLP DDP1010 present pattern. For inspection of 'major light blemish' and
Gray 6
light pixel' on DMD chip.
54
DLP DDP1010 present pattern. For inspection of 'minor blemishes' on
White Full
DMD chip.
DLP DDP1010 present pattern. For inspection of 'minor blemishes' on

Black Full
DMD chip.
DLP DDP1010 present pattern. For inspection of 'unstable pixel' on DMD

Red Ramp
chip.
10 . Test Mode
For different situation, we need different settings. Here we define 5 kinds of settings in
‘Picture Adjust’ page to fit some situations.
Page Items Comment
Optical Test High brightness, high contrast, high saturation
Middle Value All settings in the middle value
Test Mode Play DVD Optimal settings for watching DVD
Color Wheel Delay Low brightness, high contrast, high saturation
Blue Filter Only 'blue' is left, for 'color' and 'tint' adjustment
55
11. Firmware Upgrade Procedure
1. Connect specific download cable to RS232 (RJ-11) connector. Remember to turn the
AC switch off.
2. Execute the ‘Flash Loader’ program. If the ‘COM Settings’ item is ready, you can see
‘Identifying target…’ at the bottom of flash loader. If not, open ‘COM Settings’ item.
Choose the ‘COM Port’ you use, always set the baud rate 115200, then press ‘Connect’
and ‘OK’ button. The program returns to its main page, and ‘Connected’ and ‘Identifying
target’ are supposed to be displayed at the bottom of the flash loader.
56
3. Turn the AC switch on. In 3 seconds, ‘flash loader’ will identify the flash ROM of this
unit. Choose ‘Hex File Format’ as ‘Intel Extended’, ‘Operation’ as ‘Program’, and
‘Browse’ the ‘File Name’. After that, press the ‘Start’ button. ‘Flash Loader’ starts to
load program to Flash ROM.
4. After download procedure finished, remove download cable and turn the AC switch off.
Then the user can operate this machine in normal condition.
5. The hex file to be loaded, the format of its name is
BenQ_PE8700_RM1A_Ver102_20030619.hex
I. II. III. IV. V.
I. Brand name
II. Model name
III. Scaler type
IV. Version of SW
V. Released date
57
12. RS232 Codes
1. Set up peripherals
BenQ PE8700 provides an RJ-11 connector for RS232 serial communication control. The
user can use the ‘Hyper Terminal’ program of Microsoft Windows to control this unit.
To set the settings of serial port first is necessary. Choose which COM port you want
to connect, and set its settings as below:
Baud Rate: 115200 or 9600

Parity: None
Data bits: 8
Stop bits: 1
Flow Control: None
For baud rate setting, it depends on the settings in our \Factory OSD\FACTORY\RS232
BAUDRATE\ 9600 or 115200.
58
After settling down, connect our specific RS232 cable and press the ‘call’ icon of ‘Hyper
Terminal’ program. After this, press ‘Enter’ key, if an ‘>’ symbol come up, that means the unit
is ready to accept commands for computer.
2. Commands list
There are 3 kinds of serial commands, X-group, Y-group and Z-group.
For X-group, these functions are public. Any end-user can control the unit by these
commands, as long as they set correct RS232 communication. Following table is the codes
list of X-group command.
59
Code Function
X00 Must be Reversed , no function
X01 Power On
X02 Power Off
X03 Message On
X04 Message Off
X05 Lamp hours reset
X06 Load all user OSD default value
X07 Save current active source settings
X08 Change active OSD
X10 Menu
X11 Enter
X12 Exit
X13 Up(arrow key)
X14 Down(arrow key)
X15 Left(arrow key)
X16 Right(arrow key)
X20 Switch to Composite input
X21 Switch to S-Video input
X22 Switch to Component input
X23 Switch to Dsub_PC input
X24 Switch to YPbPr input
X25 Switch to BNC_PC input
X26 Switch to DVI input
X27 Switch to DVI_I input
X30 4:3 screen
X31 16:9 screen
X35 Aspect - Anamorphic

60
X36 Aspect - Standard (4:3)
X37 Aspect - Letter box
X38 Aspect - Virtual wide
X39 Aspect - Through
X40 Load memory 1 settings
X43 Load 'optical test' mode settings
X44 Load 'middle' mode settings
X45 Load 'CW delay adjustment' mode settings
X46 Load default of current source
X47 Save memory 1 settings
X50 Scale up
X51 Scale down
X55 Switch active source
X56 Picture in picture display
X57 Picture by picture display
X60 Switch language 1
X85 PC input - auto
61
X90 Image orientation - floor front
X91 Image orientation - ceiling front
X92 Image orientation - floor rear
X93 Image orientation - ceiling rear
X94 Back light board On
X95 Back light Board Off
X99 On line help

When an user sends a command, he must follow the command format in the list. After
he sends a command, program will acknowledge 2 pieces of information. This information,
we call it ‘ACK’ in the following content.
The format of first ACK is XnX
The length is 3, first and last characters are always be X. And the number ‘n’ is 0, 1 or
2. The explanation of n is
0: Right command format and function
1: Illegal format
2: Illegal function
So, if the user presses XA85, this one is wrong format, ACK will be X1X.
And if the user presses X98, because this function is not included in our command
table, ACK will be X2X.
For above situation, program sends the user an ACK, then waiting for a new
command.
If the user presses correct command, take an example, X35, first ACK, X0X will send
to the user. That tells the user it’s a right command. Then program starts to deal with this
command, and changes the aspect ratio to ‘anamorphic’ mode. When finish, the user will
receive 2nd ACK. The format is Xn_ccX
The length is 6. First and last characters are X, second character is the ACK, followed
by a ‘_’ character. ‘cc’ is the function number. So, in this case, the 2nd ACK is X0_35X. And
the user can continue to send next command.
For Y-group, this one is for our factory, not public. When our operators send
commands to the unit, the ACK format is identical as X-group, difference is only ‘Y’ instead
of ‘X’.
62
Following is the list of Y-group:
Code Function
Y01 Save current factory settings
Y02 Load saved factory settings
Y03 Load factory default
Y04 Load all user default
Y05 Burn-In mode on
Y06 Burn-In mode off
Y07 Set RS232 baudrate as 9600
Y08 Set RS232 baudrate as 115200
Y10 Save as data color temperature 1
Y20 Save as video color temperature 1
Y30 Restore data color temperature to default
Y31 Restore video color temperature to default
Y32 Restore white balance settings to default
Y40 DMD -- Degamma table 0
63
Y52 Red Curtain
Y53 Green Curtain
Y54 Blue Curtain
Y55 Black Curtain
Y57 Color Bar
Y58 Chess Board
Y59 Optical 13-point
Y60 Reflective Edge
Y61 Grid
Y62 Blue 90 Curtain
Y63 Gray 10 Curtain
Y64 Gray 6 Curtain
Y65 Full White Curtain
Y66 Full Black Curtain
Y67 Red Ramp Curtain
Y68 Gray 20 Curtain
Y70 Load 'optical test' mode settings
Y71 Load 'middle value' mode settings
Y72 Load 'Play DVD' mode settings
Y73 Load 'CW delay adjustment' mode settings
Y74 Load 'Blue filter' mode for color and tint adjustment
Y80 Load default for factory auto alignment procedure
Y81 Save corresponding settings after auto alignment
Y98 Display version
Y99 On line help
64
Example:
1. Command = Y89893 (Enter)
ACK = Y1Y (Illegal format, wrong length)
ACK = Y2Y (Illegal function)
1st ACK = Y0Y
2nd ACK = Y0_52Y
For Z-group, this one is for ‘auto-alignment’ procedure in our factory. This one allows
engineers to read or write the unit settings without OSD operation, it will save time to set
the value. Following is the table of Z-group.
Code Function
Z001 Brightness adjustment
Z002 Contrast adjustment
Z003 Color adjustment
Z004 Sharpness adjustment
Z005 Tint adjustment
Z006 Color temperature adjustment
Z007 Filters adjustment
Z008 Independent color control - Red adjustment
Z009 Independent color control - Green adjustment
Z010 Independent color control - Blue adjustment
Z011 Independent color control - Yellow adjustment
Z012 DMD white peaking adjustment
Z020 Frequency adjustment
Z021 Phase adjustment
Z022 H - Position adjustment
Z023 V - Position adjustment
65
Z030 Keystone adjustment
Z034 RGBHV input -- Red offset
Z035 RGBHV input -- Green offset
Z036 RGBHV input -- Blue offset
Z037 RGBHV input -- Red gain
Z038 RGBHV input -- Green gain
Z039 RGBHV input -- Blue gain
Z042 YPbPr input -- Brightness
Z043 YPbPr input -- Contrast
Z044 YPbPr input -- Saturation
Z045 YPbPr input -- Pb Offset
Z046 YPbPr input -- Pr Offset
Z050 CVBS & S-Video -- Brightness
Z051 CVBS & S-Video -- Contrast
Z052 CVBS & S-Video -- Saturation
Z053 CVBS & S-Video -- Hue
Z054 Component -- Brightness
Z055 Component -- Contrast
Z056 Component -- Saturation
Z060 Gamma--Index
Z061 Gamma--Red
Z062 Gamma--Green
Z063 Gamma--Blue
Z064 Gamma gain -- Red
Z065 Gamma gain -- Green
Z066 Gamma gain -- Blue
Z067 Gamma offset -- Red
Z068 Gamma offset -- Green
66
Z069 Gamma offset -- Blue
Z070 DMD -- Brightness
Z071 DMD -- Contrast
Z072 DMD -- Color Wheel Delay
Z073 DMD -- Degamma table
Z080 Burn-in hours
Z099 On line help
The length of the command must be 11. The format, take an example, to read DMD
color wheel delay:
Z072RxxxxxZ, where
Byte 1: must be 'Z' or 'z'

Byte 2~4: function code
Byte 5: action, must be ‘r’ or ‘R’
Byte 6~10: Don’t care
In contrast, if write DMD color wheel delay:
Z072W+0025Z, where

Byte 5: action, must be ‘w’ or ‘W’
Byte 6: sign byte, must be ‘-‘ or ‘+’
Byte 7~10: the value to be written
67
And the length of ACK must be 12, and format is
Z0_072+0025Z
Byte 1: Always ‘Z’

Byte 2: ACK
Byte 3: Always ‘_’
Byte 7: sign byte, ‘+’ or ‘-‘
Byte 8~11: the current value after writing
Byte 12: Always ‘Z’
And ‘ACK’ value is
0: Right command and function

1: Illegal Format
2: Illegal Function
3: Illegal Action,
4: Illegal Adjusted Situation,
5. Written value is over up limit,
6. Written value is over down limit
If the ACK is 0, 5, 6, program will deal this command. If ACK = 5, program writes the legal
maximum value to the setting. If ACK = 6, writes the legal minimum value to the setting.
68
5 4 3 2 1
TP2 TP4
TP1 TP3
E1 E1 E1 E1
120-Pin B2B Connectors RM1
1
D_ INA[0..23] 80 Pin Connector to DLP
D_INA[0..23] D_INA[0..23]
D D
D _VSYNC OP_A[0..23]
D_VSYNC D_VSYNC OP_A[0..23] OP_A[0..23] DMD_SCL
D_HS YNC DMD_SCL
D_HSYNC D_HSYNC OP _VSYNC DMD_SDA
DIN _CLK OP_VSYNC OP_HS YNC OP_VSYNC DMD_SDA
DIN_CLK DIN_CLK OP_HSYNC OP_HSYNC TP5
OP_ENABLE
DVI_SCDT OP_ENABLE OCLK_OUT OP_ENABLE
DVI_SCDT OCLK_OUT OCLK_OUT E1
OP_FIELD
OP_FIELD OP_FIELD
D LP
MEM_DQ[0..79]
1
MEM_DQ[0..79] MEM_A[0..11] MEM_DQ[0..79]
MEM_A[0..11] MEM_RAS_N MEM_A[0..11] POWER
Connector/POWER
MEM_RAS_N MEM_CAS_N MEM_RAS_N POWER
MEM_CAS_N MEM_BS MEM_CAS_N
MEM_BS MEM_CLK MEM_BS
MEM_CLK MEM_WE_N MEM_CLK LAMPLIT
MEM_WE_N MEM_WE_N LAMPLIT
BALLAST_CTRL
MEM_CS_N +3VA +5VA +12VA +3VS +5VS
MEM_CS_N MEM_CS_N
DLP_RESETZ
MEM_DQM_L
DLP_SPARE
SYNCVALID
MEM_DQM_L MEM_DQM_L
POWERON
MEM_DQM_U
MEM_DQM_U MEM_DQM_U +5VS
+3VS
+3VA +12VA
+5VA
+3VA
+3VA 7_100 Pin Connector to DLP/POWE
BALLAST_CTRL
POWERON
8_SDRAM 64MBit x 3 TP6
SYNCVA LID
DLP_SPARE
DLP_RESETZ
SDRAM 64MBit x 3 E1
SPAREO
SPAREI
Sil503_Deinterlacer
1
DI_IN[ 2..9]
DI_IN[2..9] DI_IN[2..9]
DI_27M_CLK
DI_27M_CLK DI_27M_CLK I/O KEYPAD&THERMAL_CONNECTOR
D I_VSYNC CPU_A1
DI_VSYNC DI_VSYNC CPU_A2 CPU_A1
SPAREI
SPAREO
DLP_SPARE
DI_H SYNC CPU_A3 CPU_A2 DLP_RESETZ
DI_HSYNC DI_HSYNC CPU_A4 CPU_A3 IR
CPU_A4 POWERON POWERON IR
C V _IN[0..15] MCURESET C
RESET_DVDO V_IN[0..15] V_IN[0..15] MCURESET KEY PAD[0..9]
V_ACTIVE TRIGGER KEYPAD[0..9] KEYPAD[0..9]
V_ACTIVE V_ACTIVE TRIGGER
DEINTDONE V_VSYNC SII141_PDO LAMP_PROTECT
V_VSYNC V_VSYNC SII141_PDO LAMP_PROTECT LAMP_PROTECT
POWER
V _HSYNC MUX_SEL
V_HSYNC V_HSYNC MUX_SEL
V_CLK DVI_SCDT S CL
VCLK VCLK DVI_SCDT SCL
S DA
RM1_RST_N SDA
RM1_RST_N RM1_RST_N
1
BACKLIGHT_CTRL
BACKLIGHT_CTRL
+3VA +1_8V E1 +3VS +5VS +12VA
RESET_DVDO
+3VS
DEINTDONE
DI_SDA TP11
+1_8V
CPU_PCS0_N
WRITE_PROT
DI_SCL +3VS
CPU_WR_N
RESETVCC
+3VA +3VS
FAN_CTRL
KEY_LED2
KEY_LED1
KEY_LED0
RESET_N
DLP_RST
DI _SCL
DI _SDA
2_Sil504_Deinterlacer +5VS
CPU_R D_N
CPU_RD_N
MCU503 Controller CPU_ D[0..7] +12VA
CPU_D[0..7]
6_I/O 10_KEYPAD&THERMAL_CONNECTOR
CPU_PCS0_N
DI_SCL
WRITE_PROT
FAN_CTRL
KEY_LED2
KEY_LED1
KEY_LED0
CPU _WR_N
TP16
DLP_RST
RESETVCC
BALLAST_CTRL
SYNCVA LID
RESET_N
DI_SDA E1 TP13
DEINTDONE
TP7
MCURESET E1
1
RESET_DVDO MCURESET
E1 CPU_FLASH_SRAM
DMD_SDA
CPU_PCS0_N
RESETVCC
WRITE_PROT
RESET_N
SYNCVALID
BALLAST_CTRL
FAN_CTRL
KEY_LED2
KEY_LED1
KEY_LED0
DLP_RST
CPU_WR_N
1
SII141_PDO DMD_SDA
SII141_PDO DMD_SCL CPU_R D_N
TRIGGER DMD_SCL CPU_RD_N CPU_RD_N
B TRIGGER CPU_ D[0..7] B
RM1_RST_N CPU_D[0..7] CPU_D[0..7]
RM1_RST_N C PU_A[0..7]
MUX_SEL +1_8V CPU_A[0..7] CPU_A[0..7]
MUX_SEL +3VA +5VA +3VA RM1_WR_N LAMPLIT
DVI_ACTDATA
S CL RM1_WR_N RM1_WR_N LAMPLIT

SPAREI SCL RM1CLKIN
SPAREI TP20 TP19 TP18 TP17 RM1CLKIN RM1CLKIN
S DA
SPAREO E1 E1 E1 E1 SDA RM1_CS_N POWER
SPAREO +5VA +3VA RM1_CS_N RM1_CS_N POWER
+1_8V RM1_IRQ
+3VA RM1_IRQ RM1_IRQ
1
3_MCU503 Controller 4_RM1

DMD_SCL
S CL DMD_SDA
SCL SCL
+5VS +1_8V +12VA +5VA +3VA SDA
CPU_RXD0
S DA
CPU_RXD0
SDA
CPU_RXD0
CPU
CPU_TXD0
+3VA CPU_TXD0 CPU_TXD0
MUX_SEL_P
+5VA MUX_SEL_P MUX_SEL_P
MUX_BUFFER
+12VA MUX_BUFFER MUX_BUFFER +12VA +5VS +3VS
DVI_ACTDATA +5VA +3VA
+1_8V DVI_ACTDATA
BACKLIGHT_CTRL
+5VS BACKLIGHT_CTRL +12VA
MUX_SEL_Q +5VA
MUX_SEL_Q MUX_SEL_Q +5VS
IR +3VA
IR IR +3VS
1
1_120Pin B2B Connectors
A 5_CPU_FLASH_SRAM A
TP8 TP9 TP15
E1 E1 E1
Benq Corporation
Project Code Model Name OEM/ODM Model Name
99.J5877.001 HT720G NA
Title
MAIN BOARD
Size PCB P/N P CB Rev. Document Number Rev.
<Size> 48.J5801.S02 99.J5877.R22-C3-304-001 0
S02
Date: Thursday, January 16, 2003 Sheet 1 of 10

Prepared By Reviewed By Approved By
ANGEL HU COLIN CHANG BEN CHEN
5 4 3 2 1
5 4 3 2 1
+5VS
+5VS
C1
0.1UF
+12VA
J5
J1 SDA
+12VA SDA 1 1
1 2 2
SCL 3
2 SCL 3
3 KEY_LED0 4 4
4 KEY_LED1 FAN_CTRL 5 5
5 KEY_LED2 DLP_RST 6 6
6 IR POWERON 7 7
7 8 8
8 DLP_RESETZ 9 9
C BACK_LIGHT_CTRL 10
9 LAMP_PROTECT 10
10 11 11
KEYPAD0 12
11 KEYPAD1 +3VS 12
12 KEYPAD2
13 KEYPAD3
14 +3VS CON_12P
KEYPAD4
15 KEYPAD5
16 KEYPAD6
17 KEYPAD7
18 KEYPAD8
19 KEYPAD[0..9]
KEYPAD9
20
CON20
THERMAL CONNECTOR
B
KEYPAD CONNECTOR
+3VS
U8D
Benq Corporation
14
74HC132 Project Code Model Name OEM/ODM Model Name
BACKLIGHT_CTRL 12 99.J5877.001 HT720G NA

11 BACK_LIGHT_CTRL
13 Title
A
MAIN BOARD
7
Size PCB P/N PCB Rev. Document Number R ev.

<Size> 48.J5801.S02 99.J5877.R22-C3-304-001 0
S02

5 4 3 2 1
D D
DI_IN[2..9]
Screw Holes
D_INA[0..23]
RED -- D_INA[23..16]
GREEN -- D_INA[15..8]
BLUE -- D_INA[7..0]
1
5 9 5 9 5 9 5 9
J2
4 8 4 8 4 8 4 8
61 61 1 1 DVI_SCDT
TRIGGER 62 62 2 2 3 7 3 7 3 7 3 7
63 63 3 3
MUX_SEL_P 64 64 4 4 2 6 2 6 2 6 2 6
65 65 5 5 IR
CPU_RXD0 66 66 6 6 H1 H2 H3 H4
67 67 7 7
68 8 +5VS
CPU_TXD0 68 8 HOLE-V8 HOLE-V8 HOLE-V8 HOLE-V8
69 69 9 9 MUX_SEL
MUX_BUFFER 70 70 10 10
71 71 11 11 +5VS
D_HS YNC 72 72 12 12
73 73 13 13 D_VSYNC
DIN_CLK 74 74 14 14
75 15 D_INA23
D_INA21 75 15 D_INA22
76 76 16 16
D_INA20 77 17
77 17 D_INA19
C 78 78 18 18 C
D_INA17 79 19 D_INA18
D_INA16 79 19
80 80 20 20
81 21 D_INA15
D_INA13 81 21 D_INA14
82 82 22 22
D_INA12 83 23
83 23 D_INA11
84 84 24 24
D_ INA9 85 25 D_INA10
D_ INA8 85 25
86 86 26 26
87 27 D_ INA7
D_ INA5 87 27 D_ INA6
88 88 28 28
D_ INA4 89 29
89 29 D_ INA3
90 90 30 30
D_ INA1 91 31 D_ INA2
D_ INA0 91 31
92 92 32 32
93 93 33 33 SII141_PDO
94 94 34 34 SPARE for DVI interface
95 95 35 35 DVI_ACTDATA
SCL 96 96 36 36
97 97 37 37 SDA
DI_I N8 98 38
98 38 DI_I N9
99 99 39 39
DI_I N6 100 40
100 40 DI_I N7
101 101 41 41
DI_I N4 102 42
102 42 DI_I N5
103 103 43 43
DI_I N2 104 44
104 44 DI_I N3
105 105 45 45
RM1_RST_N 106 106 46 46
107 107 47 47 DI_VSYNC
DI_H SYNC 108 108 48 48
109 109 49 49 SPAREI Optical Points
DI_27M_CLK 110 110 50 50
111 111 51 51 MUX_SEL_Q
112 52 OP1 OP2 OP3 OP4 OP5 OP6 OP7
SPAREO 112 52
113 53 OP OP OP OP OP OP OP
113 53
114 114 54 54
115 115 55 55
116 56 +12VA
116 56
117 117 57 57 +12VA
118 118 58 58
B +5VA 119 59 OP8 OP9 OP10 OP11 OP12 OP13 OP14 B
119 59 OP OP OP OP OP OP OP
+5VA 120 120 60 60
C2
0.1UF
AMP 120P D0.8
C3
10UF/16 + C4
0.1UF
OP15 OP16 OP17 OP18
OP OP OP OP
U1
+3VA LM8117A-1.8(SOT223) L1 +1_8V
3 2 +1.8VOUT 1 2
+3VA VIN VOUT 1 2 +1_8V
FCB3216K
GND
C6 + C5
22UF/16 C7
1
0.1UF 0.1UF
A A
Benq Corporation
99.J5877.001 HT720G NA
Title
MAIN BOARD
<Size> 48.J5801.S02 99.J5877.R22-C3-304-001 0
S02

5 4 3 2 1
5 4 3 2 1
V _IN[0..15]
V_IN[0..15]
D I_VSYNC
DI_VSYNC
DI_H SYNC
DI_ HSYNC
TP21
E1
DEINTDONE
DEINTDONE
AVSSI
D R1
D
CLK54_72M1
10K TP22
INTERLACE_DETECT TP23
1
2:2_DETECT TP24
1
VDD_PLL 3:2_DETECT 1
VDD_CORE E1
E1
RESET_DVDO E1
RESET_DVDO
+3VA
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
TEST1
TEST0
/RESET
/DETVIDEO
HOSTDATA7 / VS
AVDD_1.8
AVSS_1.8
SCKOUT
SDOUT
MEMADDR12
DEINTDONE_N
/DET22PD
/DET32PD
HOSTDATA0
HOSTDATA1
HOSTDATA2
HOSTDATA3
HOSTDATA4
HOSTDATA5
HOSTDATA6 / HS
HOSTDATA8 / VIDLNDATA12
HOSTMODE
GND
VDDCORE_1.8
CLK54_72M
/BYPPLLCLK54_72M
VDDCORE_1.8
GND
SCKLN
SDLN
VDD
GND
VDD
GND
VDD
RSVD
VDDCORE_1.8
GND
GND
HOSTCLK
VDDCORE_1.8
HOSTADDR7
HOSTADDR6
WSOUT
WSLN
TP27
E1
TP25 TP26
E1 E1
1 156
1
1
NC HOSTADDR5
2 VDDCORE_1.8 HOSTADDR4 155
3 GND HOSTADDR3 154
TP28 4 153 Note: The Sil 503 does not support a standard
R2 33 E1 503CBLANK LCDPWREN HOSTADDR2
V_ACTIVE 5 152
1V _CSYNC 6
/CBLANK HOSTADDR1
151 I2C protocol. See data sheet page 22.
R3 33 503VSYNC /CSYNC HOSTADDR0
V_VSYNC 7 /VSYNC GND 150
503HSYNC 8 149
V _HSYNC /HSYNC /HOSTCS
R4 33 9 148 DI _SDA
BLUE_CB0 /HOSTRD_SDA DI_SDA
10 147 DI _SCL
BLUE_CB1 /HOSTWR_SCL DI_SCL
V_IN0 2 1 C B0 11 146
V_IN1 C B1 BLUE_CB2 VDDCORE_1.8 DI_27M_CLK
V_IN2
4
6
3
5 C B2
12
13
BLUE_CB3 VIDLNCLK 145
144 DI_IN[ 2..9] DI_27M_CLK Input Port
BLUE_CB4 GND DI_IN[2..9]
V_IN3 8 7 C B3 14 143 DI_I N9
BLUE_CB5 VIDLNDATA9 DI_I N8
15 GND VIDLNDATA8 142
RP1 47_RP 16 141 DI_I N7
V_IN4 C B4 VDD VIDLNDATA7 DI_I N6
2 1 17 BLUE_CB6 VIDLNDATA6 140
V_IN5 4 3 C B5 18 139 DI_I N5
V_IN6 C B6 BLUE_CB7 VIDLNDATA5 DI_I N4
6 5 19 BLUE_CB8 VIDLNDATA4 138
V_IN7 8 7 C B7 20 137 DI_I N3
BLUE_CB9 U2 VIDLNDATA3 DI_I N2
21 GND VIDLNDATA2 136
RP2 47_RP 22 SII504 135
C V_IN8
V_IN9
2 1 GRE EN_Y2
GRE EN_Y3
23
24
GREEN_Y0
GREEN_Y1
GREEN_Y2
VDD
RSVD
RSVD
134
133 DI _RSVD1 R5 10K C
4 3 25 GREEN_Y3 VDD 132
V_IN10 6 5 26 131
V_IN11 GRE EN_Y4 VDD GND DQ16
8 7 27 GREEN_Y4 MEMDATA16 130
RP3 47_RP GRE EN_Y5 28 129 DQ17
V_IN12 GRE EN_Y6 GREEN_Y5 MEMDATA17 DQ18
2 1 29 GREEN_Y6 MEMDATA18 128
V_IN13 4 3 GRE EN_Y7 30 127 DQ19
V_IN14 GRE EN_Y8 GREEN_Y7 MEMDATA19
6 5 31 GREEN_Y8 GND 126
V_IN15 8 7 GRE EN_Y9 32 125 DQ20
GREEN_Y9 MEMDATA20 DQ21
33 GND MEMDATA21 124
RP4 47_RP 34 123 DQ22
RED_CR0 MEMDATA22 DQ23
35 RED_CR1 MENDATA23 122
36 RED_CR2 GND 121
37 120 DQ31
RED_CR3 MEMDATA31 DQ30
38 RED_CR4 MEMDATA30 119
39 RED_CR5 GND 118
40 GND VDD 117
41 116 DQ29
VDDCORE_1.8 MEMDATA29 DQ28
TP29 43 114
E1 RED_CR7 GND DQ27
45 112 DQ25
1
VCLK R6 33 VIDOUTCLK RED_CR9 MEMDATA26 DQ26

VCLK 46 VIDOUTCLK MEMDATA25 111
47 110 DQ24
GND MEMDATA24 DQ15
48 /BYPPLLCLK48M MEMDATA15 109
49 CLK48M /BYPPLLMEMCLK 108
50 GND GND 107
EXTREFCLKXTALIN
51 VDDCORE_1.8 VDDCORE_1.8 106

ExtRefClkXtalOut
52 105
EXTREFSEL
ExtRefSel_N NC
VDDCORE_1.8
VDDCORE_1.8
MEMADDR10
MEMADDR11
MEMDATA10
MEMDATA11
MEMDATA12
MEMDATA13
MEMDATA14
MEMADDR3
MEMADDR2
MEMADDR1
MEMADDR0
MEMADDR4
MEMADDR5
MEMADDR6
MEMADDR7
MEMADDR8
MEMADDR9
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
MEMDATA8
MEMDATA9
MEMCLK
PUPDIS
RSVD
RSVD
Note: For compatability with Sil504
/RAS
/CAS
DQM
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDD
VDD
/WE
R99
NC
place bypass resistors
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
NC_R0603
B M_CLK
D Q[0..31] B
+3VA +3V_MEM
DQ14
R98 4.7K DQ13
RA SN
CA SN
W EN
DQM
DQ12 U3
A10
A11
DQ10
A3
A1
A0
A4
A5
A6
A7
A8
A9
D Q7
D Q6
D Q5
D Q4
D Q3
D Q2
D Q1
D Q0
D Q8
D Q9
DQ11 1 86
L2 D Q0 VDD VSS DQ15
2 85
A2
VDD_CORE Z1000/100MHZ VDD_PLL DQ0 DQ15

3 VDDQ VSSQ 84
PLL Power D Q1 4 83 DQ14
D Q2 DQ1 DQ14 DQ13
5 DQ2 DQ13 82
6 VSSQ VDDQ 81
C8 + C9 C10
D Q3
D Q4
7
8
DQ3 DQ12 80
79
DQ12
DQ11
0.1UF 10UF/16 0.1UF DQ4 DQ11
9 VDDQ VSSQ 78
AVSSI D Q5 10 77 DQ10
D Q6 DQ5 DQ10 D Q9
11 DQ6 DQ9 76
12 VSSQ VDDQ 75
D Q[0..31] D Q7 13 74 D Q8
DQ7 DQ8
14 NC NC 73
+3VA 15 72
DQM VDD VSS DQM Note: Connect RP4, RP5 and R256 to bypass Sil503
+3VA 16 DQM0 DQM1 71
W EN 17 70 V_IN8 1 2 DI_I N2
CA SN WE NC RP5 V_IN9 DI_I N3
18 CAS NC 69 3 4
+ C11 C12 C13 C14 C15 C16
RA SN 19
20
RAS CLK 68
67
M_CLK NC_RP V_IN10
V_IN11
5
7
6
8
DI_I N4
DI_I N5
10UF/16 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF CS CKE A9 V_IN12 DI_I N6
21 NC A9 66 1 2
A11 22 65 A8 RP6 V_IN13 3 4 DI_I N7
A12 BA0 A8 A7 NC_RP V_IN14 DI_I N8
23 BA1 A7 64 5 6
A10 24 63 A6 V_IN15 7 8 DI_I N9
A0 A10/AP A6 A5
25 A0 A5 62
A1 26 61 A4 VCLK R7 NC_R0603 DI_27M_CLK
VDD_CORE A2 A1 A4 A3
27 A2 A3 60
28 DQM2 DQM3 59
29 VDD VSS 58
30 NC NC 57
A[0..11] A[0..11] DQ16 31 56 DQ31
C17 C18 C19 C20 C21 C22 DQ16 DQ31
32 VSSQ VDDQ 55
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF DQ17 33 54 DQ30
DQ18 DQ17 DQ30 DQ29
34 DQ18 DQ29 53
A L5
DQ19
DQ20
35
36
37
VDDQ
DQ19
DQ20
VSSQ
DQ28
DQ27
52
51
50
DQ28
DQ27
A
+1_8V L3 Z1000/100MHZ Z1000/100MHZ +3V_MEM
Benq Corporation
38 VSSQ VDDQ 49
DQ21 39 48 DQ26
+3VA DQ22 DQ21 DQ26 DQ25
40 DQ22 DQ25 47
41 VDDQ VSSQ 46 Project Code Model Name OEM/ODM Model Name
C23 C24 C25 C26 C27 C28 C29 C34 + C35 C36 C37 C38 C39
DQ23 42
43
DQ23 DQ24 45
44
DQ24
99.J5877.001 HT720G NA
4.7UF/16 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF/16 0.1UF 0.1UF 0.1UF 0.1UF VDD VSS
+1_8V Title
K4S643232C-TC/L10
MAIN BOARD

<Size> 48.J5801.S02 99.J5877.R22-C3-304-001 0
S02

5 4 3 2 1
D D
RESET_DVDO
R120 0
(open)
DMD_SDA
R121 0
(open)
DMD_SCL
+3VA
+3VA 3
D
1
Q1
1 2
G S
2 3 +5VA
MCURESET
+5VA BSN20
BSN20
1
C Q2 +5VA C
SDA 2 3
BSN20
1
1
3
5
7
Q3 R8 R9
RP7
2 3 +5VA 470 470
SCL
LED1_EN
LED2_EN
4.7K_RP
BSN20
2
4
6
8
C40
0.1UF R10 R11
U4
1
2.2K 2.2K D1 D2
LED_1206 LED_1206
RESET_DVDO 1 20
DVRESET VDD
DEINTDONE SDA_5V DI_ SDA
15 SDA DVSDA 2 DI_SDA
SCL_5V 14 3 DI_ SCL
2
+5VA SCL DVSCL DI_SCL
DEI NTDONE 21 23 LED0
VSYNC PRMODE0 LED1
PRMODE1 24
2 1 MCEN 6
MCADDRSEL ENABLE
4 3 7 SA GPIO0 22
6 5 FILM
SUBT
5 FILMBIAS GPIO1 27 LED2 LED3 SOURCE
8 7 4 SUBTITLE
B B
RP8 4.7K_RP GAME
EXTGAME
11 GMODE ON ON 3:2
2 1 12 EXTGMD RX 18
4 3 CLKSPEED 13 MCKSEL TX 17 ON OFF 2:2
6 5 25 SQMODE
8
RP9
7
4.7K_RP
Y PBPR 26 YPRPB RSVD0 16 OFF ON VID
28 WAVE
P ICXIN
OFF OFF GAME
9 OSC1 Vss 19
PICXOUT 10 8
OSC2 Vss
R13 10M MCU503

2
X1 20MHZ
3 1
4
C41 C42
22PF 22PF
A
Benq Corporation A
99.J5877.001 HT720G NA
Title
MAIN BOARD
Size PCB P/N PCB Rev. Document Number Rev.

<Size> 48.J5801.S02 99.J5877.R22-C3-304-001 0
S02

5 4 3 2 1
5 4 3 2 1
MEM_DQ[0..79]
MEM_DQ[0..79]
RED -- D_INA[23..16]
D
GREEN -- D_INA[15..8] Place the resistors as close to the RM1 D
BLUE -- D_INA[7..0] pins as possible.

D_ INA[0..23]
D_INA[0..23]
CPU_ D[0..7]
CPU_D[0..7]
+3VA LEFT EDGE BOTTOM EDGE RIGHT EDGE +3VA
+3VA +3VA +1_8V TOP EDGE
U5A U5B U5C +1_8V
VDP01 +1_8V VDP01 VDP01 +3VA U5D
+1_8V VDP01
A1 AF1 B26 R14
D_INA12 GND CP U_D0 CP U_D1 GND GND MEM_DQ22 120
B1 D_INA12 AF2 DB1 MEM_DQ22 C25 A2 GND
B2 AE2 C26 MEM_DQ24 D_INA11
A3
D_INA14 GND CP U_D3 GND MEM_DQ24 MEM_DQ23 D_ INA9 D_INA11
C1 D_INA14 AF3 DB3 MEM_DQ23 D24 TP30 TP31 B3 D_INA9
D_INA13 C2 CP U_D2 AE3 D25 R15 D_ INA7
A4
D_INA22 D_INA13 DB2 VDD33 MEM_DQ20 180 D_ INA5 D_INA7
C3 GND AD3 GND MEM_DQ20 D26 E1 E1 B4 D_INA5
D_INA17 D1 CP U_D6 AF4 E23 D_INA10
C4
D_INA15 D_INA17 CP U_D4 DB6 GND MEM_DQ21 D_ INA3 D_INA10
D2 D_INA15 AE4 DB4 MEM_DQ21 E24 A5 D_INA3
D_INA16 D3 CP U_D5 AD4 E25 D_ INA2
B5
1
D_INA23 D_INA16 CP U_D7 DB5 VDD18 D_ INA8 D_INA2
D4 GND AC4 GND GND E26 C5 D_INA8
D_INA21 E1 33 R16 RM1_OP_ENABLE AF5 F23 D_ INA6
D5
D_INA21 OP_ENABLE OP_ENABLE VDD33 D_INA6
D_INA18 E2 AE5 F24 D_ INA0
A6
D_INA20 D_INA18 33 R17 R M1_OP_HSYNC DB7 GND MEM_DQ19 OVERFLOW2 D_INA0
E3 D_INA20 OP_HSYNC AD5 OP_HSYNC MEM_DQ19 F25 B6 DINA_OVERFLOW2
D_INA19 E4 33 R18 RM1_OP_VSYNC AC5 F26 C6
D_INA19 OP_VSYNC OP_VSYNC TEST D_INA4
F1 AF6 G23 D_ INA4 D6
D_INB1 OP_FIELD VDD18 GND RM1CLKIN WIRE_TP31 VDD33
F2 D_INA22 OP_FIELD AE6 OP_FIELD MPLL_CLK_IN G24 RM1CLKIN A7 DINA_OVERFLOW0
F3 RM1CLKIN AD6 G25 MEM_DQ16 B7
D_INB0 RM1CLKIN OPLL_CLK_IN MEM_DQ16 MEM_DQ17 MEM_A11 R19 33 D_ INA1 D_FIELD
F4 VDD50 AC6 VDD33 MEM_DQ17 G26 C7 D_INA1
G1 D_INB3 +3VA
R20 NC_R0603 AF7 GND VDD18 H23
MEM_DQ18
TP32
E1
1
TP33
RM1_D_FIELD
RM1_D_VALID
D7 GND RM1_GP0 , RM1_GP1
G2 AE7 H24 1 A8
G3
D_INB2
D_INB4 AD7
GND
VDD33
MEM_DQ18
MEM_DQ13 H25 MEM_DQ13
DIN_CLK
E1 B8
D_VALID
DIN_CLK
Input Only or Output Only
G4 AC7 H26 MEM_DQ14 WIRE_TP30 C8
D_INA23 RM1_RST_N OP_FIELD_3D MEM_DQ14 DINA_OVERFLOW1
H1 D_INB6 RM1_RST_N AF8 RST_N GND J23 D8 VDD18
H2 AE8 J24 MEM_DQ15 A9
D_INB5 GND MEM_DQ15 D _VSYNC D_VSYNC
H3 AD8 J25 MEM_DQ10 TP34 1 RM1_DPLL_CLK B9
D_INB7 RM1_IRQ IRQ MEM_DQ10 DPLL_CLK
H4 RM1_OCLK_OUT AC8 J26 MEM_DQ12 E1 C9
GND GND MEM_DQ12 DVI_ACTDATA D_ACTIVE
J1 OUT_A23 AF9 K23 MEM_DQ9 D9
D_INB9 OP_A23 MEM_DQ9 MEM_DQ11 TP49 CLAMP_TESTPIN GND
J2 D_INB8 AE9 OCLK_OUT MEM_DQ11 K24 1 A10 CLAMP
C J3 OP_A23 3 4 OUT_A21 AD9 K25 MEM_DQ6 E1 B10 C
D_INB11 OP_A21 OP_A21 MEM_DQ6 MEM_DQ8 ADC_CLK
J4 VDD18 7 8 AC9 VDD18 MEM_DQ8 K26 D_HS YNC C10 D_HSYNC
K1 OP_A20 5 6 OUT_A20 AF10 L23 ADC_SYNC _INV D10
D_INB12 OP_A20 VDD33 ADC_SYNC_INV
1
K2 OP_A22 1 2 OUT_A22 AE10 L24 MEM_DQ7 0 R23 RM1_MCLK_IN A11
D_INB10 RP10 47_RP OUT_A18 OP_A22 MEM_DQ7 MEM_DQ2 TP35 RM1_MCLK_OUTB MCLK_IN
K3 D_INB14 AD10 OP_A18 MEM_DQ2 L25 B11 MCLK_OUTB
K4 OP_A18 1 2 AC10 L26 MEM_DQ4 E1 TP36 1 RM1_ADC_CLKB C11
GND OP_A17 OUT_A17 GND MEM_DQ4 MEM_DQ5 E1 ADC_CLKB
L1 D_INB15 3 4 AF11 OP_A17 MEM_DQ5 M23 D11 VDD33
L2 OP_A19 5 6 OUT_A19 AE11 M24 MEM_DQ3 33 R24 RM1_MEM_RAS_N A12
D_INB13 OP_A19 MEM_DQ3 MEM_RAS_N MEM_RAS_N
L3 OP_A14 7 8 OUT_A14 AD11 M25 MEM_DQ79 RM1_MCLK_OUT B12
D_INB18 RP11 47_RP OP_A14 MEM_DQ79 MEM_DQ1 DPLL_COAST MCLK_OUT
L4 VDD50 AC11 VDD33 MEM_DQ1 M26 1 C12 DPLL_COAST
M1 OP_A15 3 4 OUT_A15 AF12 N23 MEM_DQ76 TP50 E1 NC_R0603 R26 RM1_DPLL_DIV D12
D_INB17 OP_A16 OUT_A16 OP_A15 MEM_DQ76 MEM_DQ0 +3VA1 RM1_MEM_WE_N DPLL_DIV
M2 D_INB16 1 2 AE12 OP_A16 MEM_DQ0 N24 MEM_WE_N 2 A13 MEM_WE_N
M3 OP_A10 7 8 OUT_A10 AD12 N25 MEM_DQ75 3 4 RM1_MEM_DQM_U B13
D_INB21 OP_A10 MEM_DQ75 MEM_DQM_U MEM_DQM_U
M4 OP_A12 5 6 OUT_A12 AC12 N26 MEM_DQ77 5 6 RM1_MEM_CS_N C13
VDD33 OP_A12 MEM_DQ77 MEM_CS_N MEM_CS_N
N1 OP_A11 RP12
3 4 47_RP OUT_A11 AF13 P23 7 8 RM1_MEM_DQM_L D13
D_INB20 OP_A11 GND MEM_DQM_L MEM_DQM_L
N2 OP_A13 1 2 OUT_A13 AE13 P24 MEM_DQ78 MEM_A1 1 2 RM1_MEM_A1 A14
D_INB19 OP_A6 OUT_A6 OP_A13 MEM_DQ78 MEM_DQ71 MEM_A3 RM1_MEM_A3 MEM_A1
N3 V_IN1 5 6 AD13 OP_A6 MEM_DQ71 P25 3 4 B14 MEM_A3
V_IN1 N4 OP_A7 7 8 AC13 P26 MEM_DQ73 5 6 RM1_MEM_CAS_N C14
GND GND MEM_DQ73 MEM_CAS_N MEM_CAS_N
V_IN0 P1 RP14 47_RP OUT_A7 AF14 R23 MEM_DQ72 7 8 D14
V_IN0 OP_A9 OUT_A9 OP_A7 MEM_DQ72 MEM_DQ74 MEM_A5 RM1_MEM_A5 GND
P2 D_INB22 1 2 AE14 OP_A9 MEM_DQ74 R24 A15 MEM_A5
V_IN3 P3 OP_A4 5 6 OUT_A4 AD14 R25 MEM_DQ68 MEM_A6 1 2 RM1_MEM_A6 B15
V_IN3 OP_A8 OUT_A8 OP_A4 MEM_DQ68 MEM_DQ69 MEM_A0 RM1_MEM_A0 MEM_A6
P4 D_INB23 3 4 AC14 OP_A8 MEM_DQ69 R26 3 4 C15 MEM_A0
V_IN4 R1 OP_A3 7 8 OUT_A3 AF15 T23 MEM_A2 5 6 RM1_MEM_A2 D15
V_IN2 V_IN4 RP16 47_RP OUT_A5 OP_A3 VDD33 MEM_DQ70 MEM_A7 RM1_MEM_A7 MEM_A2
R2 V_IN2 AE15 OP_A5 MEM_DQ70 T24 7 8 A16 MEM_A7
V_IN6 R3 OP_A5 1 2 OUT_A1 AD15 T25 MEM_DQ65 MEM_A9 1 2 RM1_MEM_A9 B16
V_IN8 V_IN6 OP_A1 OP_A1 MEM_DQ65 MEM_DQ67 MEM_A4 RM1_MEM_A4 MEM_A9
R4 V_IN8 5 6 AC15 OP_B23 MEM_DQ67 T26 3 4 C16 MEM_A4
V _IN[0..15] V_IN7 T1 OP_A0 7 8 OUT_A0 AF16 U23 MEM_A10 5 6 RM1_MEM_A10 D16
V_IN[0..15] V_IN7 OP_A0 GND VDD33
V_IN5 T2 OP_A2 3 4 OUT_A2 AE16 U24 MEM_DQ66 MEM_A8 7 8 A17
V_IN5 OP_A2 MEM_DQ66 MEM_A10
YUV422 +3VA
V_IN10 T3 V_IN10
RP18 47_RP AD16 OP_B21 MEM_DQ62 U25 MEM_DQ62
MEM_DQ64 RP13 33_RP RM1_MEM_A8
B17 MEM_DQ47
T4 AC16 U26 C17
Y -- V_IN[15..8] V_IN11 U1
VDD50
V_IN11 AF17
VDD33
OP_B20
MEM_DQ64
VDD18 V23 RP15 33_RP MEM_DQ47 D17
MEM_A8
GND
MEM_A[0..11]
UV -- V_IN[7..0] V_IN9
V_IN13
U2
U3
V_IN9 AE17
AD17
OP_B22 MEM_DQ63 V24
V25
MEM_DQ63
MEM_DQ60
RP17 33_RP
RP19 33_RP
MEM_DQ46
MEM_DQ45
A18
B18
MEM_DQ46
R27 R28 V_IN14 V_IN13 OP_B17 MEM_DQ60 MEM_DQ61 RM1_MEM_BS C18 MEM_DQ45
U4 VDD33 AC17 OP_B19 MEM_DQ61 V26 MEM_BS
1K 1K V_IN12 V1 AF18 W23 D18
V_IN15 V_IN14 OP_A[0..23] OP_B16 GND MEM_DQ59 MEM_DQ43 VDD18
V2 V_IN12 AE18 OP_B18 MEM_DQ59 W24 A19 MEM_DQ43
V_VALID V3 V_VALID RED -- OP_A[23..16] AD18 OP_B13 MEM_DQ57 W25 MEM_DQ57
MEM_DQ58
MEM_DQ42
MEM_DQ44
B19 MEM_DQ42
V4 AC18 W26 C19
VCLK
VCLK W1
GND
VCLK
GREEN -- OP_A[15..8] AF19
GND
OP_B14
MEM_DQ58
MEM_DQ51 Y23 MEM_DQ51 D19
MEM_DQ44
GND
V _HSYNC
W2
W3
V_IN15 BLUE -- OP_A[7..0] AE19
AD19
OP_B15 MEM_DQ56 Y24
Y25
MEM_DQ56
MEM_DQ54
MEM_DQ40
MEM_DQ39
A20
B20
MEM_DQ40
V _HSYNC V_HSYNC OP_B10 MEM_DQ54 MEM_DQ39
B W4 AC19 Y26 MEM_DQ55 MEM_DQ41 C20 B
V_FIELD VDD18 VDD18 MEM_DQ55 MEM_DQ36 MEM_DQ41
Y1 V_FIELD AF20 OP_B11 VDD33 AA23 MEM_A[0..11] D20 MEM_DQ36
V_ACTIVE Y2 AE20 AA24 MEM_DQ52 MEM_DQ38 A21
V_ACTIVE V_ACTIVE OP_B12 MEM_DQ52 MEM_DQ38
CPU_R D_N Y3 AD20 AA25 MEM_DQ50 MEM_DQ35 B21
CPU_RD_N RD_N RM1CLKIN PPLL_CLK_IN MEM_DQ50 MEM_DQ35
Y4 AC20 AA26 MEM_DQ53 MEM_DQ37 C21
GND GND MEM_DQ53 MEM_DQ37
RM1_CS_N
RM1_CS_N
V_VSYNC
AA1 CS_N 24.576MHz AF21 OP_B8 NTRST AB23 RM1_NTRST
MEM_DQ48 MEM_DQ34
D21 VDD33
V_VSYNC AA2 V_VSYNC AE21 OP_B9 MEM_DQ48 AB24 A22 MEM_DQ34
CPU_A1 AA3 AD1 MPLL_CLK_IN , OPLL_CLK_IN , AD21 GND TMS AB25 RM1_TMS
MEM_DQ49
MEM_DQ31
MEM_DQ33
B22 MEM_DQ31
AA4 AC21 AB26 C22
CPU_A0 AB1
VDD33
AD0
PPLL_CLK_IN are 24.576MHz AF22
VDD33
GND
MEM_DQ49
GND AC23 MEM_DQ32 D22
MEM_DQ33
MEM_DQ32
AB2 AE22 AC24 MEM_DQ30 A23
CPU_A5 WR_N VDD18 TDI R29 MEM_DQ28 MEM_DQ30
AB3 AD5 AD22 OP_B6 TCK AC25 B23 MEM_DQ28
CPU_A3 AB4 AC22 AC26 MEM_DQ29 C23
CPU_A4 AD3 GND TDO R30 MEM_DQ29
AC1 AD4 AF23 OP_B7 GND AD24 D23 GND
CPU_A2 AC2 AE23 AD25 MEM_DQ27 A24
CPU_A7 AD2 VDD33 OP_B1 1K MEM_DQ26 MEM_DQ27
AC3 AD7 AD23 OP_B4 OP_B0 AD26 B24 MEM_DQ26
AD1 DB0 AF24 OP_B3 GND AE25 C24 GND
CPU_A6 AD2 AE24 AE26 1K MEM_DQ25 A25
AD6 OP_B5 OP_B2 MEM_DQ25
CPU_A[0..7] AE1 GND AF25 GND GND AF26 B25 GND
R31 A26
33 GND
RM1_WR_N +3VA
RM1_WR_N MEM_BS
CP U_D0
+3VA L8
+ C43 C44 C45 C46 R32 MEM_CLK

RM1_MCLK_OUT
10UF/16 0.1UF 0.1UF 0.1UF 1K

Z1000/100MHZ
From Pin B12,
+1_8V +1_8V Former R25
+ C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 R33
10UF/16 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 1K
+3VA +3VA
A L9 A
+ C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 R34 RM1_OCLK_OUT
OCLK_OUT
10UF/16 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 1K
Benq Corporation
Z1000/100MHZ
From Pin AE9,
Former R22
modify this area 99.J5877.001 HT720G NA
Title
MAIN BOARD
<Size> 48.J5801.S02 99.J5877.R22-C3-304-001 0
S02

5 4 3 2 1
5 4 3 2 1
+3VS
+3VS
U6 R35 R36 R37

1 8 5.1K 2K 2K
NC VCC
2 NC WP 7
3 NC SCL 6
4 GND SDA 5
R114 R115
5.1K 5.1K AT24C16
RESET_N
CPU_ D[0..7] RESET_N KEY_LED2
PIO1 R38 33
CPU_D[0..7] KEY_LED1
CPU_A[0..19]
CPU _D[0..15]
D S DA S DA D
CP U_D0 SDA S CL S CL WRITE_PROT
SCL WRITE_PROT
CP U_D1
CP U_D2 R122 0 +3VS
FAN_CTRL +3VS
CP U_D3 R123 0 +3VS
DMD_SCL
CP U_D4 R39 R40 R41 R42
DMD_SDA
CP U_D5
CP U_D6 +3VS 10K 10K 10K 10K R43 R45 R44 R105
CP U_D7 R46 5.1K 2K
5.1K
NC_R0603 5.1K POWER
CPU_A[0..7]
2
CPU_A0 R47 R48
CPU_A1 PIO17_1 33 PIO17_2 1 Q28
CPU_A2 R49
CPU_A3 10K 10K 2N2907
3
CPU_A4
CPU_A5 PIO19 R50 33
DLP_RST
CPU_A6 +3VS
CPU_A7 R51 33
BACKLIGHT_CTRL
U8A
CPU_PCS0_N
(INT1)
14
CPU_PCS0_N
74HC132 R52 2K
+5VS
1 E1 TP37
CPU_MCS2_N
1
CPU_MCS3_N
INT0 3
POWERON_TEST
CPU_ UCS_N
I R_IN R53 33
C PU_LCS_N
2 IR
(PIO17)
CPU_TMRIN0
CPU_TMRIN1
Note: Instead of KM616V1000B,
PIO_PORT
(PIO18)
(PIO19)
CPU_INT1
IS61LV25616-12T (256K x 16 bit
7
C72
(PIO12)
(PIO13)
(PIO10)
(PIO1)
+3VS
4M) can be stuffed for debug. 470PF
INT2
(PIO2) LAMPLIT
RM1_IRQ
RM1_IRQ
CPU_A5 1 44 CPU_A6
CPU_A4 A4 A5 CPU_A7 +3VS +3VS
2 A3 A6 43
CPU_A3 U9 CPU_A8
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
3 A2 42
CPU_A2 4 IS61LV25616-12T A7 41 CPU_R D_N
CPU_A1 A1 OE# C PU_BHE_N R54
5 40
TMRIN0
INT0
INT3/INTA1/IRQ
DRQ0/INT5
DRQ1/INT6
TMROUT0
TMROUT1
TMRIN1/PIO0
MCS3/RFSH
MCS2
PCS2/CTS1/ENRX1
PCS3/RTS1/RTR1
INT1/SELECT
INT2/INTA0/PWD
RES
PCS5/A1
PCS6/A2
GND
VCC
PCS0
PCS1
GND
VCC
LCS/ONCE0
UCS/ONCE1
C PU_LCS_N A0 UB# CPU_A0 R55 R56 R57
C 6 CS# LB# 39 C
CP U_D0 7 38 C PU_D15 NC_R0603
CP U_D1 I/O1 I/O16 C PU_D14 CP U_D0 5.1K 5.1K NC_0603
8 I/O2 I/O15 37 78 AD0
CP U_D2 9 36 C PU_D13 CP U_D8 79 52 INT4 R58 33
CP U_D3 I/O3 I/O14 C PU_D12 CP U_D1 AD8 INT4 CPU_MCS1_N R119 33
10 I/O4 I/O13 35 80 AD1 MCS1 51 BALLAST_CTRL
11 34 CP U_D9 81 50 RM1_CS_N
+3VS VCC VSS AD9 MCS0 RM1_CS_N
12 VSS VCC 33 +3VS
CP U_D2 82 AD2 DEN/DS 49 PIO5
(PIO5) R59 33
MUX_SEL_Q
CP U_D4
CP U_D5
13 I/O5 I/O12 32 C PU_D11
C PU_D10
C PU_D10
CP U_D3
83 AD10 DT/R 48
C PU_NMI R61 0
PIO4
(PIO4) R60 33
KEY_LED0
14 I/O6 I/O11 31 84 AD3 NMI 47
CP U_D6
CP U_D7
15 I/O7 I/O10 30 CP U_D9
CP U_D8
C PU_D11
CP U_D4
85 AD11 SRDY 46
CP U_HOLD R62 1K
(PIO6) SY NVAL
SYNCVALID
16 I/O8 I/O9 29 86 AD4 HOLD 45
CPU _WR_N 17 28 C PU_D12 87 44 CPU _HLDA E1 R117 33
CPU_A16 WE# NC CPU_A9 CP U_D5 AD12 HLDA CPU_WLB
18 A15 A8 27 88 AD5 WLB 43 1 TP40
CPU_A15 19 26 CPU_A10 89 42 CP U_WHB 1
CPU_A14 A14 A9 CPU_A11 C PU_D13 GND U10 WHB TP41
20 A13 A10 25 90 AD13 GND 41 E1
CPU_A13 21 24 CPU_A12 CP U_D6 91 RDC8820 40 CPU_A0
CPU_A17 A12 A11 CPU_A18 AD6 A0 CPU_A1
22 NC NC 23 92 VCC A1 39
C PU_D14 93 38
AD14 VCC
(128KBytes SRAM) CP U_D7
C PU_D15
94 AD7 A2 37 CPU_A2
CPU_A3
95 AD15 A3 36
E1 TP42 96 35 CPU_A4 CPU _D[0..15]
S6/LOCK/CLKDIV2 A4
1 CPU_UZI 97 UZI A5 34 CPU_A5
CPU_TXD1 98 33 CPU_A6
CPU_RXD1 TXD1 A6 CPU_A7
99 RXD1 A7 32
100 31 CPU_A8
CPU_RXD0 CTS0/ENRX0 A8 CPU_A9 CPU_A[0..19]
CPU_RXD0 1 RXD0 A9 30
CPU_TXD0 2 29 CPU_A10
RTS0/RTR0
CPU_TXD0
BHE/ADEN
TXD0 A10
CLKOUTA
CLKOUTB
28 CPU_A11
+3VS A11 J3
ARDY
CPU_A0 1 41 CPU_A10
GND
GND
VCC
VCC
ALE
1 41
A19
A18
A17
A16
A15
A14
A13
A12
WR
CPU_A17
RD
CPU_A1 2 42 CPU_A11
S2
S1
S0
X1
X2
(PIO21)
+3VS CPU_A2 2 42 CPU_A12
3 3 43 43
CPU_A3 4 44 CPU_A13
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
CPU_A16 R63 CPU_A4 4 44 CPU_A14
1 A15 A16 48 5 5 45 45
CPU_A15 2 47 10K CPU_A5 6 46 CPU_A15
CPU_A14 A14 BYTE# CPU_A6 6 46 CPU_A16
3 A13 VSS 46 7 7 47 47
CPU_A13 C PU_D15 C PU_ARDY CPU_A7 CPU_A17
C PU_BHE_N
CPU_A12
4
5
A12 DQ15/A-1 45
44 CP U_D7 CPU_A8
8
9
8 48 48
49 CPU_A18 Link to test
A11 DQ7 9 49
CPU_A11 6 A10 DQ14 43 C PU_D14 CPU_A9 10 10 50 50 CPU_A19
board.
CPU_CLKOUTA
CPU_CLKOUTB
CPU_A10 7 42 CP U_D6 11 51
CPU_ALE
CPU_A9 A9 DQ6 C PU_D13 CP U_D0 11 51 CP U_D8
CPU_S2
CPU_S1
CPU_S0
8 A8 DQ13 41 12 12 52 52
B 10K HI_A19 9 40 CP U_D5 CPU_A12 CP U_D1 13 53 CP U_D9 B
+3VS R65 A19 DQ5 C PU_D12 CPU_A13 CP U_D2 13 53 C PU_D10
10 NC DQ12 39 14 14 54 54
CPU _WR_N 11 38 CP U_D4 CPU_A14 CP U_D3 15 55 C PU_D11
MUX_BUFFER_1
WE# DQ4 15 55
ANTI_CLKDIV_1
12 37 CPU_A15 CP U_D4 16 56 C PU_D12
RESET# VCC C PU_D11 CPU_A16 CP U_D5 16 56 C PU_D13
13 NC DQ11 36 17 17 57 57
1
14 35 CP U_D3 E1 CPU_A17 CP U_D6 18 58 C PU_D14
NC DQ3 18 58
1
15 34 C PU_D10 E1 CPU_A18 CP U_D7 19 59 C PU_D15
(PIO20)
CPU_A19 RY/BY# U12 DQ10 CP U_D2 CPU_A19 19 59
16 A18 DQ2 33 20 20 60 60
CPU_A18 17 32 CP U_D9 RESETVCC 21 61 POWERON_TEST
A17 AM29LV160DT-90EI
DQ9 TP43 RESETVCC 21 61
CPU_A8 18 31 CP U_D1 TP44 CPU_S0 22 62 CPU_ UCS_N
CPU_A7 A7 DQ1 CP U_D8 CPU_S1 22 62 FLASH1_CE
CPU_X2
CPU_X1
19 A6 DQ8 30 23 23 63 63
CPU_A6 20 29 CP U_D0 CPU_S2 24 64 RESET_N
CPU_A5 A5 DQ0 CPU_R D_N R67 24 64 RM1_IRQ
PIO20
21 A4 OE# 28 25 25 65 65
CPU_A4 22 27 1M S CL 26 66
CPU_A3 A3 VSS S DA 26 66 RM1CLKIN
23 A2 CE# 26 27 27 67 67
CPU_A2 24 25 X2 CP U_HOLD 28 68 CPU _WR_N
A1 A0 25MHZ CPU _HLDA 28 68 CPU_R D_N
29 29 69 69
+3VS
(256K x 16Bit FLASH) R68 C PU_BHE_N 30 30 70 70 CPU_MCS1_N
2
CPU_A1 FLASH1_CE CPU_ UCS_N RM1_CS_N 31 71 CPU_MCS2_N
R69 C PU_LCS_N 31 71 CPU_MCS3_N
3 1 32 32 72 72
NC_R0603 33 73 +3VS
C75 C76 CPU_RXD0 33 73
34 74 +3VS
4
R70 CPU_TXD0 34 74
35 35 75 75
10K 20PF 20PF CPU_RXD1 36 76
C YX 36 76 +3VA
CPU _WR_N 33 CPU_TXD1 37 77
CPU_WR_N 37 77
CPU_R D_N 38 78
CPU_RD_N 38 78
L6 +5VS 39 79
39 79 +5VA
+5VS 40 40 80 80
ANTI_CLKDIV
(PIO29) R71 33 Z1000/100MHZ
AMP 80PIN D0.6
MUX_BUFFER R72 33
MUX_BUFFER +12VA
(PIO21)
MUX_SEL_P
MUX_SEL_P
(PIO20) R73 33
RM1CLKIN
1
Note: Infra-Red generates two interrupts: at the rising edge and at the falling edge,
TP45
A +3VS for IR signal decoding. A
The RM1_WR_N is +3VS
delayed by 2 gates +3VS

14
14
because the data

U7B
4
U7C
9 Benq Corporation
should be stable RM1_WR_N
R74 33 CPU _DELAY2 6 CPU _DELAY1 8 CPU _WR_N C77 Project Code Model Name OEM/ODM Model Name
during the falling
5 10 +22UF/16 C78
0.1UF
C79
0.1UF
C80
0.1UF
C81
0.1UF
C82
0.1UF
C83
0.1UF
C84
0.1UF
C85
0.1UF
C86
0.1UF
C87
0.1UF 99.J5877.001 HT720G NA
edge of the WRITE
7
74VHC32 74VHC32 Title

signal. MAIN BOARD
<Size> 48.J5801.S02 99.J5877.R22-C3-304-001 0
S02

5 4 3 2 1
5 4 3 2 1
+3VS
20
KEYPAD[0..9] RP20 47_RP U13
K EYPAD0 1 2 INLTCH1_1 2 18 CP U_D0
VCC
K EYPAD1 INLTCH1_2 1A1 1Y1 CP U_D1
3 4 4 1A2 1Y2 16
7 8 8 1A4 1Y4 12
D 3 4 13 2A2 2Y2 7 D
7 8 17 2A4 2Y4 3
IOR D0_N RP21 47_RP 1
GND
1G
19 2G
+3VS +3VS
74AHC244
10
+3VS
16
20
U14A RP22 47_RP U15
CPU_A3 K EYPAD8 INLTCH2_1 CP U_D0
14
2 4 1 2 2 18
GNDVCC
VCC
CPU_A3 CPU_A4 A Y0 IOR D0_N K EYPAD9 INLTCH2_2 1A1 1Y1 CP U_D1
U7A 3 5 3 4 4 16
CPU_A4 B Y1 IOR D1_N INLTCH2_3 1A2 1Y2 CP U_D2
CPU_RD_N 1 Y2 6 LAMP_PROTECT 5 6 6 1A3 1Y3 14
IOCS_RD_SET_N WIRE_TP53 RP23 INLTCH2_4 CP U_D3
3 1 G Y3 7 1E1 7 8 8 1A4 1Y4 12
CPU_PCS0_N 2 TP53 1E1 WIRE_TP52 2 1 INLTCH2_5 11 9 CP U_D4
74VHC139 TP52 WIRE_TP51 INLTCH2_6 2A1 2Y1 CP U_D5
1E1 4 3 13 7
8
TP51 WIRE_TP46 INLTCH2_7 2A2 2Y2 CP U_D6
74VHC32 1E1 6 5 15 5
7
TP46 WIRE_TP47 INLTCH2_8 2A3 2Y3 CP U_D7
1E1 8 7 17 2A4 2Y4 3
TP47 47_RP
IOR D1_N 1
GND
1G
19 2G
74AHC244
10
DVI_SCDT
SPAREI
CPU_ D[0..7]
CPU_D[0..7] +3VS
20
U17 RP24 47_RP
CP U_D0 2 19 OUTLTCH1_1 1 2
VCC
D1 Q1 MUX_SEL
CP U_D2 D2 Q2 OUTLTCH1_3 TRIGGER
4 D3 Q3 17 5 6 SII141_PDO Note: All outputs are disabled
+3VS CP U_D4 D4 Q4 OUTLTCH1_5
RM1_RST_N after power-up until
6 D5 Q5 15 1 2 MCURESET
C CP U_D5 7 14 OUTLTCH1_6 3 4 IOCS_WR_SET_N is activated by C
D6 Q6 POWERON
+3VS CP U_D6 OUTLTCH1_7
16
8 D7 Q7 13 5 6 WRITE_PROT software.
U14B CP U_D7 9 12 OUTLTCH1_8 7 8 DLP_SPARE
D8 Q8 DLP_SPARE
CPU_A1
14
14 12
GNDVCC
CPU_A1 CPU_A2 A Y0 I OWR0_N I OWR0_N RP25 47_RP
U7D 13 11 11
GND
CPU _WR_N 12 CPU_A2 B Y1 OUT_BUFFER_OE_N CLK
CPU_WR_N Y2 10 1 OC
11 IOCS_WR_SET_N 15 9
CPU_PCS0_N G Y3 74ABT574
CPU_PCS0_N 13
10
74VHC139 R75 R76
8
74VHC32
7
10K 10K
+3VS
CPU_ D[0..7]
CPU_D[0..7]
U22
20
CP U_D0 2 19 OUTSPARE1
VCC
CP U_D1 D1 Q1 OUTSPARE2
3 D2 Q2 18
5 D4 Q4 16
7 D6 Q6 14
9 D8 Q8 12
IOWR0_N1 11
GND
OUT_BUFFER_OE_N CLK R106 R107 R108 R109 R110 R111 R112 R113
1 OC 0 0 0 0 0 0 0 0
74ABT574
10
+3VS
+3VS
SPAREO
U8B
14
74HC132
IOCS_WR_SET_N 4
6 +3VS
B 5 B
7
R77
180
U18
3 RESETVCC
VDD RESETVCC
2 +3VS
S_B UFFER GND
RES 1
+3VS AME8500BEET
C89 C90 C91 C92 C93 C94
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
+3VS
R118
R78 100K
5.1K
14
2
9 R80 1K D3
8 OUT_BUFFER_OE_N 3.3VRESET 3 BAV99
RESET_N
RESET_N 10
U8C
7
1
74HC132
C88
1U Z
** Generate Harward RESET Singnal **
VDD
A
3 SOT23 A
Benq Corporation
1 2 99.J5877.001 HT720G NA
RST GND Title
MAIN BOARD
AME8500AF27
<Size> 48.J5801.S02 99.J5877.R22-C3-304-001 0
S02

5 4 3 2 1
5 4 3 2 1
OP_A[0..23]
J4
1 1 2 2
OP_A23 3 4 OP_A22
D 3 4
5 5 6 6
OP_A21 7 8 OP_A20
7 8
9 9 10 10
OP_A19 11 12 OP_A18
11 12
13 13 14 14
OP_A17 15 16 OP_A16
15 16
17 17 18 18
OP_A15 19 20 OP_A14
19 20
21 21 22 22
OP_A13 23 24 OP_A12
23 24
25 25 26 26
OP_A11 27 28 OP_A10
27 28
29 29 30 30
OP_A9 31 32 OP_A8
31 32
33 33 34 34
OP_A7 35 36 OP_A6
35 36
37 37 38 38
OP_A5 OP_A4
39
41
39 40 40
42
PIN41, 42 is prohibited by
41 42
C
OP_A3 43
45
43 44 44
46
OP_A2
mechanical design,
OP_A1 45 46 OP_A0
47 47 48 48
49 49 50 50
OCLK_OUT 51 51 52 52 OP_HSYNC
53 53 54 54
OP_ENABLE 55 55 56 56 OP_VSYNC
57 57 58 58
DMD_SDA 59 59 60 60 LAMPLIT
61 61 62 62
DMD_SCL 63 63 64 64 DLP_RESETZ
65 65 66 66
POWER 67 67 68 68 POWERON
69 69 70 70
71 72 DLPSP R124 0
+3VS 71 72 DLP_SPARE
73 73 74 74
75 75 76 76 +3VA
77 77 78 78
79 79 80 80
+5VS 81 81 82 82
83 83 84 84
B 85 85 86 86
87 88 SYNVAGR125 0
87 88 SYNCVALID
89 90 BALLAG
89 90 BALLAST_CTRL
91 92 R126 0
91 92 +5VA
+12VA 93 93 94 94
95 95 96 96
97 97 98 98
99 99 100 100 OP_FIELD
GOLDEN_FINGER THIS PIN ONLY FOR TEST
Benq Corporation
99.J5877.001 HT720G NA
Title
A
MAIN BOARD
<Size> 48.J5801.S02 99.J5877.R22-C3-304-001 0
S02

5 4 3 2 1
MEM_DQ[0..79]
MEM_DQ[0..79]
+3VB_MEM +3VA +3VB_MEM +3VA +3VB_MEM +3VA
U19 U20 U21

1 VDD VSS 86 1 VDD VSS 86 1 VDD VSS 86
MEM_DQ16 2 85 MEM_DQ31 MEM_DQ0 2 85 MEM_DQ15 MEM_DQ48 2 85 MEM_DQ63
DQ0 DQ15 DQ0 DQ15 DQ0 DQ15
3 VDDQ VSSQ 84 3 VDDQ VSSQ 84 3 VDDQ VSSQ 84
D MEM_DQ17 4 83 MEM_DQ30 MEM_DQ1 4 83 MEM_DQ14 MEM_DQ49 4 83 MEM_DQ62 D
MEM_DQ18 DQ1 DQ14 MEM_DQ29 MEM_DQ2 DQ1 DQ14 MEM_DQ13 MEM_DQ50 DQ1 DQ14 MEM_DQ61
5 DQ2 DQ13 82 5 DQ2 DQ13 82 5 DQ2 DQ13 82
6 VSSQ VDDQ 81 6 VSSQ VDDQ 81 6 VSSQ VDDQ 81
8 DQ4 DQ11 79 8 DQ4 DQ11 79 8 DQ4 DQ11 79
11 DQ6 DQ9 76 11 DQ6 DQ9 76 11 DQ6 DQ9 76
14 NC NC 73 14 NC NC 73 14 NC NC 73
16 DQM0 DQM1 71 16 DQM0 DQM1 71 16 DQM0 DQM1 71
17 WE NC 70 17 WE NC 70 17 WE NC 70
18 CAS NC 69 18 CAS NC 69 18 CAS NC 69
19 RAS CLK 68 19 RAS CLK 68 19 RAS CLK 68
20 CS CKE 67 20 CS CKE 67 20 CS CKE 67
21 66 MEM_A9 21 66 MEM_A9 21 66 MEM_A9
NC A9 MEM_A8 NC A9 MEM_A8 NC A9 MEM_A8
22 BA0 A8 65 22 BA0 A8 65 22 BA0 A8 65
MEM_A11 23 64 MEM_A7 MEM_A11 23 64 MEM_A7 MEM_A11 23 64 MEM_A7
MEM_A10 BA1 A7 MEM_A6 MEM_A10 BA1 A7 MEM_A6 MEM_A10 BA1 A7 MEM_A6
24 A10/AP A6 63 24 A10/AP A6 63 24 A10/AP A6 63
MEM_A1 A0 A5 MEM_A4 MEM_A1 A0 A5 MEM_A4 MEM_A1 A0 A5 MEM_A4
26 A1 A4 61 26 A1 A4 61 26 A1 A4 61
A2 A3 A2 A3 A2 A3
28 DQM2 DQM3 59 28 DQM2 DQM3 59 28 DQM2 DQM3 59
30 NC NC 57 30 NC NC 57 30 NC NC 57
MEM_DQ32 31 56 MEM_DQ47 31 56 MEM_DQ64 31 56 MEM_DQ79
MEM_DQ34 DQ17 DQ30 MEM_DQ45 DQ17 DQ30 MEM_DQ66 DQ17 DQ30 MEM_DQ77
34 DQ18 DQ29 53 34 DQ18 DQ29 53 34 DQ18 DQ29 53
37 DQ20 DQ27 50 37 DQ20 DQ27 50 37 DQ20 DQ27 50
40 DQ22 DQ25 47 40 DQ22 DQ25 47 40 DQ22 DQ25 47
BS -- Bank Select MEM_DQ39 42 DQ23 DQ24 45 MEM_DQ40 42 DQ23 DQ24 45 MEM_DQ71 42 DQ23 DQ24 45 MEM_DQ72
43 44 43 44 43 44
CS -- Chip Select VDD VSS VDD VSS VDD VSS
C
RAS -- Row Address Strobe K4S643232C-TC/L10 K4S643232C-TC/L10 K4S643232C-TC/L10 C
CAS -- Column Address Strobe

WE -- Write Enable
DQM_L -- Lower Byte Data Qualifier
DQM_U -- Upper Byte Data Qualifier
(MEM_A11= =D_INA2_OVFL)
(Address and Control bus)
MEM_A[0..11]
MEM_DQM_L
MEM_WE_N
MEM_CAS_N
MEM_RAS_N
MEM_CS_N
MEM_CLK
MEM_BS
MEM_DQM_U
MEM_A11 -- Higher Bank Select (BA1) +3VA

MEM_BS -- Lower Bank Select (BA0)
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
RP26 RP27 RP28 RP29 RP30
NC_RP NC_RP NC_RP NC_RP NC_RP
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
MEM_DQM_L
MEM_DQM_U
B MEM_A0 B
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
Test parts and resistors are located at the end of bus chain.
MEM_A6
MEM_A7
All address and control signals must be routed in a daisy MEM_A8
chain, with the same trace length from RM1 to each SDRAM. MEM_A9
MEM_A10
Termination resistors values = (traces impedance) x 2 MEM_A11
MEM_BS
MEM_CS_N
MEM_WE_N
MEM_RAS_N
MEM_CAS_N
MEM_CLK
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
RP31 RP32 RP33 RP34 RP35
NC_RP NC_RP NC_RP NC_RP NC_RP
VDD - Input buffers and the
core supply
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
+3VA
+ C95 C96 C97 C98 C99 C100 C101 C102 C103

10UF/16 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
A A
L7
Z1000/100MHZ
VDD - Output buffers
+3VA +3VB_MEM Benq Corporation
C104 + C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 99.J5877.001 HT720G NA
0.1UF 10UF/16 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
Title
MAIN BOARD
<Size> 48.J5801.S02 99.J5877.R22-C3-304-001 0
S02

5 4 3 2 1
5 4 3 2 1
P3P3V
VOUT_BV[7..0]
LAMOLITZ CIRCUIT
VOUT_GY[7..0]
R16
1K
C22
VOUT_RU[7..0] 0.047U K
D R17 R18 D
LAMPLITZ 10K 2K
1 1 2 2
3
VOUT_RU7 3 J2 4 VOUT_RU6
3 4 Q1 LAMPD
5 5 6 6 1
VOUT_RU5 7 8 VOUT_RU4 MMBT2222AWT1
7 8
3
9 10 20D0038104
2
VOUT_RU3 9 10 VOUT_RU2 Q2 LAMPHIGH
11 11 12 12 1 1
13 13 14 14 MMBT2222AWT1 2
VOUT_RU1 15 16 VOUT_RU0 3
2
15 16
17 17 18 18 BALLAST_CTRL 4
VOUT_GY7 19 20 VOUT_GY6
19 20 J1
21 21 22 22
23 24
25 25 26 26
27 28 P3P3V
29 29 30 30
VOUT_GY1 31 32 VOUT_GY0 R126
31 32 NC
33 33 34 34
VOUT_BV7 35 36 VOUT_BV6
35 36 U11A
37 37 38 38 14
VOUT_BV5 39 40 VOUT_BV4 R124 1K
39 40 R19
RESETZ 1
VOUT_BV3 43 44 VOUT_BV2 3 TURNON
43 44 R112 1K
45 45 46 46 LAMPEN 2
VOUT_BV1 47 48 VOUT_BV0
47 48 47
49 49 50 50
R123 R111 7 74ACT08MTC C23
CLKIN 51 51 52 52 MHSYNCZ
53 54 10K 0.047U K
C 53 54 10K C
VIO20/M_DACT 55 55 56 56 MVSYNCZ
57 57 58 58
SDA_DI 59 59 60 60 LAMPLITZ
61 61 62 62
63 64
SCL_DI
65
63 64
66
RESETZ LAMPEN CIRCUIT
65 66
BALLAST_CTRL 67 67 68 68
69 69 70 70
71 71 72 72 PWRGOOD
73 74 P3P3V
73 74 P3P3V_IN R125
75 75 76 76
77 78 L6 80 OHM
77 78 10K 3V3_SENSOR
79 79 80 80
81 82 C24 C25
81 82 0.1U Z 0.1U Z P3P3V 3V3_SENSOR
83 83 84 84
85 85 86 86 L9
P12V 87 88 SYNCVALID
87 88 R22
L8 89 89 90 90
91 92 2K
P12V_IN 91 92 P5V 120 OHM
93 93 94 94 R27
80 OHM 95 96 P5V_IN L7 C36
95 96 C34 C35 R26 0.047U K
97 97 98 98 80 OHM
C28 C29 99 100 0.047U K 4.7U Z 10K R24
0.1U Z 0.1U Z 99 100 C26 C27 (1206)
510K 180
0.1U Z 0.1U Z
2
20C1001100
2V_REF 3 +
1
4 - CWINDEX
B R29 U4 B
(To DDP1010)
6.8K LMC7225
5
R25 J3
INPUT SIGNALS FROM MAIN BOARD 75K OPDIODE
R28 1
CWSPPED1 CWSPEED 2
3
P3P3V 20L2021003
10K C33 C30
TP51 10P J 0.1U Z
R121 NC_R0603
SCL_DI SCL_D
R119 R120 CWINDEX CIRCUIT
4.7K 4.7K
TP50 TP49 J5
(IIC From Main CPU)
4
5
6
SW2 SCL_DTI 3
4
5
6
SDA_DTI 2
2240138001 1
1
2
3
INPUTS, LAMPEN, LAMPLIZ, CWINDEX

1
2
3
20L2021003
A
SDA_DI (IIC From Computer)
(Connector for DLP FALSH DOWNLOAD)
Benq Corporation A
R122 NC_R0603
99.J5877.001 HT720G NA
SDA_D
Title
DMD BOARD

<Size> 48.J5802.S01 99.J5877.R22-C3-304-002 0
S01
TP52
Date: Tuesday, January 14, 2003 Sheet 1 of 8
ANGEL HU ALEX HY TSENG BEN CHEN
5 4 3 2 1
5 4 3 2 1
FLDATA[0..15] FLDATA[0..15]
P3P3V
D D
DDP1010 C21
13
10
37
FLADDR[0..18] U3 0.1U Z
FLDATA0 AG26 AH7
NC
NC
VCC
FLDATA1 FLDATA0 FLADDR19 FLADDR18 FLADDR0
AH26 FLDATA1 FLADDR18 AF8 25 A0
FLDATA2 AJ26 AG8 FLADDR17 FLADDR1 24
FLDATA3 FLDATA2 FLADDR17 FLADDR16 FLADDR2 A1
AF25 FLDATA3 FLADDR16 AF9 23 A2
FLDATA4 AG25 AG9 FLADDR15 FLADDR3 22
FLDATA5 FLDATA4 FLADDR15 FLADDR14 FLADDR4 A3
AJ25 FLDATA5 FLADDR14 AH9 21 A4
FLDATA6 AJ24 AG10 FLADDR13 FLADDR5 20 29 FLDATA0
P5V FLDATA7 FLDATA6 FLADDR13 FLADDR12 FLADDR6 A5 D0 FLDATA1
AF24 FLDATA7 FLADDR12 AJ10 19 A6 D1 31
FLDATA8 AG24 AG13 FLADDR11 FLADDR7 18 33 FLDATA2
FLDATA9 FLDATA8 FLADDR11 FLADDR10 FLADDR8 A7 D2 FLDATA3
AH24 FLDATA9 FLADDR10 AH13 8 A8 D3 35
FLDATA10 AF23 AJ14 FLADDR9 FLADDR9 7 38 FLDATA4
AG23 FLDATA11 FLADDR08 AF15 6 A10 D5 40
R7 R8 FLDATA12 AG22 AJ15 FLADDR7 FLADDR11 5 42 FLDATA6
10K 10K AJ22 FLDATA13 FLADDR06 AJ17 4 A12 D7 44
FLDATA14 AF20 AH17 FLADDR5 FLADDR13 3 30 FLDATA8
AJ21 FLDATA15 FLADDR04 AH18 2 A14 D9 32
AG19 FLADDR3 FLADDR15 1 34 FLDATA10
FLADDR03 FLADDR2 FLADDR16 A15 D10 FLDATA11
IIC Bus (open drain) FLADDR02 AH20 48 A16 D11 36
AJ20 FLADDR1 FLADDR17 17 39 FLDATA12
DDP2P5V FLADDR01 FLADDR0 FLADDR18 A17 D12 FLDATA13
L4 SDA_D AH23 SDA0 FLADDR0 AG20 16 A18 D13 41
SCL_D AF22 9 43 FLDATA14
SCL0 NC D14 FLDATA15
15 RY/BY D15/A-1 45
120 OHM FL_OE AH27 47 BYTE
Minimize Noise on PLL_VCCA AG28 APLLMD1
AF28 APLLMD0 FL_WE AJ27 14 NC
C17 C18 AG29 FL_OEZ 28
PLL_VCCA OE
29LV800BB-90EC
C 0.1U Z 0.1U Z AF19 FL_WEZ 11 C
FL_CS FL_CSZ WE
26 CE
OCLKA AF27 COSC
P3P3V 12
VSS
VSS
TP39 TP40 TP41 RST
L5 Master Clock (100MHz) FLASH
F3 MOSCN
VDDMOSC 4 3 MOSC F2 AM29LV800BB-120EC
27
46
VCC OUT MCRYSTALEN MOSC
120 OHM G4 MCRYSTALEN SR16STRB V2 SR16STROBE
MOSCEN 1 C31 R10
R11 OE GND 2
22P J 39.2F SR16OEZ W3 SR16OEZ (To DAD1000) 7229800219
Y1 G3 R4 SR16ADDR3 (Pin 14 should be disconnected from P3P3V)
10K 100MHZ L19 POSCN SR16ADDR3
G2 POSC SR16ADDR2 R1 SR16ADDR2
C19 C20 220OHM H4 U1
0.1U Z 0.1U Z PCRYSTALEN SR16ADDR1 SR16ADDR1
68.00129.0D1 U2
SR16ADDR0 SR16ADDR0
T26
Pixel Clock (74.25MHz) from Scalar CLKIN
WCLK
SR16MODE1 N2 SR16MODE1
DDP3P3V TP30 TP29 TP28 P1
SR16MODE0 SR16MODE0
R12 AB28 Y2 SR16SEL1
1K DRCGPDZ DIO0 SR16SEL1
DADSELZ AA26 DIO1 SR16SEL0 Y1 SR16SEL0
AB27 DIO2
SERIES CONTROL PORT 0 AB26 DIO3 DMDBIN3 J3
SCPDO AC28 DIO4 DMDBIN2 K3
(To MUSTANG) SCPDI AC27 DIO5 DMDBIN1 K1
SCPCLK AC26 DIO6 DMDBIN0 N3
TP31 PWM0 AD28
DDP3P3V DIO7 TP37 TP38
SR16VCCEN AB1
B B
DMDVCCEN Y4
TP32 PWM1 AD27 AA1
DIO8 VCC2EN
MTRPWM AD29 DIO9 VBIASEN Y3
AE28 DIO10 VRSTEN W4 SERIES CONTROL PORT 1
R13 AE29
R14 DIO11/ASICID0
AE27 DIO12/ASICID1 SCP1_CLK AF1 SCP_CLK (To DAD1000)
1.33KF 1.33KF AE26 AF2 SCP_DO
DIO13/ASICID2 SCP1_DO
DMDSPARE0 AF29 DIO14 SCP1_DI AF3 SCP_DI
AH3 TP45 TP46 TP47 TP48
DMDSPARE1 DIO15 TSTPNT3
DMDSPARE0 TSTPNT3 A21
D19 TSTPNT2
DMDSPARE1 TSTPNT2
C20 TSTPNT1
TSTPNT1 TSTPNT0
MTRRSTZ AG4 DIO16 TSTPNT0 A20
4
3
(To SSI Motor) MTRSELZ AH4 DIO17

SW1 AJ4 (v-sync, delay CWI, spoketest for debug)
DDP3P3V MTRCLK DIO18
6240019001 MTRDATA AF5 DIO19 OCLKF J2
AG5 DIO20
TP2 ARMTEST1 AH6 H3
TP1 ARMTEST2 DIO21 OCLKE
AF7
1
2
DIO22
DADINTZ AG7 DIO23 OCLKD F1
R114
R115 R113 10K TP33TP27TP26 E1 TP36
10K OCLKC
10K
DIO24 AB3 D1 50MHz Clock
IDO25 AB4
DIO24 OCLKB R15 22 DDP1010 Flash, Micro, Clocks, DAD1000 Control
DIO25 OCLKA1
AC2 E3 OCLKA
CWINDEX DIO26 OCLKA
Benq Corporation
MTRDMUX AC3 DIO27
DMDRSTZ AC4 DIO28
A AD2 C1 PUM_ARSTZ A
DIO29 PUM_ARSTZ Project Code
DIO31 DMDSELZ AD3 DIO30 EXT_ARSTZ D2 EXT_ARSTZ (To DAD1000) Model Name OEM/ODM Model Name
AD4 DIO31 EXT_ARST D3 HT720G
99.J5877.001 NA
Title
R116 DMD BOARD
NC_R0603
U2B DDP1010
Micro, Clocks ,SR16 and Flash interface TP34 TP35
<Size> 48.J5802.S01 99.J5877.R22-C3-304-002 0
S01

5 4 3 2 1
5 4 3 2 1
TP42
VOUT_GY[7..0] U2C DDP1010 DDAP[15..0]
VOUT_GY7 K28 DDAN[15..0]
VOUT_GY6 A9 DDAP15
K29 A8 DDAP15 H1
VOUT_GY5 K27 J1 DDAP14 LVDS Differential DataBus DDA
VOUT_GY4 A7 DDAP14 DDAP13
L26 A6 DDAP13 K2
Video Inputs From Scalar VOUT_GY3 J29 L1 DDAP12 (To Mustang DMD)
J28 A4 DDAP11 L2
RGB 888 Format (24bits) VOUT_GY1 J27 M2 DDAP10
K26 A2 DDAP9 N1
H29 P3 DDAP8
A1 DDAP8 DDAP7
H28 A0 DDAP7 T3
D U3 DDAP6 D
TP43 DDAP6 DDAP5
VOUT_BV[7..0] DDAP5 V3
V4 DDAP4
VOUT_BV7 DDAP4 DDAP3
N29 B9 DDAP3 AA2
VOUT_BV6 N28 AB2 DDAP2
VOUT_BV5 B8 DDAP2 DDAP1
N27 B7 DDAP1 AD1
VOUT_BV4 N26 AE3 DDAP0
VOUT_BV3 B6 DDAP0 DDAN15
M28 B5 DDAN15 K4
VOUT_BV2 M27 L4 DDAN14
VOUT_BV1 B4 DDAN14 DDAN13
L28 B3 DDAN13 L3
VOUT_BV0 M26 M4 DDAN12
B2 DDAN12 DDAN11
L29 B1 DDAN11 M3
L27 N4 DDAN10
TP44 B0 DDAN10 DDAN9
DDAN9 P4
VOUT_RU[7..0] P2 DDAN8
DDAN8 DDAN7
DDAN7 T4
VOUT_RU7 T28 U4 DDAN6
VOUT_RU6 C9 DDAN6 DDAN5
T29 C8 DDAN5 W2
VOUT_RU5 R26 W1 DDAN4
R27 C6 DDAN3 AA3
VOUT_RU3 R28 AA4 DDAN2 LVDS Differential DataBus DDB
R29 C4 DDAN1 AE2
VOUT_RU1 P29 AE4 DDAN0 (To Mustang DMD)
VOUT_RU0 C3 DDAN0
P28 C2
P27 C1 DDBP[15..0]
P26 C0
AH22 DDBP15
DDBP15 DDBP14
DDBP14 AH21 DDBN[15..0]
AF18 DDBP13
C DDBP13 DDBP12 C
VIO20/M_DACT U26 MACT DDBP12 AG18
Video Syncs From Scalar MVSYNCZ U28 AG17 DDBP11
MVSYNCZ DDBP11 DDBP10
MHSYNCZ U27 MHSYNCZ DDBP10 AG16
AJ16 DDBP9
DDBP9 DDBP8
DDBP8 AG15
AH12 DDBP7
DDBP7 DDBP6
W29 SACT DDBP6 AH11
W27 AJ11 DDBP5
SVSYNCZ DDBP5 DDBP4
V26 SHSYNCZ DDBP4 AH10
AJ9 DDBP3
DDBP3 DDBP2
DDBP2 AH8
AF6 DDBP1
DDBP1 DDBP0
V28 OSDACT DDBP0 AJ5
AF21 DDBN15
DDBN15 DDBN14
DDBN14 AG21
AJ19 DDBN13
DDBN13 DDBN12
F29 RMG7 DDBN12 AH19
E28 AF17 DDBN11
RMG6 DDBN11 DDBN10
E29 RMG5 DDBN10 AF16
E27 AH16 DDBN9
RMG4 DDBN9 DDBN8
E26 RMG3 DDBN8 AH15
D29 AF13 DDBN7
RMG2 DDBN7 DDBN6
B27 RMG1 DDBN6 AG12
A27 AF12 DDBN5
RMG0 DDBN5 DDBN4
DDBN4 AG11
AF11 DDBN3
DDBN3 DDBN2
DDBN2 AJ8
D24 AG6 DDBN1
RMB7 DDBN1 DDBN0
C24 RMB6 DDBN0 AH5
B B
B24 RMB5
D23 RMB4
C23 RMB3
B23 RMB2 DCKAP T1 DCLKAP LVDS Differential DCLKA
D22 RMB1 DCKAN T2 DCLKAN
C22 RMB0
SCAP R3 SCTRLAP LVDS Differential Series Control Bus A

SCAN R2 SCTRLAN
C26 RMR7
B26 RMR6
A26 RMR5 DCLKBP AJ13 DCLKBP LVDS Differential DCLKB
D25 RMR4 DCLKBN AF14 DCLKBN
C25 RMR3
A25 RMR2
B25 RMR1 SCBP AG14 SCTRLBP LVDS Differential Series Control Bus B
A24 RMR0 SCBN AH14 SCTRLBN
RMHSOZ AA27
H27 RMA7 RMVSOZ AA28
H26 RMA6
G28 RMA5
G27
G26
RMA4
Y27
DDP1010 Video Input and DMD Output
RMA3 HSYNCOZ
F28 RMA2 VSYNCOZ W26
Benq Corporation
F27 RMA1
F26 RMA0
A
DDP3P3V J26 A
RMACT Project Code
AA29 Model Name OEM/ODM Model Name
FSD16
99.J5877.001 HT720G NA
R70 Y28
(NC) RMVSYNCZ
Y29 RMHSYNCZ Title
DMD BOARD

FSD16 T27 <Size> 0
FILEDSYNC 48.J5802.S01 S01 99.J5877.R22-C3-304-002
SYNCVALID C28 SYNCVALID2
5 4 3 2 1
5 4 3 2 1
VTERM (1.8V) Bulk Decoupling Caps
C207 C208 C209 C210 C211

0.1U Z 0.1U Z 0.1U Z 0.1U Z 0.1U Z
DDP3P3V
U10 R109
3.4KF
DQA3
DQA8
DQA4
DQA7
DQA0
DQA6
DQA5
DQA2
DQA1
DQB5
DQB6
DQB2
DQB3
DQB8
DQB4
DQB7
DQB1
DQB0
RQ5
RQ0
RQ4
RQ1
RQ6
RQ7
RQ2
RQ3
MIC39100-1.8BS
1 IN OUT 3
GND1
GND2
8
7
6
5
5
6
7
8
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
D
C218 C219 C220 C221 C222 R110 D
1
0.1U Z 0.1U Z 0.1U Z 0.1U Z 0.1U Z
39
39
39
39
39
39
11.8KF R6 R9
C223
RN6
RN5
RN4
RN3
RN2
RN1
+ C231 + 39.2F 39.2F
2
4
4.7U Z 100U
(1206) 6.3V VTERM
1
2
3
4
4
3
2
1
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
C230
100U
6.3V C226 C227 C228
0.1U Z 0.1U Z 0.1U Z
VTERM
R108 1.8V
VREF_ASIC 110F VREF_RDRAM
Termination Components
C213 C212 U2A

0.1U Z 0.1U Z
DDP1010 RQ[7..0]
RamBus Address Channel
Rambus, JTAG and Customer Input
DQA[0..8]
RamBus Data Channel A
V27
LAMPLITZ LAMPSTAT
LAMPEN
Y26 LAMPCTRL RQ7 DQB[0..8]
RamBus Data Channel B
RQ7 B11
AG2 C12 RQ6
PWRGOOD PWRGOOD RQ6
C13 RQ5
RQ5 RQ4
RESETZ C2 STARTZ RQ4 B13
RQ3
U8 K4R271669D
RQ3 D14
C VREF_ASIC A11 C14 RQ2 RQ0 G1 J1 DQB8 C
RD_VREF1 RQ2 RQ1 C225 RQ1 RQ0 NC1 DQB7
RQ1 A15 F2 RQ1 DQB7 J7
DDP2P5V B8 B15 RQ0 0.1U Z RQ2 F6 H2 DQB6
RD_VREF0 RQ0 RQ3 RQ2 DQB6 DQB5
F7 RQ3 DQB5 H6
B9 A4 DQA8 RQ4 F1 H7 DQB4
RD_AVDD0 DQA8 DQA7 RQ5 RQ4 DQB4 DQB3
DQA7 D5 E7 RQ5 DQB3 H1
D12 B5 DQA6 RQ6 E6 G2 DQB2
C194 C195 C196 RD_AVDD1 DQA6 DQA5 R95 RQ7 RQ6 DQB2 DQB1 VDRCG
DQA5 A6 E2 RQ7 DQB1 G6
0.1U Z 68P J 0.1U Z DQA4 1K DQB0 VDRCG
DQA4 C6
DQA3 SIO1 DQB0 G7 U9
DQA3 B6 J3 SIO1
C7 DQA2 SIO J5 C1 DQA0 CDCR83
DQA2 DQA1 CMD SIO0 DQA0 DQA1 R94
E4 TDO2 DQA1 B7 A5 CMD DQA1 C2
JTAG is inactive for normal operation TRSTZ D8 DQA0 SCK A3 C6 DQA2 110F 2 DDP2P5V
DQA0 SCK DQA2 DQA3 CTM CTM1_M REFCLK
C29 TMS2 DQA3 B1 20 CLK SYNCLKN 7
TCK C19 DQB8 CTM E1 B7 DQA4 3 6
DQB8 DQB7 CTMN CTM DQA4 DQA5 VDD PCLKM
J4 TDO1 DQB7 A19 D1 CTMN DQA5 B6 9 VDD
B19 DQB6 CFM C7 B2 DQA6 R98 16 15 R96 R100
R117 R118 DQB6 DQB5 CFMN CFM DQA6 DQA7 VDD MULT0 1K
D27 TMS1 DQB5 C18 D7 CFMN DQA7 A7 22 VDD MULT1 14 1K
1K 1K C17 DQB4 D2 A1 DQA8 56.2F 19
DDP3P3V DQB4 DQB3 VREF NC2 NC
B3 TDI DQB3 B17 S0 24
D16 DQB2 R104 A2 D5 CLKTM C197 23
DQB2 DQB1 39.2F VCMOS GNDA 4.7P C S1
AG1 TRSTZ/IBMT_LT DQB1 C16 J2 VCMOS GND A6 S2 13
A16 DQB0 D6 B3 C198 4
R101 R102 DQB0 CLKFM VDDA GND GND
C4 TCK B5 P2P5V GND C5 5 GND PWRDNB 12 DRCGPDZ
10K 10K C3 D3 0.1U Z R99 8 11 STOPZ
SCK R103 C201 P2P5V GND 56.2F GND STOPB
RD_SCK B22 E5 P2P5V GND E3 17 GND
A22 CMD 39.2F 0.1U Z F3 F5 21 1 DDP2P5V
ICEOENZ RD_CMD SIO P2P5V GND GND VDDIR
A3 ICEOENZ RD_SIO D21 G5 P2P5V GND G3
D10 CFM H5 H3 CTMN CTMN1_M 18 10
B ICTSENZ RD_CFM CFMN P2P5V GND CLKB VDDIPD B
D28 ICTSENZ RD_CFMN C9 GND J6
C10 CTM R97
RD_CTM CTMN 110F C199 C200
AJ3 IBMT_RI RD_CTMN D11
0.1U Z 0.1U Z
PCLKM C21 PCLKM1 R105 22 PCLKM

W28 POSTST
SCLKN D20 SCLKN1 R106 22 SCLKN
E2 LSSDEN Direct Rambus Clock Generator (DRCG)
REFCLK B21 REFCLK1 R107 22 REFCLK
P3P3V VDRCG
RDRAM
L18 CDCR83 (DRCG) 3.3V Decoupling Caps
120 OHM
RDRAM Memory Control C184 C185 C186 C187 C188 C189 C190 C191 C192 C193
0.1U Z 4.7U Z 0.1U Z 68P J 0.1U Z 68P J 0.1U Z 68P J 0.1U Z 68P J
(1206)
DDP2P5V
RDRAM VDD (2.5V) DECOUPING CAPS
1
C202 C203 C204 C205 + C229
Benq Corporation
0.1U Z 0.1U Z 0.1U Z 0.1U Z 150U
6.3V
2
A A
99.J5877.001 HT720G NA
Title
DMD BOARD

<Size> 48.J5802.S01 99.J5877.R22-C3-304-002 0
S01

5 4 3 2 1
5 4 3 2 1
Screw Holes Screw Holes

Optical Points
MARK1 MARK2 MARK3 MARK4 MARK5 MARK6 MARK7

OP OP OP OP OP OP OP
1
5 9 5 9 5 9 5 9 5 9 5 9 5 9 5 9
4 8 4 8 4 8 4 8 4 8 4 8 4 8 4 8
MARK9 MARK11 MARK12 MARK14 MARK17 MARK18 MARK20
3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 OP OP OP OP OP OP OP
D D
2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6
H1 H2 H3 H4 H5 H6 H7 H8
HOLE-V8 HOLE-V8 HOLE-V8 HOLE-V8 HOLE-V8 HOLE-V8 HOLE-V8 HOLE-V8 MARK8 MARK10 MARK13 MARK15 MARK16 MARK19 MARK21
MARK22 MARK23 MARK24

OP OP OP
DDP3P3V
AC29
AD26
AA25
AB29
AC1
M29
M12
M13
M14
M15
M16
M17
M18
G29
AA5
AE1
C27
D26
N25
U25
U29
N12
N13
N14
N15
N16
N17
N18
R12
R13
R14
R15
R16
R17
R18
U12
U13
U14
U15
U16
U17
U18
A12
A18
A23
A28
A29
B28
B29
E13
E17
E21
E25
V29
P12
P13
P14
P15
P16
P17
P18
V12
V13
V14
V15
V16
V17
V18
T12
T13
T14
T15
T16
T17
T18
U 2D
J25
M1
G1
C3
D4
N5
U5
A1
A2
A7
B1
B2
E5
E9
V1
F4
J5
DDP1010
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C119 0.1U Z
AE20 VCC33
C120 0.1U Z
AE19 VCC33
C121 0.1U Z
AE18 VCC33
C122 0.1U Z
AE12 VCC33
C123 0.1U Z
AE11 VCC33
C C124 0.1U Z C
AE10 VCC33
C125 0.1U Z
Y5 VCC33
C126 0.1U Z
W5 VCC33
C127 0.1U Z
V5 VCC33 GND AJ29
GND AJ28
C128 0.1U Z AJ23
GND
M5 VCC33 GND AJ18
GND AJ12
C129 0.1U Z AJ7
GND
L5 VCC33 GND AJ6
GND AJ2
C130 0.1U Z AJ1
GND
K5 VCC33 GND AH29
GND AH28
C131 0.1U Z AH25
GND
Y25 VCC33 GND AH2
GND AH1
C132 0.1U Z AG27
GND
W25 VCC33 GND AG3
GND AF26
C133 0.1U Z AF10
GND
V25 VCC33 GND AF4
GND AE25
C134 0.1U Z AE21
GND
M25 VCC33 GND AE17
GND AE13
C135 0.1U Z AE9
GND
L25 VCC33 GND AE5
C136 0.1U Z
K25 VCC33
B B
DDP2P5V
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
VCC25
U2E
T25
F25
G25
H25
P25
R25
AB25
AC25
AD25
F5
G5
H5
P5
R5
T5
H2
AB5
AC5
AD5
AE6
AE7
AE8
AE14
AE15
AE16
AE22
AE23
AE24
E6
E7
E8
E14
E15
E16
E22
E23
E24
E10
E11
E12
E18
E19
E20
DDP2P5V B20 D18
RD_VDD5 RD_RSGND17
D15 RD_VDD3 RD_RSGND16 D17
B4 RD_VDD0 RD_RSGND15 A17
RD_RSGND14 B16
C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C151 C152 C153 C154 C155 C156 C157 C158 C159 C160 C161 C162 C163 C164 C165 C166 C167 C15
RD_RSGND13
RD_RSGND12 B14
B18 RD_RGND10 RD_RSGND11 A13
A14 RD_RGND7 RD_RSGND10 B12
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U D13 C11
RD_RGND6 RD_RSGND9
A10 RD_RGND4 RD_RSGND8 B10
C5 RD_RGND0 RD_RSGND7 A9
RD_RSGND6 A8
RD_RSGND5 D9
C8 RD_RGNDC RD_RSGND3 D7
RD_RSGND2 D6
RD_RSGND1 A5
U7 DDP1010
MIC39100
P3P3V 4
GND
1 IN GND 2
OUT
P3P3V
C180 DDP3P3V
4.7U Z DDP2P5V L15
3
A (1206) A
L17
P2P5V_IN 80 OHM
1
Benq Corporation
C181 C182 80 OHM C183 + C236 C115 C116 C232 C233 C234 C235
4.7U Z 0.1U Z 0.1U Z 150U 0.1U Z 0.1U Z 4.7U Z 4.7U Z 4.7U Z 4.7U Z
(1206) 6.3V (1206) (1206) (1206) (1206) (1206)
2
99.J5877.001 HT720G NA
Title
DMD BOARD
DDP3P3V Decoupling Caps Size PCB P/N P CB Rev. Document Number Rev.
2.5V Regulator and Decoupling Caps <Size> 48.J5802.S01 S01 99.J5877.R22-C3-304-002 0

5 4 3 2 1
A
B
C
D
VCC
0
R58
VCC A3
0
R59
C63
TP6
0.1U
SCPDI
SCPDO
A11
SCPCLK
VCC
DMDSELZ
DMDRSTZ
0
R60
C64
0.1U
TP7
VCC A21
5
5
R62
R61
C65
0.1U
DCLKAP
DCLKAN
SCTRLAP
SCTRLAN
A13
R57 33
VCC
TP8
DCLKBP
DCLKBN
0
C66
SCTRLBP
SCTRLBN
0.1U
A33
EVCC3
EVCC2
EVCC1
EVCC0
VCC
TPM2
TPM1
TPM0
C67
0.1U
SCPDOM
VCC A27
W7
W9
W11
SCRLR A9
U7
V6
A7
C33
V34
C9
D8
B8
D6
B6
U13
Y10
C68
0.1U
VCC A35
TP2
TP1
TP0
EVCC
EVCC
EVCC
EVCC
B38
SCPDI
VCC
SCPEN
SCPCK
SCPDO
W35 DCLK_BP DCLK_AP B34
C69 C70
SCR_CLR
0.1U0.1U
W37 B36 A5
FUSE_CLK
DCLK_BN DCLK_AN GND
FUSE_DATA
DDBP[15..0]
A15 GND VCC C1
DMD_RESETB
U33 SCTRL_BP SCTRL_AP D34 A37 GND
C71
PROG_FUSE_EN
DDAP[15..0]
0.1U
U35 SCTRL_BN SCTRL_AN D36 B2 GND

B4 GND VCC D2
B12 GND
C72
DDBP0 DDAP0
0.1U
Y24 D_BP0 D_AP0 A23 B14 GND

DDBP1 U21 D22 DDAP1 B16 E1
DDBP2 D_BP1 D_AP1 DDAP2 GND VCC
W25 D_BP2 D_AP2 B24 B18 GND
C73
DDBP3 DDAP3
0.1U
U23 D_BP3 D_AP3 D24 B20 GND

DDBP4 Y30 B28 DDAP4 B26 F40
V28 D_BP5 D_AP5 C27 B32 GND
C74
DDBP6 DDAP6
0.1U
W31 D_BP6 D_AP6 B30 C3 GND

DDBP7 V30 C29 DDAP7 C5 F4
U37 D_BP8 D_AP8 D38 C7 GND
C75
DDBP9 DDAP9
0.1U
T36 D_BP9 D_AP9 E35 C13 GND

DDBP10 T38 E37 DDAP10 C15 J3
P36 G35 C17
4
4
D_BP11 D_AP11 GND

C76
DDBP12 DDAP12
0.1U
P38 D_BP12 D_AP12 G37 C19 GND

DDBP13 N35 H36 DDAP13 J39
DDBP14 D_BP13 D_AP13 DDAP14 VCC
L39 D_BP14 D_AP14 K40
C77
DDBP15 DDAP15
0.1U
L35 K36
U6A
DDBN0 D_BP15 D_AP15 DDAN0
W23 B22 K2
U6B
DDBN1 D_BN0 D_AN0 DDAN1 VCC

V22 D_BN1 D_AN1 C21
C78
DDBN2 DDAN2
0.1U
Y26 D_BN2 D_AN2 A25
MUSTANG
DDBN3 V24 C23 DDAN3 L1
D_BN3 D_AN3 VCC
MUSTANG
DDBN4 W29 A29 DDAN4

D_BN4 D_AN4
C79
DDBN5 DDAN5
0.1U
U27 D_BN5 D_AN5 D28

DDBN6 Y32 A31 DDAN6 M40
DDBN7 D_BN6 D_AN6 DDAN7 VCC
U29 D_BN7 D_AN7 D30
C80
DDBN8 DDAN8
0.1U
U39 D_BN8 D_AN8 D40

DDBN9 T34 E33 DDAN9 C25 P4
DDBN10 D_BN9 D_AN9 DDAN10 GND VCC
T40 D_BN10 D_AN10 E39 C31 GND
C81
DDBN11 DDAN11
0.1U
P34 D_BN11 D_AN11 G33 C35 GND

DDBN12 P40 G39 DDAN12 C37 R3
DDBN13 D_BN12 D_AN12 DDAN13 GND VCC
N33 D_BN13 D_AN13 H34 C39 GND
C82
DDBN14 DDAN14
0.1U
L37 D_BN14 D_AN14 K38 D4 GND

DDBN15 L33 K34 DDAN15 D10 R39
D_BN15 D_AN15 GND VCC
D16 GND
C83
0.1U
D18 GND
RVB0 V10 C11 RV_A0 D20 T2
RVB1U11 RSV_B0 RSV_A0 GND VCC
RSV_B1 RSV_A1 D14 RV_A1 D26 GND
C84
0.1U
RVB2 Y8 B10 RV_A2 D32

RSV_B2 RSV_A2 GND
R63
R52
10K
10K
Y18 RSV_B3 RSV_A3 A17 E3 GND VCC U1

Y20 RSV_B4 RSV_A4 A19 E5 GND
C85
0.1U
E7 GND
R64
R53
10K
10K
RV_A3
F6 V2
DDBN[15..0]
DDAN[15..0]
GND VCC
F8 GND
C86
0.1U
RV_A4
F34 GND
RVB3
RVB4
R65
R54
10K
10K
F36 W3
READOUTB1
READOUTB0
MBRST15
MBRST14
MBRST13
MBRST12
MBRST11
MBRST10
MBRST09
MBRST08
MBRST07
MBRST06
MBRST05
MBRST04
MBRST03
MBRST02
MBRST01
MBRST00
READOUTA1
READOUTA0
GND VCC
3
3
F38 GND
C87
0.1U
G3 GND
R66
R55
L3
L5
K4
P6
N7
N5
N3
U5
10K
10K
M6
M4 G5 W39
Y12
V18
V16
V12
D12
U17
U15
W19
W17
W13
GND VCC
G7 GND
C88
0.1U
H4 GND
R67
R56
10K
10K
H6 GND VCC Y4
H8 GND
C89
0.1U
J5 GND
MBRST9
MBRST8
MBRST7
MBRST6
MBRST5
MBRST4
MBRST3
MBRST2
MBRST1
MBRST0
J7 Y14
MBRST15
MBRST14
MBRST13
MBRST12
MBRST11
MBRST10
GND VCC
J33 GND
C90
0.1U
J35 GND
READOUTA1
READOUTA0
J37 GND VCC Y22

READOUTB1
READOUTB0
K6
TP10
GND
K8 GND
L7 GND VCC Y28
M8
TP11
GND
TP9
M34 GND
M36 GND VCC Y34
M38
TP12
GND
P8 GND
R5 GND VCC Y36
R7 GND
R33 GND
R35 GND
MBRST[15..0]
R37 GND VCC2 F2

T4 GND
C95
0.1U
T6 GND
T8 GND VCC2 G1
U3 GND
C96
0.1U
U9 GND
U19 GND VCC2 H2
U25 GND
C97
P3P3V
0.1U
U31 GND
2
2
VCC2 H38
C98
0.1U
H40
C111
VCC2
0.1U Z
C99
0.1U
L14
VCC2 J1
V4 GND
0.1U
V8
120 OHM
GND
V14 GND VCC2 M2
V20 GND
0.1U
V26 GND
V32 GND VCC2 N1
V36 GND
0.1U
V38
Title
GND
<Size>
V40 N37
C112
GND VCC2
VCC
W5
0.1U Z
GND
0.1U
W15 GND
Project Code
VCC2 N39
W21
Size PCB P/N
GND
0.1U
W27
C100 C101 C102 C103 C104
Prepared By
GND
ANGEL HU
99.J5877.001
W33 GND VCC2 P2

Y6
C107
GND
Y16
2.2U Z
GND
48.J5802.S01
Y38 GND VCC2 R1

Date: Tuesday, January 14, 2003
C108
2.2U Z
Model Name
DMD BOARD
S01
1
1
HT720G
Reviewed By
ALEX HY TSENG
C109
Sheet
2.2U Z
VCC2
Benq Corporation
1U Z
C113
6
MUSTANG (HD2) DMD
PCB Rev. Document Number

C110
2.2U Z
of
NA
8
1U Z
99.J5877.R22-C3-304-002
C114
Approved By
BEN CHEN
OEM/ODM Model Name
0
R ev.
A
B
C
D
5 4 3 2 1
P3P3V
R1 TP13
D 1K TP14 TP18 D
MBRST[15..0]
TP16 TP15
U1
RP1 10
SCP_CLK 56 79 RST15 5 4 MBRST15
SCP_CLK OUT15 RST14 MBRST14
SCP_DO 57 SCPDI OUT14 77 6 3
SCP_DI 42 74 RST13 7 2 MBRST13
SCPDO OUT13 RST12 MBRST12
DADSELZ 58 SCPENZ OUT12 72 8 1
69 RST11 5 4 MBRST11
OUT11 RST10 MBRST10
SR16STROBE 15 STORBE OUT10 67 6 3
SR16MODE1 2 64 RST9 7 2 MBRST9
MODE1 OUT09 RST8 MBRST8
SR16MODE0 3 MODE0 OUT08 62 8 1
SR16SEL1 4 RP2 10
SEL1 RP3 10
SR16SEL0 5 SEL0
39 RST7 5 4 MBRST7
OUT7 RST6 MBRST6 P3P3V
OUT6 37 6 3
16 34 RST5 7 2 MBRST5 TP19
P3P3V SR16ADDR3 A3 OUT5
SR16ADDR2 17 32 RST4 8 1 MBRST4
P3P3V A2 OUT4 RST3 MBRST3
18 29 5 4
SR16ADDR1
SR16ADDR0 19
A1
A0 DAD1000 OUT3
OUT2
OUT1
27
24
RST2
RST1
6
7
3
2
MBRST2
MBRST1 TP17 R2
R3 R4 45 22 RST0 8 1 MBRST0 1K
1K 10K DEV_ID1 OUT0
44 DEV_ID0 RP4 10
IRQZ 43 DADINTZ
EXT_ARSTZ 59 RESETZ
SR16OEZ 6 VCC2
OEZ
VOFF_RAIL7 78
54 VCC VOFF_RAIL6 73
C 68 C
P12V VOFF_RAIL5 R5
52 V12_SWL1 VOFF_RAIL4 63
51 38 C1
L1 V12_SWL0 VOFF_RAIL3 C2 C3 4.7U Z
33 10K
P12V_FLT VOFF_RAIL2 0.1U Z 0.1U Z (50V)
50 V12_3 VOFF_RAIL1 28
120 OHM 48 V12_2 VOFF_RAIL0 23
11 V12_1 VOFF 49
C4 C5 C6 C7 C8
0.1U Z 0.1U Z 0.1U Z 0.1U Z 4.7U Z
(50V) 80 47 V5REG
VBIAS_RAIL7 V5REG
71 VBIAS_RAIL6
70 VBIAS_RAIL5
61 VBIAS_RAIL4 VRST_RAIL7 76
VBIAS 40 75 C9 --> (1U--> 0.22U) for more working margin
VBIAS_RAIL3 VRST_RAIL6 0.22U M
30 65 (0805)
VBIAS_RAIL1 VRST_RAIL4
C11 C12 C10 35
0.1U Z 0.1U Z 4.7U Z VRST_RAIL2
9 VBIAS VRST_RAIL1 26
(50V) 25 VRST
VRST_RAIL0
VBIAS_SWL 8 13
VBIAS_SWL VRST
1
L2 D1
22UH MBR0540T1
C15 C13 C14
4.7U Z 0.1U Z 0.1U Z
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
VBIAS_LHI 10 12 VRST_SWL (50V)
VBIAS_LHI VRST_SWL
B B
1
7
14
20
41
46
53
55
60 L3
22UH
1
+ C16
10U
16V
2
DAD1000
A
Benq Corporation A
99.J5877.001 HT720G NA
Title
DMD BOARD

<Size> 48.J5802.S01 99.J5877.R22-C3-304-002 0
S01

5 4 3 2 1
5 4 3 2 1
P12V
P5V SSI_VDD V12A
L10
D8 RB051L-40
P12V
P5V
120 OHM P12V 1 2
D2 D3
2
C37 C38 C39 C40 C41 (3A, 40V)
1
D
1U Z 4.7U Z C42 1U Z 1U Z 4.7U Z P12V_P
1 2 1 2 C43 C44 C45 C46 C47 (4.6x2.6) D9 D
(0805) (1206) 0.1U Z (0805) (0805) (1210) 0.1U Z 0.1U Z 0.1U Z 0.1U Z 0.1U Z (ROHM) 15V,1.5W,5% C62 + C58
R30 (83.3R002.08P) 0.1U Z 10U K
3
300 BAT54SW BAT54SW (1SMB5929BT3) 35V
2
(1/8W) PUMPN2 PUMPN1 (ONSEMI)
SSI_VDD P12V TP3 TP4 TP5 (83.15R03.03D) (80.10623.141)
V12A
5
6
R31
R32
R33
R34
C59 C60 C61 4 V12A
0.1U Z 0.1U Z 0.1U Z
2
C48 C49 Q5B
0.01U K 0.01U K
3.3K
3.3K
3.3K
3.3K
D4
3
47
46
48
45
22
59
U13 7 BAT54SW
8 3
11 5
VCK5
VCK12
V5
V12
VM1
VM2
MTRCLK SCLK SWG
MTRDATA 10 SDATA 2
9 6 PUMPZ
MTRSELZ SDEN PUMPZ
5
6
7 PUMP Q5A
1
PUMP CP FDS6930A
MTRPWM 64 8
1
PWMIN CP
4
38 61 PW R35 100
R36 A IN SUM PW WH SD
37 AIN WHSD 53
2
1K AOUT 36 52 WLSD
ERRN ADUT WLSD Q6B D5
35
3
R37 ERR ERRN PV R38 100
34 ERR PV 62 7 BAT54SW
DDP3P3V 1K 33 55 VHSD 8 3
C SOUT VHSD VLSD C
VLSD 54
RSV 24 2 200 OHM
U12 RSV L11
SSI_VDD 63 PU R39 100
PU UHSD MDY1A MDY1
19 57
1
PRG UHSD
5
6
1 5 SSI_VDD 15 56 ULSD Q6A
1
NC VCC R68 PRI ULSD FDS6930A 200 OHM 20K2002004
14 PREG L12
2 4.7K SSI-32H6742T 58 RSM 4
MTRRSTZ A RSM
18 44 MDY2A MDY2 J4
NRG SGND
2
R69 3 4 PORZ 17 2 CRH C50 TP24 Q7B
GND Y NRC CRH 120P J D6 200 OHM 1
16 NREG L13 2
1K 41 SSI_AMUX 7 BAT54SW
3
TP20 AMUX R71 R72 R73 MDY3A MDY3 3
32 ISET DMUX 3 MTRDMUX 8 3 4
74LVC1G07 31 4 CCLK 10M 10M 10M
GLS CCLK TP25 2
20 26 Motor Drive
SSI_VDD RETZ GPA FDS6930A
23 RSV
1
VCMA Q7A
49 25
1
R40 PORZ GNA
2.74KF 39 29 C51 R41 RSM
PWNSB GPB 100P J 3.3K
40 PMWLSB VCMB 27
VREFIN 42 28
2XVREF VREFIN GNB R42 R43 R44 R45 R46 R47 R48
43
AGND1
AGND2
AGND3
2XVREF
VMAG
CVCO
R49 13 NC_R1206 NC_R0805 NC_R0805 NC_0805 1 1 1

2.26KF DGND
RC
12 FP
C52 (1206) (0805) (0805) (0805) (0805) (0805) (0805)
0.1U Z
51
50
21
30
60
TP23 C/A C/A

3 3
TP21 SSI_VDD
B P45 SOT-323 SOT-323 B
CVCO
1 2 1 2
TP22 A C A C
SSI_VDD
SSI_RC VMAG 1 2
R50 D7
3K R51 1N4148
(1206) C53 C54 150K
0.1U Z 330P J
(0805) C55
C56 270P J
2.2U Z C57
2700P K
SSI COLOR WHEEL DRIVE CIRCUIT
A
Benq Corporation A
99.J5877.001 HT720G NA
Title
DMD BOARD

<Size> 48.J5802.S01 99.J5877.R22-C3-304-002 0
S01

5 4 3 2 1
5 4 3 2 1
+5VA +3VA
+5VA +3VA
+V_DAC +V_DAC
OP_A[0..23] OP_A16 R14 10IN_OP_A16
OP_A17 R15 10IN_OP_A17 0
OP_A18 R16 10IN_OP_A18 R1
OP_A19 R17 10IN_OP_A19 R2
OP_A20 R18 10IN_OP_A20 51K R3 NC
OP_A21 R19 10IN_OP_A21 C11 C12 C13 C14 C15
OP_A22 R20 10IN_OP_A22 4.7U K
PWR_SAVE
OP_A23 R21 10IN_OP_A23 0.047U K 0.047U K 0.047U K 0.047U K
D D
RST_DAC R4 560
+V_DAC
48
47
46
45
44
43
42
41
40
39
38
37
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
PSAVE
RST
C16
1 36 VREF 0.1U Z J4
G0 VREF COMP C17 0
2 G1 COMP 35 6
OP_A8 R22 10IN_OP_A8 3 34 0.1U Z OUT_R R5 OUT_RED 1 11
OP_A9 R23 10IN_OP_A9 G2 IOR
4 G3 IOR 33 7
OP_A10 R24 10IN_OP_A10 5 32 OUT_G R6 0 OUT_GREEN 2 12
OP_A11 R25 10IN_OP_A11 G4 IOG
6 G5 IOG 31 8
OP_A12 R26 10IN_OP_A12 7 ADV7123 30 OUT_BLUE 3 13
OP_A13 R27 10IN_OP_A13 G6 VAA
8 G7 VAA 29 9
OP_A14 R28 10IN_OP_A14 9 U1 28 OUT_B R7 0 4 14
OP_A15 R29 10IN_OP_A15 G8 IOB
10 G9 IOB 27 10
11 BLACK GND 26 5 15
12 25
CLOCK
SYNC GND
SY NC
VAA
R8 R9 R10 2022012015
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
OP_ENABLE 75 75 75
OP_ENABLE
13
14
15
16
17
18
19
20
21
22
23
24
+V_DAC R11
10K
C C
OP_A0 R30 10IN_OP_A0

OP_A3 R33 10IN_OP_A3 +V_DAC
2
BAV99
3 3
DN1
BAV99
1
R38 10 OCLK_OUT_INPUT DN2
OCLK_OUT
OP_VSYNC R12 75 VSYNC_OUT

OP_VSYNC
75
OP_HSYNC R13 HSYNC_OUT
OP_HSYNC
B B
Optical Points
OP1 OP2 OP3 OP4 OP5 OP6 OP7
Screw Holes
1
1
5 9 5 9 5 9 5 9 5 9 5 9
4 8 4 8 4 8 4 8 4 8 4 8
3 7 3 7 3 7 3 7 3 7 3 7
2 6 2 6 2 6 2 6 2 6 2 6
A
H1 H2 H3 H4 H5 H6 Benq Corporation A
HOLE-V8 HOLE-V8 HOLE-V8 HOLE-V8 HOLE-V8 HOLE-V8
99.J5877.001 HT720G NA
Title
DMD BOTTOM BOARD

<Size> 0
48.J5824.S02 S02 99.J5877.R22-C3-304-003
Date: Wednesday, January 15, 2003 Sheet 1 of 2

5 4 3 2 1
5 4 3 2 1
OP_A[0..23]
J1 J2
1 1 2 2 1 1 2 2
OP_A23 3 4 OP_A22 OP_A23 3 4 OP_A22
3 4 3 4
5 5 6 6 5 5 6 6
OP_A21 7 8 OP_A20 OP_A21 7 8 OP_A20
7 8 7 8
9 9 10 10 9 9 10 10
OP_A19 11 12 OP_A18 OP_A19 11 12 OP_A18
11 12 11 12
D 13 13 14 14 13 13 14 14 D
OP_A17 15 16 OP_A16 OP_A17 15 16 OP_A16
15 16 15 16
17 17 18 18 17 17 18 18
OP_A15 19 20 OP_A14 OP_A15 19 20 OP_A14
19 20 19 20
21 21 22 22 21 21 22 22
OP_A13 23 24 OP_A12 OP_A13 23 24 OP_A12
23 24 23 24
25 25 26 26 25 25 26 26
OP_A11 27 28 OP_A10 OP_A11 27 28 OP_A10
27 28 27 28
29 29 30 30 29 29 30 30
OP_A9 31 32 OP_A8 OP_A9 31 32 OP_A8
31 32 31 32
33 33 34 34 33 33 34 34
OP_A7 35 36 OP_A6 OP_A7 35 36 OP_A6
35 36 35 36
37 37 38 38 37 37 38 38
OP_A5 39 40 OP_A4 OP_A5 39 40 OP_A4
39 40 39 40
OP_A3 43 44 OP_A2 OP_A3 43 44 OP_A2
43 44 43 44
45 45 46 46 45 45 46 46
OP_A1 47 48 OP_A0 OP_A1 47 48 OP_A0
47 48 47 48
49 49 50 50 49 49 50 50
OCLK_OUT OCLK_OUT (CLK_OUT) 51 52 OP_HSYNC OP_HSYNC OCLK_OUT (CLK_OUT) 51 52 OP_HSYNC
51 52 51 52
53 53 54 54 53 53 54 54
OP_ENABLE OP_ENABLE (OP_ENABLE) 55 56 OP_VSYNC OP_VSYNC OP_ENABLE (OP_ENABLE) 55 56 OP_VSYNC
55 56 55 56
57 57 58 58 57 57 58 58
SDA 59 60 LAMPLITZ (For HD2) SDA 59 60 LAMPLITZ (For HD2)
59 60 59 60
61 61 62 62 61 61 62 62
SCL 63 64 DLP_RESETZ SCL 63 64 DLP_RESETZ
63 64 63 64
65 65 66 66 65 65 66 66
POWER 67 68 POWERON Ballast_Ctrl 67 68 POWERON
67 68 67 68
69 69 70 70 69 69 70 70
C 71 72 PWRGOOD (For HD2) 71 72 PWRGOOD (For HD2) C
71 72 +3VA 71 72 +3VA
73 73 74 74 73 73 74 74
+3VS 75 76 +3VA 75 76
75 76 75 76
77 77 78 78 77 77 78 78
79 79 80 80 79 79 80 80
81 81 82 82 81 81 82 82
+5VS 83 84 83 84
83 84 83 84
85 85 86 86 85 85 86 86
87 88 SYNCVALID (For HD2) 87 88 SYNCVALID (For HD2)
87 88 Ballast_Ctrl +5VA 87 88 +5VA
89 89 90 90 89 89 90 90
+12VA 91 92 +12VA 91 92
91 92 +5VA 91 92
93 93 94 94 93 93 94 94
95 95 96 96 95 95 96 96
97 97 98 98 97 97 98 98
99 99 100 100 99 99 100 100
20C1001100 20C1001100
L4
+3VA
3VA
500 OHM
1
+ C7 (1206)
C8 22U
B 0.1U K 35V B
2
+5VS L3 J3
5VS 3VA 7 1 3VA
(1206) 7 1
500 OHM
1
8 2 3VS
C6 + C5 8 2
0.1U K 22U 9 3 5VS
35V 9 3
2
10 4 5VA
10 4
11 5 POWER
11 5 L1 +12VA
L2
+5VA 12 6 12VA
5VA 12 6
500 OHM
1
500 OHM (1206) 20E1006206
1
(1206) + C1 C2
C4 + C3 22U 0.1U K
0.1U K 22U 35V
2
35V
2
A
L5
Benq Corporation A
+3VS Project Code Model Name OEM/ODM Model Name
3VS NA
99.J5877.001 HT720G
500 OHM
1
Title
+ C9 (1206) DMD BOTTOM BOARD
C10 22U
0.1U K 35V Size PCB P/N PCB Rev. Document Number R ev.
2
<Size> 0
48.J5824.S02 S02 99.J5877.R22-C3-304-003
Date: Wednesday, January 15, 2003 Sheet 2 of 2

5 4 3 2 1
5 4 3 2 1
120-Pin B2B Connectors
Graphics_ADC_AD9883
D_INA[0..23]
D_INA[0..23] D_INA[0..23]
D D _VSYNC D
D_VSYNC D_HSY NC D_VSYNC
Y /R D_HSYNC DIN_CLK D_HSYNC
PB/G Y/R DIN_CLK DIN_CLK
PR/B PB/G Trigger/3D/Thermal/RS232
PR/B +5VS +12VA
DVI_PDO +5VS
DVI_PDO
VSYNC
VSYNC
H SYNC HSYNC SDA
+5V_AD +3VD SDA SCL SDA IR
SCL SCL IR IR +12VA
+3VD
+5V_AD
DVI_CLK
TRIGGER
TRIGGER TRIGGER
DVI_CLK
3_Graphics ADC AD9883 CPU_TXD0
Graphics_Inputs
DVI_PDO
CPU_RXD0
Y/R
VSYNC
HSYNC
PB/G
PR/B
DVI
PC_VS
PC_VS PC_HS PC_VS
DVI_CLK
DVI_PDO
C PC_HS PC_GREEN PC_HS C
+5V_AD PC_GREEN PC_RED PC_GREEN
PC_RED PC_BLUE PC_RED
+5V_AD PC_BLUE PC_BLUE SPAREI
DVI_SCDT SPAREO
MUX_SEL_Q MUX_SEL_Q DVI_SCDT DVI_SCDT MUX_SEL_Q MUX_SEL_Q
+5V_MUX +5V_AD
+3VD D_HSYNC
+5V_MUX YpYcG D_VSYNC
YpYcG +5V_AD
D_INA[0..23] 6_Trigger/3D/Thermal/RS232
PbCbB
PbCbB +3VD
PrCrR DVI_ACTDATA
PrCrR DVI_ACTDATA DVI_ACTDATA
O_COMP_CR
O_COMP_CB
O_COMP_Y
8_DVI INPUT&RECEIVER
MUX_SEL_P
L_Y_G
L_Pb
L_Pr
MUX_SEL
O_COMP_CR
O_COMP_CB
1_Graphics Inputs
O_COMP_Y
L_Y_G
L_Pb
L_Pr
Video Inputs Video Decoder SAA7118E

DI_IN[2..9]
YpYcG DI_IN[2..9] DI_27M_CLK DI_IN[2..9]
O_COMP_Y
L_Y_G
O_COMP_CB
O_COMP_CR
L_Pb
L_Pr
B DI_27M_CLK DI_27M_CLK B
PbCbB D I_VSYNC
DI_VSYNC DI_HSY NC DI_VSYNC
MUX_BUFFER MUX_BUFFER Y_RCA PrCrR DI_HSYNC DI_HSYNC
Y1 Y1 SDA
Cb_RCA SDA
CB1 CB1 SCL
+5V_MUX Cr_RCA SCL
+5V_AD CR1 COMPOSITE CR1
COMPOSITE COMPOSITE
+5V_MUX Y
Y Y RESET_DEC
C RESET_DEC RESET_DEC
C C
+5V_AD +5V_AD
2_Video Inputs +3VD CPU_TXD0
CPU_RXD0
+3VD
+5V_AD
+5V_AD +12VA
5_Video Decoder SAA7118E MUX_SEL +3VD +5VS
MUX_SEL_P
A
MUX_BUFFER MUX_BUFFER
+3VD
+5VS
Benq Corporation A
CPU_RXD0
CPU_TXD0

MUX_SEL HT720G
+5V_AD 99.J5877.001 NA
MUX_SEL_P Title
+12VA CONNECTOR BOARD

7_120Pin B2B Connector <Size> 48.J5810.S02 S02 99.J5877.R22-C3-304-004 0
Date: Monday, February 17, 2003 Sheet 1 of 8

5 4 3 2 1
5 4 3 2 1
-5V_RGB -5V_RGB
C135 U16 +5V_AD
+
10UF/16 1 NC 8
V+
2 1CAPP+ 2 CAP+ OSC 7
3 GND LV 6
CAPP- 4 CAP- 5 C22 C23 C24 +5V_AD
VOUT
2
0.1UF 0.1UF 0.1UF
+5V_AD ICL7660A C136
L_Y_G
10UF/16
+
1
L_Pb
2
D1 D2 D3
BAV99 BAV99 BAV99 C18 C19
L_Pr -5V 0.1UF 0.1UF
D D
3 3 3
-5V
C1 U1 +5V_AD
+
10UF/16 1 8
1
1
NC V+
J1 2 1CAP+ 2 CAP+ OSC 7
3 GND LV 6
CAP- 4 5 C15 C16 C17
CAP- VOUT
2
6 L2 R112 18 0.1UF 0.1UF 0.1UF
GND Y_ Y_G Yp YcG ICL7660A C4
1 1 1 2 YpYcG
10UF/16
+
FCB3216K
1
7 GND L3 R113 18
2 Pb_Cb_B 1 2 PbCbB
2 PbCbB
FCB3216K
8 +5V_MUX
GND L4 R114 18 L1
3 Pr_Cr_R 1 2 +5V_AD Z1000/100MHZ +5V_MUX
3 PrCrR
FCB3216K +5V_AD
9 GND L5 FCB3216K C2 C3 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
4 HS_B 1 2 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
4 BNC_HS
10 GND
For AD8183
5 VS_B 1 2
5 BNC_VS
L6 FCB3216K
BNC_5_IN_1
1
C137 C138 C139 R1 R2 R3 R4 R5
0.1UF 0.1UF 0.1UF C140 C141 C142 56 56 56 4.7K 4.7K
0.1UF 0.1UF
2
0.1UF
C +5V_MUX C
+5V_AD
+5V_MUX
2
D4 D5
BAV99 BAV99
U2
3 3 O_R
1 IN0A VCC 24
2 DGND OE 23
3 22 MUX_SEL
O_G IN1A SEL A/B MUX_SEL
4 GND VCC 21
5 20 OUT_Y/R 1R6 752
Y/R
1
O_B IN2A OUT0

6 VCC VEE 19
7 18 OUT_PB/G 1R7 752
VEE OUT1 PB/G
O_COMP_CR 8 IN2B VCC 17
9 16 OUT_PR/B 1R8 752
GND OUT2 PR/B
10 15 +5V_AD
O_COMP_CB IN1B VEE
11 GND DVCC 14
O_COMP_Y 12 IN0B VCC 13
1
-5V
AD8183
R9
1K
2
This MUX is for seletion between
BNC_YPbPr and DSUB_BNC_RGB
+5V_MUX
U3
L_Y_G 1 IN0A VCC 24
2 DGND OE 23
3 22 MUX_SEL_P
L_Pb IN1A SEL A/B MUX_SEL_P
4 GND VCC 21
B 5 20 B
L_Pr IN2A OUT0 O_G
6 VCC VEE 19
7 VEE OUT1 18 O_B
PC_RED 8 IN2B VCC 17
9 GND OUT2 16 O_R
10 15 +5V_AD
PC_BLUE IN1B VEE
11 GND DVCC 14
PC_GREEN 12 IN0B VCC 13
1
AD8183 -5V_RGB
R10
10K
2
This MUX is for seletion between
BNC-RGB and DSUB_RGB
+5V_MUX
C25
0.1UF
U4
7 GND VCC 14
2 3 O_HS 1R11 752
BNC_HS A0 O0 HSY NC
BNC_VS 5 A1 O1 6
PC_HS 12 A2 O2 11
9 8 O_VS 1R12 752
PC_VS A3 O3 V SYNC
1 OE0 OE2 13
4 10 MUXPP 1R73 0 2
OE1 OE3 MUX_SEL_Q
+5V_MUX
74126(73.74126.0HB)
R13
5.1K
1:BNC-HV
OUT
A
SEL_HV
0:DSUB-HV A
OUT
3
R14 1K Q1
MUX_SEL_P
SEL 1 2N3904
Benq Corporation
2
R15
10K 99.J5877.001 HT720G NA
Title
2N3904 CONNECTOR BOARD
3_C Size PCB P/N P CB Rev. Document Number Rev.

<Size> 48.J5810.S02 S02 99.J5877.R22-C3-304-004 0

1_B 2_E Prepared By Reviewed By Approved By
5 4 3 2 1
5 4 3 2 1
L39
42 OHM
+5V_AD
L40
42 OHM
D11
J3 BAV99
RCA-JACK 1 2 +5V_AD
The voltage level of CB/CR is
2
D L41 42 OHM D
+0.35~-0.35 , add one diode
3
L13 +5V_AD
OUT_COMP 1R21 182
1 1 2 COMPOSITE to prevent uncertain 'ON'
RCA_IN
error
1
FCB3216K
(open)
2
D12 D13 D14
C144 R22 BAV99 BAV99 BAV99
C143 0.1UF 56
0.1UF 3 3 3
2
(open) D15
BAV99 D16
1 2 BAV99
+5V_AD ERRORON1 2 1
1
3
L14 ERRORON2
3
SVIDEO_Y1 2 OU T_YY 1R23 18 2
Y
1
FCB3216K
(open) L15
1
3 Cr 1 2 CRR 1R24 182
3 CR1
1
5 C145 C146
5
1
0.1UF 0.1UF FCB3216K
6 6 (open) R25
56 R26
4 4
C149 C150 56
2
J5
2
0.1UF 0.1UF
2
(open) (open)
2
J4 2 1
S-VIDEO D17 2 1
C BAV99 C
1 2 L16 R27
+5V_AD Cb CBB 182
4 4 3 3 1 2 1 CB1
3
L17 18 FCB3216K
SVIDEO_C1 2 OUT_CC 1R28 2 C
1
6 6 5 5
FCB3216K
1
C151 C152 R29
(open) (open) 0.1UF 0.1UF 56
R30 RCA 3 IN 1
(open) (open)
2
C147 C148 56
0.1UF 0.1UF
2
+5V_AV L18
YC 1 2 Y CC 1R31 182
Y1
FCB3216K
1
U5
Y CC R124 0 YCC_ U5 1 24
IN0A VCC R35
2 DGND OE 23
CBB R125 0 CBB_U5 3 22 C153 C154 56
IN1A SEL A/B MUX_BUFFER 0.1UF 0.1UF
4 21
2
GND VCC
CRR R126 0 CRR_U5 5 IN2A OUT0 20 MUX_YP 1R36 02
O_COMP_Y (open) (open)
6 VCC VEE 19
7 18 MUX_PB 1R37 02
VEE OUT1 O_COMP_CB
L_Pr 8 IN2B VCC 17
9 16 MUX_PR 1R38 02
B GND OUT2 O_COMP_CR B
10 15 +5V_AD
L_Pb IN1B VEE
11 GND DVCC 14
1
1
L_Y_G 12 IN0B VCC 13
AD8183 -5V_AV R70 R71 R72 R39
56 56 56 1K
2
This MUX is BUFFER of (open) (open)

Composite and (open)
S-Video
-5V_AV
+5V_MUX
Open if -5V is not necessary +5V_AV
+5V_MUX
-5V_AV L19
Z1000/100MHZ +5V_AD
C26 U6 +5V_AD
1
1
+
+ +
Benq Corporation
10UF/16 1 NC 8
V+
2 1CAPP+ 2 CAP+ OSC 7
A 3 GND 6 C29 C30 C31 C27 C28 C32 C33 C34 C35 C36 C37 A
CAPP- LV 0.1UF 0.1UF 0.1UF 10UF/16 10UF/16 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF Project Code
4 CAP- 5 Model Name OEM/ODM Model Name
2
VOUT
2
99.J5877.001 HT720G NA
ICL7660A C38
10UF/16
+ For AD8183 Title
CONNECTOR BOARD
1

<Size> 48.J5810.S02 S02 99.J5877.R22-C3-304-004 0

5 4 3 2 1
5 4 3 E1 TP4
1
TP2
2
E1 1
TP1 1 1
E1 1 TP6
TP3 1 E1 TP8 E1
E1 1
TP5 1 1 TP10
E1 E1 E1
TP7
E1
1 (open) (open) (open) (open) 1 TP12
TP14
1
TP9 1 E1
E1 1 TP16
1
TP11 1 E1
E1 C N1 C N2 C N3 C N4
TP13 1 22P 22P 22P 22P
D_INA[0..23]
E1
8
TP15 1
E1
D 1
LP1 120 OHM
8D_ INA8
D
2 7D_ INA9
3 6 D_INA10
4 5 D_INA11
1 8 D_INA12
2 7 D_INA13
3 6 D_INA14
4 5 D_INA15
AD_G0
AD_G1
AD_G2
AD_G3
AD_G4
AD_G5
AD_G6
AD_G7
LP2 120 OHM LP4 120 OHM
AD_R0 1 8 D_INA16
AD_R1 2 7 D_INA17
AD_R2 3 6 D_INA18
AD_R3 4 5 D_INA19
AD_R4 1 8 D_INA20
AD_R5 2 7 D_INA21
AD_R63 6 D_INA22
AD_R7
4 5 D_INA23
LP3 120 OHM

TP17 1 DATACK
AD_CLK
E1
HSOUT 1R41 332 D _HSYNC
D_ HSYNC
TP19
TP18
1
E1 SOGOUT E1
VSOUT 1R42 332 D_VSY NC
D_VSYNC
1
C39
Y /R 47NF AD_RIN
Y/R
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
C40
HSOUT
SOGOUT
VSOUT
GND
VDD
VDD
R0
R1
R2
R3
R4
R5
R6
R7
DATACK
VDD
GND
GND
VD
GND
TP20 1 60 0.1UF
GND GND
2 G7 VD 59
E1 3 58 REF_BYPASS+3VB_A2D
G6 REF BYPASS SDA
4 G5 SDA 57 SDA
5 56 SCL
C C41 6
G4 SCL
55
SCL
C
1
PB/G 47NF AD_ GIN G3 A0

PB/G 7 G2 RAIN 54
TP21 TP22 8 G1 GND 53
9 G0 VD 52
E1 E1 10 U7 51 +5V_ADDVI
GND AD9883 VD
+3VD 11 VDD GND 50
12 49 R116 0
C42 B7 SOGIN
13 48
1
P R/B 47NF AD _BIN B6 GAIN

PR/B 14 B5 GND 47
15 B4 VD 46
16 B3 VD 45
17 44 R115 0 U22
B2 GND U22_ADCLK
HSYNC 18 B1 BAIN 43 AD_CLK 1 IN0A VCC 24
19 B0 VD 42 2 DGND OE 23
MIDSCV
HSYNC
COAST
CLAMP
VSYNC
20 GND GND 41 3 IN1A SEL A/B 22 DVI_PDO
(open) 4 21 L30 30 OHM
GND
GND
GND
GND
GND
GND
GND
VDD
VDD
PVD
PVD
FILT
GND VCC OUTDINCLK
VD
VD
VD
5 IN2A OUT0 20 DIN_CLK
R43 R44 R45 6 19
VCC VEE
7 18
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VEE OUT1
1
8 17 C156 C155
220 220 220 C N6 IN2B VCC 22P J 22P J
9 GND OUT2 16
C43 0.1UF 22P 10 15 <Spec> <Spec>
IN1B VEE
For AD8185 11 14
8
R117 0 U22_DVICLK 12 GND DVCC
13
R=75 MIDSCV
DVI_CLK IN0B VCC
C44 LP6 120 OHM AD8183
1NF AD_SOGIN AD_B0 +3VC_A2D 1 8 D_ INA0 +5V_AD
AD_B1 2 7 D_ INA1
AD_B2 3 6 D_ INA2
1
TP23 R46 AD_B3 4 5 D_ INA3 R118 0

1K AD_B4 1 8 D_ INA4
E1 AD_B5 2 7 D_ INA5
AD_B6 3 6 D_ INA6
AD_B7 4 5 D_ INA7 C178
2
0.1U Z
1
LP5 120 OHM

V SYNC
5
TP24
22P
C N5
H _SYNC 1
1
1 2FLT
TP25
4
B R48
51K
R47
2.7K
C45
82NK 16V
1 E1
TP26
-5V_ADDVI
B
F ILT
(open)
2
C46 1 E1
8200P K -5V_ADDVI
TP27 +5V_AD
1 E1
U23
TP28 C188
1 NC V+ 8
1 E1 2 1 U23_CAP 2 7
CAP+ OSC
+
3 GND LV 6
TP29 U23_CAP- 4 CAP- VOUT 5
1 E1 10U
2
16V ICL7660S 5V C187
TP30 C189 0.1U Z
+
1 E1 10U
16V
1
E1
-5V_ADDVI +5V_ADDVI
U8 C179 C180 C181 C182 C183 C184 C185 C186

+3VD +5V_AD LD1117/SOT +3VB_A2D 0.1U Z 0.1U Z 0.1U Z 0.1U Z 0.1U Z 0.1U Z 0.1U Z 0.1U Z
+3VD 3 VIN VOUT 2
GND
C47 C48 C49 C50 C51 C52 C53

+ C55 C56 C57 C58 C59 C60 C61 C62 C63 C64
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 4.7UF/16 C54 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
1
10UF/16
2
A A
+5V_AD U9
LD1117/SOT +3VC_A2D
Benq Corporation
+5V_AD
3 VIN VOUT 2
99.J5877.001 HT720G NA
GND
C65
+C66 C67 C68 Title
CONNECTOR BOARD
4.7U/16V 10UF/16 0.1UF 0.1UF
1

2
<Size> 48.J5810.S02 S02 99.J5877.R22-C3-304-004 0

5 4 3 2 1
5 4 3 2 1
TP31 TP32 TP33 TP34

E1 E1 E1 E1
D D
1
SY IN S_Y IN
Y
SDA
C69 SCL
SCL
47NF
INT_A 1 TP35
E1
RESET R49 33
RESET_DEC
TP36 1 RTS0 LLC2 1 TP37
E1 E1
TP38 1 RTS1 LLC 1 TP39
E1 E1
TP40
E1
M12
M10
N14
N13
D13
C14
C13
C12
N11
N10
P13
B14
B13
B12
A13
A12
P11
P12
P10
B11
L10
C6
D6
N3
N2
N1
C4
C3
N9
N4
N5
A5
B5
B6
P2
B2
P9
P5
P4
TP41 TP42 TP43 TP44 TP45
E1 E1 E1 E1 E1
XTRI
TDI
TMS
TRST
TDO
TCK
TEST19
TEST18
TEST17
TEST16
TEST15
TEST14
TEST13
TEST12
TEST11
TEST10
TEST9
TEST8
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1
AMXCLK
INT_A
AMCLK
RTCO
RTS1
RTS0
ALRCLK
ASCLK
SDA
SCL
CE
RES
LLC2
LLC
1
S_CIN
C
1
C70
47NF M13 D8 XRV R50 33
FSW XRV DI_VSYNC
J2 C7 XRH R51 33
AI11 XRH DI_HSYNC
K1 A6 XRDY
AI12 XRDY XDQ
K2 AI13 XDQ B7
AI1C L3 A7 XCLK 2R52 33 1 DI_27M_CLK
AI14 XCLK DI_27M_CLK
C71 47NF AI1D K3 A8 XPD0
AI1D XPD0 XPD1
C2 AGND XPD1 B8
G4 A9 XPD2
AI21 XPD2 XPD3
G3 AI22 XPD3 B9
H2 A10 XPD4
AI2C AI23 XPD4 XPD5
J3 AI24 XPD5 B10
C72 47NF AI2D H1 A11 XPD6
AI2D XPD6 XPD7 TP46 TP47 TP48 TP49 TP50 TP51 TP52 TP53
E3 AI31 XPD7 C11
F2 D14 E1 E1 E1 E1 E1 E1 E1 E1
AI32 HPD0
F3 AI33 HPD1 E11 DI_IN[2..9]
AI3C G1 E13
TP54 C73 47NF AI3D AI34 HPD2
F1 E12
1
E1 AI3D HPD3 D I_IN2
L2 E14 1 8
C B1
D2
AGNDA
AI41
AI42 U10
HPD4
HPD5
HPD6
F13
F14
2
3
7
6
D I_IN3
D I_IN4
D I_IN5
C
D1 G13 4 5
1
AI4C AI43 SAA7118E HPD7

PrCrR E1 AI44 ITRI L12
C75 47NF AI4D D3 K13 RP7 47_RP
C74 TP55 EXMCLR AI4D IGP1
1 P3 EXMCLR IGP0 L14
47NF E1 M1 K14 1 8 D I_IN6
AOUT IGPV D I_IN7
M2 VSSA0 IGPH K12 2 7
J4 N12 3 6 D I_IN8
VSSA1 ITRDY D I_IN9
H3 VSSA2 IDQ L13 4 5
+3VE E4 M14
VSSA3 ICLK RP8 47_RP
C1 VSSA4 IPD0 G14
M3 VDDA0 IPD1 G12
K4 VDDA1 IPD2 H11
TP56 H4 H14
E1 VDDA2 IPD3
F4 VDDA3 IPD4 H13
D4 VDDA4 IPD5 J14
L1 VDDA1A IPD6 J13
J1 K11
1
CR1_IN VDDA2A IPD7

C R1 G2 VDDA3A CLKEXT N6
E2 VDDA4A ADP0 N8
C76
VDD(xtal)
VSS(xtal)
VDDD10
VDDD12
VDDD11
VDDD13
VSSD10
VSSD12
VSSD11
VSSD13
47NF
VDDD2
VDDD4
VDDD6
VDDD8
VDDD1
VDDD3
VDDD5
VDDD7
VDDD9
XTOUT
VSSD2
VSSD4
VSSD6
VSSD8
VSSD1
VSSD3
VSSD5
VSSD7
VSSD9
XTALO
XTALI
ADP8
ADP7
ADP6
ADP5
ADP4
ADP3
ADP2
ADP1
M11
D7
D10
F11
J11
L5
L9
C8
C10
F12
J12
M5
M9
D5
D9
D11
G11
L4
L8
L11
C5
C9
D12
H12
M4
M8
A4
B3
A2
A3
B4
P6
M6
L6
N7
P7
L7
M7
P8
TP57
E1
1
PbCbB +3VD +3VD

C77
47NF
XTALI
XTALO
B B
VDD_XTAL
TP58
E1
I2C BUS SLAVE ADDRESS: R53 820K
0x42 - W,0x43 - R
1
2
X1 24.576MHZ
3 1 L20
1
CB 1_IN NC_L1206
CB1
C79
4
C78 L21 C80 22PF
2
47NF 22PF L22
Z1000/100MHZ XTALA
XHELP
Z1000/100MHZ
C81
S OG_Y 0.1UF C83
NC_C0603
TP59 C82
E1 47NF
1
YpYcG
C84
47NF U11 L23
+5V_AD LD1117/SOT Z1000/100MHZ +3VE
3 2 3.3V_7118 ANALOG SAA7118E
+5V_AD VIN VOUT
GND
1
C85
+ + C88 C89 C90 C91 C92 C93 C94 C95 C96
4.7UF/16 C86 C87 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
1
SOG_Y_IN 10UF/16 10UF/16

2
TP60 C97
E1 47NF
+3VD
1
Y_ IN DIGITAL SAA7118E - CORE

Y1 +3VD
A C98
47NF C99
0.1UF
C100
0.1UF
C101
0.1UF
C102
0.1UF
C103
0.1UF
C104
0.1UF
A
TP61 SOG_RCA
Benq Corporation
E1
C105 99.J5877.001 HT720G NA
47NF DIGITAL SAA7118E - PERIPHERAL CELLS
Title
CONNECTOR BOARD
1
RAC_IN
COMPOSITE
C107 C108 C109 C110 C111 C112 C113 Size PCB P/N P CB Rev. Document Number Rev.
C106 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
<Size> 48.J5810.S02 S02 99.J5877.R22-C3-304-004 0
47NF

5 4 3 2 1
5 4 3 2 1
+12VA
L24 Q2 J6
F1
1 2 VOUT_TRIGGER 1 8 DR TOUT_12V 1
+5VS +12VA S D
2 S D 7 2
VCC_IR R54 47 3 6 PICOFUSE 3
S D
1
FCB3216K
+ C114
4 G D 5 69.42001.021 R74
+ SCD437
D C117 C118 C119
10UF/25
R55
G Si4431DY
84.04431.037
10K C115
10UF/25
C116
0.1UF D
2
0.1UF 4.7UF/16 0.1UF 47K
U12
VCC 3
2 GG
GND
3
1 R56 1K Q3
VOUT
2
TRIGGER TRIG 1 2N3904
TRIGGER
FM6038TM2
FCB3216K
L27
1:TURN ON
0:TURN OFF
2
R57
FRONT_IR
10K
1
2N3904
3_C
1_B 2_E
R58 130
IR
C C
+5VS
J9
1
2
IR 3
20.D0049.103
TX1
RX1
J7
+5VS 1
1
+5VS 2 2
R59 NC_R1206 3
3
1 2 4 4
C121 C122
0.1UF R60 NC_R1206
C123 0.1UF D18 D19
232_C1-
232_C1+
1 2
B 0.1UF
U14
R61 150/1206 2213008001 27V 27V B
1 2
1 C1+ VCC 16
RSV+ 2 15 RXX1
V+ GND T1OUT R62 150/1206 TXX1
3 C1- T1OUT 14
C124 232_C2+ 4 13 R1 IN 1 2
0.1UF 232_C2- C2+ R1IN RX D20 D21
5 C2- R1OUT 12
RSV- 6 11 27V 27V
V- T1IN
7 T2OUT T2IN 10
C125 8 9
0.1UF R2IN R2OUT
SP232
C126 C127
R68 R69 47PF/50 47PF/50
+5VS 1K 1K
R63
1K
Benq Corporation
A Project Code Model Name OEM/ODM Model Name A
99.J5877.001 HT720G NA
CPU_TXD0 Title
CPU_TXD0
CONNECTOR BOARD
CPU_RXD0R64 Size PCB P/N PCB Rev. Document Number R ev.

CPU_RXD0
100 <Size> 48.J5810.S02 S02 99.J5877.R22-C3-304-004 0

5 4 3 2 1
DI_IN[2..9]
D_INA[0..23]
Optical Points
D D
J8
61 61 1 1 DVI_SCDT
62 2 OP8 OP9 OP10 OP11 OP12 OP13 OP14 OP15 OP16
TRIGGER 62 2
63 3 OP OP OP OP OP OP OP OP OP
63 3
MUX_SEL_P 64 64 4 4
65 65 5 5 IR
CPU_RXD0 66 66 6 6
67 67 7 7
CPU_TXD0 68 68 8 8
69 69 9 9 MUX_SEL
70 10 +5VS
MUX_BUFFER 70 10
71 71 11 11 +5VS
D_HSYNC 72 72 12 12
73 73 13 13 D_VSYNC
74 14 C128
DIN_CLK 74 14 D_INA23 0.1UF
75 75 15 15
D_INA21 76 16 D_INA22 H1 H2
2
D_INA20 76 16 HOLE-V8 HOLE-V8
77 77 17 17
78 18 D_INA19
D_INA17 78 18 D_INA18
79 79 19 19 1 1
D_INA16 80 20
80 20 D_INA15
81 81 21 21
D_INA13 D_INA14
C 82 82 22 22
C
6
D_INA12 83 23
83 23 D_INA11
84 84 24 24
D_INA9 85 25 D_INA10
D_INA8 85 25
86 86 26 26
87 27 D_INA7
D_INA5 87 27 D_INA6
88 88 28 28
D_INA4 89 29 H3
89 29 D_INA3 HOLE-V8 H4
90 30
2
D_INA1 90 30 D_INA2 HOLE-V8
91 91 31 31
D_INA0 92 32
92 32
93 93 33 33 DVI_PDO 1 1
94 94 34 34
95 95 35 35 DVI_ACTDATA
SCL 96 96 36 36
6
97 97 37 37 SDA
DI_IN8 98 38
98 38 DI_IN9
99 99 39 39
DI_IN6 100 40
100 40 DI_IN7
101 101 41 41
DI_IN4 102 42 H5
102 42 DI_IN5 HOLE-V8
103 103 43 43
DI_IN2 104 44 H6
2
104 44 DI_IN3 HOLE-V8
105 105 45 45
RESET_DEC 106 106 46 46
107 107 47 47 DI_VSYNC 1 1
DI_HSYNC 108 108 48 48
109 49 SPA8 1R65 NC_R0603
2
109 49 SPAREI
DI_27M_CLK 110 110 50 50
6
111 51 SPA9 1R66 02
B SPAREO 1R67 NC_R0603
2 SPA7 112
111
112
51
52 52
MUX_SEL_Q
B
113 113 53 53
114 114 54 54
+5V_AD L25 115 55
5VA 115 55 H7
+5V_AD 1 2 116 116 56 56
117 57 HOLE-V8
FCB3216K 117 57
118 58
5
118 58
1
C129
+C130 C131
119 119 59 59
120 120 60 60
0.1UF 10UF/16 0.1UF
1
2
AMP 120P D0.8
9
+5V_AD U15
LD1117/SOT +3VD
L26 +12VA
3 VIN VOUT 2 +3VD
12VA 1 2
GND
+12VA
FCB3216K
1
C132 C133
0.1UF C134 0.1UF
Benq Corporation
10UF/16
A Project Code Model Name OEM/ODM Model Name A

99.J5877.001 HT720G NA
Title
CONNECTOR BOARD

<Size> 48.J5810.S02 S02 99.J5877.R22-C3-304-004 0

5 4 3 2 1
+5V_AD +3VD
+5V_AD +3VD
R122 R123
4.7K 4.7K
1
R120 R121
4.7K 4.7K
DVI_SCL 2 3 DVI_SCL3V
1
Q5
DVI_SDA 2 3 DVI_SDA3V
D
BSN20 D
Q4
BSN20
LP7
120 OHM
D_INA[0..23]
R1 0 5 4 D_INA23
DVI_ACTDATA
6 3 D_INA22
7 2 D_INA21
R87 33 8 1 D_INA20
DVI_CLK 5 4 D_INA19
6 3 D_INA18
7 2 D_INA17
D_VSYNC R2 0 8 1 D_INA16
+3VD LP8 120 OHM

D_ HSYNC R3 0
D VI_RED7
D VI_RED6
D VI_RED5
D VI_RED4
D VI_RED3
D VI_RED2
D VI_RED1
D VI_RED0
+5V_AD +3VD
DVIICLK
+5V_AD
R103
0
R105
0
(open)
2
2
D22 D23 D24 D25 D26 D27
(open)
3 BAV99 3 BAV99 3 BAV99 3 BAV99 3 BAV99 3 BAV99
R104
0
J10 R106
(open)
1
1
0
(open)
CTL2
CTL1
D2- LP9 120 OHM
1 DVI_GREEN7 D_INA15
9 D1- 5 4
D0- DVI_GREEN6 6 3 D_INA14
17 DVI_GREEN5 D_INA13
2 D2+ 7 2
C D1+ DVI_GREEN4 8 1 D_INA12 C
10
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
18 D0+
+5V_EDID D38
3 +5V_AD 1N4148
HSYNC
VSYNC
CTL3
CTL2
CTL1
QO1
QO0
DE
OGND
ODCK
OVCC
GND
VCC
QE23
QE22
QE21
QE20
QE19
QE18
QE17
QE16
OVCC
OGND
QE15
QE14
11
19 (open)
4 LP10 120 OHM
12 1 2 51 QO2 QE13 25
R79 R80 R81 R82 R83 R84 +5V_EDID 52 24
20 51K 4.7K 75 75 75 4.7K QO3 QE12 DVI_GREEN3 D_INA11
5 53 QO4 QE11 23 5 4
54 22 DVI_GREEN2 6 3 D_INA10
13 QO5 QE10 DVI_GREEN1 D_ INA9
21 55 QO6 QE9 21 7 2
DVI_SCL L34 D37 56 20 DVI_GREEN0 8 1 D_ INA8
6 PC_5V PC_5VIN QO7 QE8 LP11 120 OHM
14 1 2 57 OVCC OGND 19
58 18 DVI_BLUE7 5 4 D_ INA7
22 42 OHM 1N4148 OGND OVCC DVI_BLUE6 D_ INA6
7 DVI_SDA 59 QO8 QE7 17 6 3
1
15 L28 QO9 QE6
42 OHM IDCK+ + C174 61 15 DVI_BLUE4 8 1 D_ INA4
23 PC_V 10U C175 QO10 U17 QE5
8 PC_VS 62 QO11 QE4 14
HOT_PLUG 16V 0.1U Z 63 SII151B 13 DVI_BLUE3 5 4 D_ INA3
2
16 QO12 QE3 DVI_BLUE2 D_ INA2
24 IDCK- 64 QO13 QE2 12 6 3
L29 42 OHM QO14 QE1 DVI_BLUE0 D_ INA0
66 QO15 QE0 10 8 1
P C_R PC_RED 67 9
C1 PC_B VCC PDO LP12 120 OHM
C3 PC_BLUE 68 GND SCDT 8 DVI_SCDT
69 7 SG_OUT
C5 L31 QO16 STAG_OUT DVI_PDO
P C_H L33 42 OHM 42 OHM L32 42 OHM PC_HS 70 6
C4 PC_G QO17 VCC
C2 PC_GREEN 71 QO18 GND 5
72 4 10K R98
QO19 PIXS
73 QO20 ST 3
74 QO21 PD 2
2021008024 +5V_AD HS_DJTR R101 0
EXT_RES
75 QO22 HS-DJTR 1 RESETZ_DVI
(open)
OCK_I
OGND
OVCC
AGND
AGND
AGND
AGND
AGND
PGND
AVCC
AVCC
AVCC
AVCC
PVCC
RSVD
QO23
RXC+
RX2+
RX1+
RX0+
RXC-
RX2-
RX1-
RX0-
R100
0 +3VD
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
R75
2
NC_R0603
D28 D29 D30 D31 D32 D33 D34 D35 D36
(open) R85 1.5K
RSVED
3 BAV99 3 BAV99 3 BAV99 3 BAV99 3 BAV99 3 BAV99 3 BAV99 3 BAV99 3 BAV99 ST
B PD B
+3VD
1
R96 R86 1.5K

10K R102 0
DVI_SDA3V
(open) +3VD
R110
180
U21
3 EDID_VCC
VDD
2 GND
+3V_ADVI R111
RES 1 100K RESETZ_DVI
AME8500BEETAF29
E_RES
OCLK_INV
RESETR111
L45
42 OHM +3V_PDVI
D2+
D2-
L44 D1+
42 OHM D1-
D0+ R78 R99 0
(OPEN) C176
D0- DVI_SCL3V 1U Z
IDCK+ 390
L43 IDCK-
42 OHM R76 +3VD
1.5K +5V_EDID
+3VD
(open)
L42
42 OHM +3VD
+5V_AD +3V_ADVI
U19
+3VD
R77 R107 R108 R109
10K U18 1K 4.7K 4.7K
3 VIN VOUT 2
1 8
GND
NC VCC WP
2 NC WP 7
3 NC SCL 6 DVI_SCL
C157 LD1117-3.3V C158 C159 C160 C161 C162 C166 C167 C168 C169 4 5 DVI_SDA
1
4.7U Z 4.7U Z 0.1U Z 0.1U Z 0.1U Z 0.1U Z 0.1U Z 0.1U Z 0.1U Z 0.1U Z GND SDA
AT24C16 16K
A A
+3V_PDVI
+5V_AD
U20 C170
0.1U Z
C171
0.1U Z
C172
0.1U Z
C173
0.1U Z
Benq Corporation
3 VIN VOUT 2
99.J5877.001 HT720G NA
GND
Title
C163 C164 C165 CONNECTOR BOARD
LD1117-3.3V
1
4.7U Z 4.7U Z 0.1U Z

<Size> 48.J5810.S02 S02 99.J5877.R22-C3-304-004 0

5 4 3 2 1

Benq 8700 Service Manual PDF

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DLP PROJECTOR

READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

4. Spare Parts List 23

9. Trouble Shooting Guide 39

10. Factory OSD Operation 49

11. Firmware upgrade procedure 56

12. RS232 Codes 58

Criteria: Follow HD2 DMD image quality specifications

5.2.1 Composite RCA x 1

Uniformity = MIN ( E10, E11, E12, E13)

E10 E11 1/20h

A3. BRIGHTNESS DIFFERENCE

A4. ANSI CONTRAST

A6. LIGHT LEAKAGE

A7. IMAGE DISTORTION

A8. THROW RATIO

Dynamic Testing Specification

Set 1 (3 units) Set 2 (3 units) Set 3

Drawing 1: Top view of BENQ PE8700 video projector

2.2 Dark pixel

2.3 Bright pixel

2.4 Unstable pixel

2.5 Adjacent pixels

2.6 Border defects

2.7 Blue test screen

Major Light Blemish

2.9 Gray 10 test screen

Major Light Blemish

2.10 White test screen

Major Dark Blemish

Major Dark Blemish

Major Dark Blemish

3.1 Test Conditions (as tested in OEM projector)

· Refer to Table 1 for acceptance criteria, in specified order:

TEST TEST SCREEN ACCEPTANCE CRITERIA

4 Major Light Blemish Gray 6 No light blemishes visible on Gray 6

6 Minor Blemishes White or Black Total of Dark and Light Blemishes ≦

Table 1: Support Timings by DVI-I Input (Analog or Digital PC signals)

Table 2: Support Timing by DVI-I Input

Projector PE8700 99.J5877.B21

Conntctor Board Main Board DMD Board

RGB DVI Sil169

1. DMD Bias Voltage Alignment

Item Value Item Value

12. Select “Save Setting” at “Factory OSD>Factory>”.

OSD Default value used for DVI-Analog color alignment

Item Value Item Value

B. White Level Adjustment: (AD contrast---R,G,B gain)

C. Offset adjustment at low brightness (AD R, G, B offset)

D. Color Temperature at high brightness (Scalar Gamma R, G, B Gain)

Color Temp 4 = color temp is the same as that of 6500K

4. Adjust 6500K temperature color by changing Gamma-Rgain, Ggain, and Bgain.

user>setup>white C0 C1(5400k C2(6500k C3(7500k

4. YPBPR Color Alignment

OSD Default value used for YPBPR color alignment

Item Value Item Value

1. The variance of color coordinate via Pb offset and Pr offset:

b). Gray Level: (AD YPBPR Contrast, Brightness)

Use Lux meter to

Case Case Case Case

Decrease Pb offset Increase Pb offset

Case x<=x0: Case y<=y0: Case x>=x0: Case y>=y0:

Case x1<x0 & y1 < y0 :