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module dc_mtr(

clk,
reset,
select_in,
output_o
);

input clk;
input reset;
input [2:0]select_in;
output reg [1:0]output_o;

reg data;
wire [0:2]q;
wire [0:2]qbar;
reg [0:2]count_temp;
wire [24:0]counter_out;
reg temp_clk;
reg state;

generic_counter g0 (clk,reset,counter_out);

tff_T t1(data,q[0],reset,q[1],qbar[1]);
tff_T t2(data,q[1],reset,q[2],qbar[2]);
tff_T t0(data,counter_out[8],reset,q[0],qbar[0]);

always @ (posedge counter_out[8]) begin

if (reset == 1'b1) begin


state <= 1'b0;
end
else begin
if (state == 1'b0) begin
if (q == count_temp) begin
state <= 1'b1;
end
else begin
state <= 1'b0;
end
end
else if (state == 1'b1) begin
if (q == 3'b111) begin
state <= 1'b0;
end
else begin
state <= 1'b1;
end
end
end
end

always @ (state) begin


case (state)
1'b0 : output_o <= 2'b01;
1'b1 : output_o <= 2'b10;
endcase
end
always @ (select_in) begin
case (select_in)
3'b000 : count_temp <= 3'b000;
3'b001 : count_temp <= 3'b001;
3'b010 : count_temp <= 3'b010;
3'b011 : count_temp <= 3'b011;
3'b100 : count_temp <= 3'b100;
3'b101 : count_temp <= 3'b101;
3'b110 : count_temp <= 3'b110;
3'b111 : count_temp <= 3'b111;
endcase
end

endmodule