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Introduction to SPI

Serial to Peripheral Interface (SPI) is a hardware/firmware communications protocol developed

by Motorola .It’s commonly called as a 4 wire protocol.

The Serial Peripheral Interface or SPI-bus is a simple 4-wire serial communications interface
used by many microprocessor/microcontroller peripheral chips that enables the controllers and
peripheral devices to communicate each other. SPI is a fully duplex protocol which can get up to
speeds of 10 Mbps.

The protocol is easy to implement and takes less resources. It is a single master, multiple slave
protocol. Four wires are generally used in SPI communication with a single slave. They are

MISO – Master In Slave Out

MOSI – Master Out Slave In

SCLK- Serial Clock

SS – Slave Select {Active low usually}

The communication is controlled by Master all the time. Master gives the serial clock and the
selects the slave by putting an active low signal in the slave select line. At each clock edge a fully
duplex data transmission takes place. Master puts data in MOSI and Slave puts data in MISO.
Data gets latched in the next edge of the clock, since we need half the clock period to get the
stable data. This continues as long as master needs to send data. When there is no more data
to be exchanged, the master stops the clock and deselects the slave.

Serial Communication to ADC MCP 3008

ADC MCP 3008 is an SPI compatible 10 bit SAR ADC. . Initiating communication with either
device is done by bringing the CS line low. If the device was powered up with the CS pin low, it
must be brought high and back low to initiate communication. The first clock received with CS
low and DIN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will
determine if the conversion will be done using single-ended or differential input mode. The
next three bits (D0, D1 and D2) are used to select the input channel configuration. Tables given
below show the configuration bits for the MCP3004 and MCP3008, respectively. The device will
begin to sample the analog input on the fourth rising edge of the clock after the start bit has
been received. The sample period will end on the falling edge of the fifth clock following the
start bit.

Once the D0 bit is input, one more clock is required to complete the sample and hold period
(DIN is a “don’t care” for this clock). On the falling edge of the next clock, the device will output
a low null bit. The next 10 clocks will output the result of the conversion with MSB first, as
shown in Figure .Data is always output from the device on the falling edge of the clock. If all 10
data bits have been transmitted and the device continues to receive clocks while the CS is held
low, the device will output the conversion result LSB first. If more clocks are provided to the
device while CS is still low (after the LSB first data has been transmitted), the device will clock
out zeros indefinitely.
Fig 2: Communication with MCP 3008

Fig 3: Configuration bits of ADC

Interfacing Krypton to ADC MCP 3008
The maximum clock frequency of ADC is 200 KHz and also the minimum is 10 KHz. The Krypton I/O pins
can handle voltages up-to 3.3 V only. The available supply on board is 5 V. This needs the usage of a
voltage regulator convert the 5V to 3.3 V to interface with ADC.

Now we need to down convert the clock frequency available from Krypton, ie 50 MHz to a frequency
less than 200 KHz and greater than 10 KHz for proper operation. This needs the creation of a hardware
block in Krypton to which can divide frequency. We need a Parallel In Serial Out register to load the
control word of ADC and serially push it out on clock in MOSI line. Another Serial In Parallel Out register
can be used to get the data serially from ADC and display it when the entire data is obtained. Both this
registers can be made into one , if a mode select signal is used.

Basic reconfigurable hardware created is shown below.

Fig 4 : Basic hardware architecture

The frequency divider can be a counter whose mode can be selected based on the division factor.

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