DATE:

Experiment:-9 PAGE NO:

AIM:- To study & implement following flip-flop.

(1) J K flip-flop.

(2) D flip-fop.

(3) T flip-flop.

APPARATUS:- Digital trainer kit ,IC 7473 ,Connecting wires,etc.

THEORY:-

A flip-flop circuit can maintain a binary state indefinitely untill directed by an input signal to
switch states .The major differences among various types of flip-flops are in number of inputs
they posses and in manner in which the inputs affect the binary state.

(1) J K flip-flop:

A J K flip-flop is refinement of the RS flip-flop in that the indetermined state of the RS type is
defined in the JK type when inputs are applied to both J and K simultaneously the flip-flop
switches to the complements state that is if Q=1 it switches to Q=0 & vice versa.

A clocked J K flip-flop is shown in fig 1,output Q is ANDed with and cp input so that flip-flop
is cleared during a clock pulses only if Q was previously one. similarly output Q’ is ANDed
with J and cp inputs so that the flip flop is set with a clock pulse only if Q’ was previously 1.

The characteristic & symbols for JK flip flop are shown in Table & fig 1.a respectively.
J K FLIP-FLOP (Negative Edge T riggered)
Logic symbol,State table& Pin diagram of IC 7473

INPUTS
0 0 CLOCK Q0
Q

0 1 0

1 0 1

1 1 Q0’
 (2) D flip-flop:

The edge triggered D flip-flop has only one input terminal.The D flip-flop may be obtained from
a J K flip-flop by putting just one inverter between J and K terminals.Fig shows the logic
symbol and the truth table of positive edge triggered D flip-flop.

This flip-flop has only one synchronous control in addition to the clock.This is called D
input.The operation of D flip-flop is very simple.

The output Q will goto the same state that is present on the D input at positive going transition
of the clock pulse.In other words the level present at D will be stored in the flip-flop at the
instant the positive going transition occurs.

D FLIP-FLOP (Negative Edge Trigger)

D CLOCK Q
0 0

1 1

(3) T flip-flop:

A T-flip-flop has a single control input labelled T for toggle .When T is high the flip-flop
toggles on every new clock pulse.When T is low the flip-flop remain in whatever state it was
before it is easy to convert a J K flip-flop to the functional equivalent of a T flip-flop by just
connecting J&K together.Thus when T=1 & J=1 &K=1 flip-flop toggles.

When T=0 we have J=K=0 & there is no change.The logic symbol & truth table are shown in
fig.

T FLIP-FLOP (Negative Edge Trigger)

T CLOCK Q
0 Q0
1 Q0
PROCEDURE:-

 First of all on the trainer kit give the clock pulses input to the J K flip-flop and according

to the truth table give the input combination

 Now,observed the output Q and Q’ given to the LED.

 For the D flip-flop make the input terminals J K short with NOT gate between them &

give inputs 1 & 0 simultaneously observed the output for D flip-flop

 For the T flip-flop directly short the input terminals of J K flip-flop give the input 1 due

to which flip-flop toggles & give the 0 input for which there won’t be any change.

CONCLUSION:-