SCAN DRC Violation Solutions

S1 Violation: all the clock inputs (including sets and resets) of In dofile, before inserting
each non-scan scan chains, you must
memory element to ensure that these inputs can be turned off. specify the cell models
with the
Unstable non-scan cells when clock is off add_cell_models
command. You can use
/StartSyncWr_reg  clock the report_dft_check
/PMWr_r_reg  set command to display the
/DMWr_r_reg  set signals where test logic
/MemWrSync1_reg  Reset & Clock can be inserted to make
the signals controllable.

set test logic -set on -

reset on -clock on :
Inserts test logic to
control the set, reset,
clock, enable, or write
control signals to make
them
scannable when scan
chains are inserted

Or by manually hacking
the netlist i.e. by manually
adding required library
cells(in our case mux)
make the clock, set, and
reset controllable
S2 Violations: checks all clock inputs (not including sets and In dofile, before inserting
resets) of each non-scan scan chains, you must
memory element to see whether they can capture data. specify

The report_dft_check command set test logic -clock on:

provides information for troubleshooting these failures, by Inserts test logic to
listing the cells that fail this check control clock, to make it
along with their associated gate identification numbers. scannable when scan
chains are inserted
There were 3 clock rule C7 fails (nonscan cell capture ability check).
Or by manually hacking
Note: There were 3 S2 violations that will be fixed by adding test logic the netlist i.e. by manually
adding required clk to the
C7: #fails=3 handling=warning (scan cell capture ability check) failing cells.
D5: #fails=3 handling=warning (non-scan memory element)
S2: #fails=3 handling=warning (clock capture ability check)

/IncCr_reg  clock grounded

/StartSyncWr_reg  clock grounded
/MemWrSync1_reg  clock grounded

E4 violation: bus contention: Solution: Manual hack the

Warning: There were 1 BUS gates which may have possible contention. netlist.
(E10)
E4: #fails=4 handling=warning (bus contention during test procedures) Make scan_en as input
E10: #fails=1 handling=warning/atpg (possible BUS contention) port and add two and
ATPG bus checking performed on '/c3' (116) for 3 bussed TSDs. gates and one OR gate to
Where /c3 is bus having multiple input and one output. possible pass one of the
bus input to output by
Bus input enabling corresponding
i0, i1, i2 all three are driven by tristate buffer enable by
OR gate

Bus is having two drivers ‘72’ tristate buffer is enabled and ‘70’ tristate
buffer is also enabled

Solution: command edit:

Not knowing. Please
suggest the same.

Case 5: No violations Two latches are skipped

from the scan-insertion
"Design has 1 clock domain with DFFs and latches and insert 2 scan process. This is expected.
chains"

Latches in the original net-list(pre-scan).

1.) TLATX1 StartSyncRd_reg ( .G(n425), .D(MemReadSync1), .QN(n74)

);
2.) TLATX1 StartSyncRd_reg (.Q () , .QN ( n74 ) , .D ( MemReadSync1 )
, .G ( n425 ));
***********************************************************
***************************************************
***********************************************************
***************************************************
Latches in the scan inserted netlist

1.) TLATX1 StartRd_reg (.Q ( StartRd ) , .QN ( net232898 ) , .D ( N53 ) ,

.G ( N52 ));
2.) TLATX1 StartSyncRd_reg (.Q () , .QN ( n74 ) , .D ( MemReadSync1 )
, .G ( n425 ));

Two non-scan elements in the design net-list. Two scan-chains were

created. There were 56 sequential elements found and 54 are
converted into scan-cells and stitched properly.
Case 6: Design has 1 clock domain with only Scan FFs and insert 3 scan
chains.
Case 7: Design has no ATPG model for a Flip flop used in the netlist,
later create the model and insert scan with 2 scan chains.
Case 8: Design has 1 clock domain and a 10bit shift register. Insert scan
for the design and make the 10bit shift register has part of the scan
chain without converting it to Scan FFs. Use 2 scan chains with new
ports for scan in and scan out
Case 9: Design has 1 clock domain, insert 2 scan chains for design
containing 2 memories but no memory Bist or collar around the
memory
10) Design has modules where in block1 is already scan inserted with 4
scan chains. Insert scan for other blocks with 4 chains. Balance the scan
chains for the entire design from the top module using 4 chains.
Case 11: Design has 2 modules block1 and block2. Insert 4 scan chains
for the design by
ignoring block2 and insert lockup latches at end of chains

Top
|___block1
|___block2
Case 12: Design has 3 clocks(one +ve, one -ve, one using both edges)
a) use default scan insertion
b) mix clock domains and insert scan
c) mix edges and clock domains and insert scan
d) use a single test clock and insert 4 scan chains