EXPERIMENT 12(I): SYNCHRONOUS D-FLIP FLOP

AIM: To design and simulate Synchronous D Flip Flop using nonblocking

behavioral modeling.
VERILOG CODE: endmodule

`timescale 1ns / 1ps

module D_Flip_Flop_01_src( VERILOG TEST BENCH:

input D, module D_Flip_Flop_01_sim();

input Clock, reg D,Clock,Reset,Preset;

input Reset, D_Flip_Flop_01_src

inst(D,Clock,Reset,Preset,Qn);
input Preset,
initial
output reg Qn
begin
);
Clock=1;
always@(posedge Clock)
forever #6 Clock = ~Clock;
begin
end
if(Reset)
initial begin
Qn<=0;
Reset=1;
else if(Preset)
Preset = 0;
Qn<=1;
D=0;
else
#20;
Qn<=D;
D=1;
end
Reset=0;
#20; D=1;

Reset=1; #20;

#20; Preset = 0;

D=1; Reset=1;

Reset=0; #20;

#20; D=1;

D=1; Reset=0;

#20; #20;

D=0; D=1;

Reset=1; #20;

#20; D=0;

Reset=1; #20;

D=0; end

Preset = 1; endmodule

#20;
SIMULATION WAVEFORM:

RTL SCHEMATIC:
TECHNOLOGY SCHEMATIC:

UTILIZATION REPORT:
POWER REPORT:

RESULT:
The Synchronous D Flip Flop has been successfully designed and simulated using
nonblocking behavioral modelling with its simulation waveforms, power and
utilization reports, and RTL Schematic.