Prifysgol Morgannwg
Examinations:
MAIN ASSESSMENT SESSION 2006/07
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UNIVERSITY OF GLAMORGAN
Prifysgol Morgannwg
Examinations:
MAIN ASSESSMENT SESSION 2006/07
Date (Student Registry use only) Time (Student Registry use only) Duration:
3 hours
Instructions to Candidates:
QUESTION 1
a) Design a logic circuit (using logic gates) for the one-to-two demultiplexer shown in
Figure Q1.
4 marks
A
Input DEMUX Outputs
X
B
Control
‘0’ selects A
‘1’ selects B
Figure Q1
b) A (4 to 10) decoder is able to accept a 4 bit binary input corresponding to the
binary representation of decimal numbers between numbers 0 to 9. The output
gives a logic ‘1’on on the output line corresponding to the decimal number.
E.g. if the input is (0000) the first output will be switched to 1. If the input is
(0001), the second output is switched to 1 etc. Design the required logic
circuit.
8marks
c) Draw a diagram to show how four D-type flip-flops can be used to construct a four
stage shift register.
4 marks
d) Using the multiplexing principle, add a new control signal S to your shift register to
allow data to be input in parallel (S=1) or in series (S=0).
4 marks
QUESTION 2
a) What are hardware description languages (HDL) and how are they different
from computer programming languages such as C? Also, mention two widely
used HDLs.
5 marks
b) What are the 4 levels of abstraction in digital circuit design?
5 marks
(i) S-R flip-flop (ii) J-K flip-flop (iii) D-type flip-flop (iv) T-type
flip-flop.
5 marks
b) Design an asynchronous binary counter using D flip-flops which will count to 15
and then reset.
5 marks
c) Design an asynchronous binary coded decimal counter (BCD) using D-type flip-
flops which will count to 9 and then reset.
5 marks
d) Extend your design to make a ‘hundreds’, ‘tens’ and ‘units’ BCD counter. Explain
how the circuit works.
5 marks
QUESTION 4
a) Name two types of digital to analog (DAC) converters. Explain the relationship
between DAC resolution and the voltage range
5 marks
b) With the help of a schematic, explain the principle of operation of a flash analog to
digital converter (ADC).
5 marks
5 marks
d) Draw the voltage graph if we were to use a successive approximation ADC instead.
5 marks
a) Give a diode based implementation or the logic gates “AND” and “OR”.
5 marks
c) Using a diagram, illustrate the main components of the Van Newmann computer
machine. Explain the role of each part.
5 marks
d) What is the predication made by Moore’s law with regards to the evolution of
semiconductor integration? What are the limits of this evolution? What are the
possible new technologies that could in the future replace the current semiconductor
based computing machines.
5 marks
c) Using JK flip-flops, design a synchronous counter that will count the following
number sequences:
5 marks
0 1 3 2 7 0 1 3 2 7 0 1 3 2 7 etc.
d) Using the state machine diagram design methodology, Design a pattern recognition
system that will detect the following pattern in a stream of bits:101
5 marks
A circuit has 4-bit binary input ranging from 0000 to 1111 . The circuit detects
even numbers from odd numbers i.e. Output is high when the input is
0,2,4,8….,14. and low when input is: 1,3,5,7….15.
QUESTION 8
A Cout
Full Adder
B
Cin S
Figure Q8
From the truth table, obtain Boolean expressions for both the sum S and the
carry Cout.
5 marks
b) Hence design a 1 bit full adder using a minimal number of logic gates.
7 marks
END OF PAPER