Relays
11
11
Operating at a
Normalized Energy/op
Normalized Energy/op
does not help
Nano-Electro-Mechanical (NEM) relay is a promising device lower energy point
1×
10
10
overcoming the energy-efficiency limitations of CMOS tran- 1×
sistors operating at or near the sub-threshold voltage. Many
9
9
2× 8× 2×
exploratory research projects are currently under way inves-
tigating the mechanical, electrical and logical characteristics
8
8
Run in
of NEM relays. However, before this new and exciting tech- parallel to recoup performance
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DAC ’14 SAN FRANCISCO, CA, USA Figure 2: Sub-threshold regime of MEM relay and
Copyright 20XX ACM X-XXXXX-XX-X/XX/XX ...$15.00. CMOS transistor.
Spring-Mass-Damper
K b Model
Source Base Drain
Insulator :
Substrate : Si
(a) (b)
Figure 3: (a) Schematic 3-D view of 4-terminal suspended gate MEM relay based on [18], (b) Schematic 2-D
cross section view in the off state.
+
+
Table 2: NEMS parameters based on [18]
g0 10 nm d s
gd 5 nm b
Aov 0.77 [µm2 ]
A 12 [µm2 ] 2. The non-linear parasitic capacitor Cgd , and Cgs can be
Cgd (Z = 0), and Cgs (Z = 0) 0.6 [f F ] linearised by taking the maximum value (Cgd = Cgs =
Cgb (Z = 0) 1.46 [f F ] 0.6f F at Z = 5 nm). Then, they have been added
R(ch/2+con+pox) 800 Ω together as shown below.
g
7.0
f
+
average. However, as the size of the circuits increase, the
+
+ / simulation time of the standard model is expected to be in-
+ /
d b s creasing drastically, and hence this percentage can be con-
sidered only for the used benchmark circuits.
In terms of computational complexity, the original model In terms of latency, results indicate a small difference be-
needs to solve 8 non-linear equations to approach the solu- tween the output signal of the two models (less than 6% in
tion. While our proposed model can approach the solution average). This is attributed to the presence of approxima-
by only solving 5 non-linear equations as shown in Algorithm tion in the electrical circuit of the proposed model. It has
II. been noted from the results in Table III that the standard
Algorithm 2 Proposed NEMS model. model usually diverges when the design becomes complex
Define: Source:=s, Drain:=d, Gate:=g, Base:=b, Displace-
and big in size, such as in: 3-inputs C-Element and 5-bit
ment:=Z. carry ripple adder. This is attributed to the fact that the
Define: Discipline: Electrical ← (s, d, g, b) accumulating error due to contact discontinuities will rise
Discipline: Kinematic ← (Z, velocity). significantly as the number of stage increases. Furthermore,
Input: (Vg , Vs , Vb ). numerous number of non-linear parasitic capacitance in the
Output: (Vd ). big design is the second reason of causing the model to be
Define: Constant(Cgc , Ccb , Rtrace , Rch/2 ,Cgd ,Cgs ,Rpox , Rcon ).
diverging.
Define: Dimple gap (gd ), Spring constant, mass, Damping ratio.
1: Initially (Vg , Z) ← 0. The proposed model has checked against the standard one
2: Calculate Fe , Fs , Fvdw at (Z = 0). for different clock speed and stage levels. Results in Fig. 7
3: Calculate Z1 by solving Eq. 7. have shown a very slight impact in the simulation time of
4: If Z1 < gd Then: (NEM relay is on) the proposed model can happen as the clock period changes
5: Calculate Cgb , Fele , Fvdw . from 100ns to 500ns. For example, at stage four the simula-
6: Find: V (d, f ) = V (f, s) = R(pox+ch/2+con) ∗ I(d, f ), tion time increases only 10% as the clock period changes to
dV dV
I(f, g) = 2Cgd ∗ (g,f dt
)
, I(g, b) = Cgb ∗ (g,b)
dt
. 500ns. In contrast, the standard model shows a significant
7: Find I(d, s), Tele , Tmech , Vpi , and Es . 800
8: else: I(d, s) = 0 (NEM relay is off) Standard model [100ns]
Simulation time [sec.]
further reduction in threshold voltage of integrated circuits ultra-low-power digital logic. Electron Devices, IEEE
comes at the expense of high power consumption. Further- Transactions on 58, 1 (2011), 236–250.
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expected to be scaled less than the limit set by kT q
. Thus, tunnel field effect transistors with record high ion/ioff.
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sub-threshold regime like a NEM relay is necessary to be im- pp. 178–179.
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for large scale circuit simulation with insignificant error. The [10] Manohar, S., Venkatasubramanian, R., and
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