Tarea #3 de Microprocesadores

Grupo: 1IT141
Fecha: 04/05/2016

 Código Principal del TOP LEVEL (Unión por componentes)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Tarea3_Enti is
port(
StopN : in std_logic;
Clk : in std_logic;
ResetN : in std_logic;
SEG : out std_logic_vector(0 to 6);
Overflow : out std_logic
);
end Tarea3_Enti;
architecture Behavioral of Tarea3_Enti is
COMPONENT divisor
PORT
iclk : IN std_logic;
oclk : OUT std_logic
);
END COMPONENT;
COMPONENT counter
PORT( stp : IN std_logic;
clock : IN std_logic;
rst : IN std_logic;
overflowi : OUT std_logic;
Q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

COMPONENT decoder_bcd
PORT(
I : IN std_logic_vector(3 downto 0);
seg0 : OUT std_logic_vector(0 to 6)
);
END COMPONENT;
signal clk_s, of_s : std_logic;
signal q_s : std_logic_vector (3 downto 0);

begin
overflow<= not(of_s);

Inst_divisor: divisor PORT MAP(

iclk => clk,
oclk => clk_s
);

Inst_counter: counter PORT MAP(

stp => stopn,

clock => clk_s,
rst => resetn,
overflowi => of_s,
Q =>q_s
);
Inst_decoder_bcd: decoder_bcd PORT MAP(
I => q_s,
seg0 => seg
);
end Behavioral;
  Codigo del Divisor (reloj)

entity divisor is
port(
iclk : in std_logic;
oclk : out std_logic :='0'
);

end divisor;
architecture Behavioral of divisor is
begin
process(iclk)
variable count : integer range 0 to 20 :=0;
begin
if (iclk'event and iclk='1') then
if count = 3 then
count:=0;
oclk<='1';
else
count:= count + 1;
oclk<='0';
end if;
end if;
end process;
end Behavioral;

 Codigo del Contador

entity counter is
port(
stp : in std_logic;
clock :in std_logic;
rst : in std_logic;
overflowi : out std_logic := '1';
Q : out std_logic_vector(3 downto 0)
);
end counter;
architecture Behavioral of counter is
signal temp : std_logic_vector(3 downto 0)

begin
process(stp, clock, rst)
begin
if rst='0' then
temp<="0000";
elsif stp='1' then

temp<=temp;
elsif(clock'event and clock='1') then
if temp < "1111" then
temp<= temp + 1;
overflowi <= '1';
else
temp<="0000";
overflowi <= '0';
end if;
end if;
end process;
q<=temp;
end Behavioral;
  Codigo del decodificador
entity decoder_bcd is
port(
I : in std_logic_vector(3 downto 0);
seg0 : out std_logic_vector(0 to 6)
);
end decoder_bcd;
architecture Behavioral of decoder_bcd is

Begin
process(I)

begin
case I is

when "0000" => seg0 <= "0000001";

when "0001" => seg0 <= "1001111";

when "0010" => seg0 <= "0010010";

when "0011" => seg0 <= "0000110";

when "0100" => seg0 <= "1001100";

when "0101" => seg0 <= "0100100";

when "0110" => seg0 <= "0100000";

when "0111" => seg0 <= "0001111";

when "1000" => seg0 <= "0000000";

when "1001" => seg0 <= "0000100";

when "1010" => seg0 <= "0001000";

when "1011" => seg0 <= "1100000";

when "1100" => seg0 <= "0110001";

when "1101" => seg0 <= "1000010";

when "1110" => seg0 <= "0110000";

when "1111" => seg0 <= "0111000";

when others => seg0 <= "1111110";

end case;

end process;

end Behavioral;
 Efecto del Stop y del reset en la salida del 7 segmentos

 Activacion del overflow cuando se reinicia la cuenta (pasa de F a 0)