Register Number

SATHYABAMA UNIVERSITY
(Established under section 3 of UGC Act,1956)
Course & Branch : M.Tech - VLSI
Title of the Paper : VLSI Signal Processing Max. Marks:80
Sub. Code : SECX5024-782301 (2008-2010) Time : 3 Hours
Date : 05/03/2012 Session :FN
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PART - A (6 x 5 = 30)
Answer ALL the Questions
1. Distinguish loop bound and iteration bound.

2. List the properties of Retiming techniques.

3. What is the need for systolic architecture design?

4. Explain redundant to non redundant converter.

5. What is wave pipelining?

6. Explain scaling versus power consumption.

PART – B (5 x 10 = 50)
Answer ALL the Questions

7. Explain algorithms for computing iteration bound.

(or)
8. Consider the recursive filter x(n)=ax(n-2)+u(n).Pipeline this
multiply-add operator by 2 stages, by first breaking up the
multiply add operation into 2 components and redistributing the
delay elements in the loop.
9. Prove that the critical path of a J –unfolded DFG is greater than
or equal to the critical path of the (J-1) unfolded DFG.
(or)
10. Unfolding preserves the number of delays in a DFG. Prove.

11. Draw the space time mapping of design R1.

(or)
12. Design a radix-4 minimally redundant to non redundant converter
operating in the lsd-first mode for word length of 8 digits.

13. Draw an H-tree distribution network for a 4-bit x 4-bit array of

regular cells with and without intermediate buffering.
(or)
14. Design a 9-transistor positive edge triggered true single phase
clocked flip-flop and explain its operation.

15. Discuss Speed –Area-Power tradeoff issues related to mixed

signal design and SOC.
(or)
16. Explain CORDIC algorithm with example.