1.

Introduction:

An Insulated Gate Bipolar Transistor (IGBT) is a power semiconductor device,

which is widely used in power electronic applications such as uninterruptible power supplies, motor

drives and active filters. An IGBT combines certain advantages of a power Bipolar Junction

Transistor (BJT) and a power Metal Oxide Silicon Field Effect Transistor (MOSFET). An IGBT

can be driven easily and switched at high frequencies like a MOSFET. Further it has low on-state

loss and a high current density like a BJT.

For an IGBT based converter to be rugged and reliable, the IGBT gate-drive circuit

should be reliable. In this paper, a gate-drive circuit for an IGBT is presented. The drive circuit is

capable of protecting the IGBT against short-circuit. During fault, excessive current flows through

the device, causing the device to come out of saturation and increasing the collector-emitter voltage

Vce. The gate-drive circuit senses a fault through the increased Vce drop [1]-[5], and shuts down the

gate pulses. The drive circuit also protects the IGBT from gate-emitter over-voltage [6]-[8].

Further, if the on-state gate-emitter voltage decreases, the on-state drop of the device increases,

leading to increased loss and possible device failure [6]-[9]. The proposed circuit is capable of

protecting the device from gate-emitter under-voltage as well.

The proposed IGBT gate-drive circuit is tested both under normal condition and

short-circuit condition. The switching characteristics include gate-emitter voltage Vge, collector-

emitter voltage Vce and device current Ic. While Vge and Vce can be measured, there are difficulties

in sensing Ic in many practical situations. A current probe of appropriate bandwidth may not be

available or may be too expensive. More importantly, it may not be possible to insert a current

probe in series with the device owing to the sandwich bus-bar structure. Such a bus-bar structure is

to ensure low parasitic inductance in order to avoid excessive over-voltage spikes that could cause

device failure [1]. Owing to such practical difficulties, this paper adopts a testing method which

does not require any current sensing.

Section 2 of this paper briefly discusses the gate-drive requirements. An IGBT gate-

drive circuit is presented in section 3. Section 4 of this paper discusses the experimental set-up.
1
Section 5 and section 6 present the experimental results under normal condition and short-circuit

condition, respectively. The conclusions are presented in section 7.

2. Requirement of a gate-drive circuit:

A gate-drive circuit should have certain features, which help a power electronic

system to be rugged and reliable, as discussed below.

The drive circuit should provide adequate on-state gate-emitter voltage. Also the off-

state gate-emitter voltage should be well below the threshold voltage [6]-[9]. Even though the

IGBT is a voltage controlled device, an adequate amount of gate-drive current is required for a

short duration during turn-on/off as indicated by Fig. 1 and 2, because the device has a large input

capacitance [10]. The gate-drive circuit should be capable of supplying the peak current required

for effective turn-on/off.

For safe operation of the device, the gate-emitter voltage should not exceed the

absolute maximum gate-emitter voltage [6]. An over-voltage protection is required in this regard.

Also, lower value of on-state Vge significantly increases the on-state voltage drop of IGBT [6]. The

increased conduction loss could lead to device failure. The circuit should also be capable of

protecting the device against such failure on account of Vge under-voltage. Further, it should also

have the capability to protect an IGBT against short-circuit. Under short-circuit condition, an IGBT

can withstand a fault current of roughly eight to nine times of its rated current for 10 µs [7]. The

gate-drive circuit should have the capability to sense the fault and turn-off the IGBT well within 10

µs. The following conditions have to be fulfilled to guarantee safe operation [7];

i. The short-circuit has to be detected and turned off within a maximum of 10 µs,

ii. The time between two short-circuits has to be at least 1 second,

iii. The IGBT must not be subjected to more than 1000 short-circuits during its total operation time.

The gate-drive circuit should provide isolation between the control side and the

power side of the system. The high voltages in the power circuit should not reach the control circuit

2
for safety of personnel and equipment. Further, in a voltage source inverter, the pulse width

modulation signals for all six devices are generated in a controller (typically a digital controller).

These signals have to be fed between gate and emitter terminals of the individual devices. The

emitter terminals of different devices are at different potentials. Hence electric isolation is required

between the control circuit and power circuit [5]. Further, the drive circuit should have an on-board

isolated power supply to power the isolated side of the circuit.

Vg VGG
t

Vge
Td,on

Ig Vge,I0 VGG

Vge(th)
t

tr

Ic
I0
tfv2
t
tfv1
Vf1
Vce
Vce,sat

Fig. 1 Turn-on characteristics of IGBT [10]

3
 Vg

- VGG

Td,off
Vge,I0

Vge(th)
Vge

- VGG
Ig tf

tfi1

Ic
I0 tfi2
If1
t

trv
Vce
Vce,sat
VD
t

Fig. 2 Turn-off characteristics of IGBT [10]

An IGBT gate-drive circuit with the above features is presented in the following

section.

3. Proposed gate-drive circuit:

Fig. 3 shows a block diagram of the proposed gate-drive circuit. Fig. 4 presents the

circuit schematic of the same. The gate-drive circuit is powered by a +15V dc power supply. The

4
drive signal and Vce sensing signal are the inputs to the drive circuit, while the gate-emitter voltage

Vge and the status signals are the outputs, as indicated in Fig. 3.

Fig. 3 Block diagram of a gate-drive circuit

3.1 Isolation:

The drive signal is electrically isolated using an opto-coupler HP3101, (U1) [11], as

shown in Fig. 4. The status signal, produced by the gate-drive circuit as will be explained in section

3.4, is similarly isolated using another opto-coupler (U6). An isolated power supply is used to feed

the isolated (power) side of the circuit, indicated by dashed lines in Fig. 3.

3.2 Drive:

When the gate-drive signal is ‘HIGH’, the corresponding output of the opto-coupler,

U1 [11], is also ‘HIGH’. This isolated drive signal is fed to a logic circuit, which is simply a

NAND gate (U3/4), as seen from Fig. 4. The other input to the NAND gate is the isolated status

signal (Status_Iso) produced by the protection circuit as indicated in Fig. 3.

The output of the NAND gate drives an inverting buffer (U4), MIC4429 [12], and a

non-inverting buffer (U5), MIC4420 [12]. The output of the non-inverting buffer is connected to

the emitter terminal as shown in Fig. 4. The output of the inverting buffer is connected to the gate

terminal through gate resistance Rg. Sometimes, the gate resistance required for turn-on and turn-

off transitions are different. In Fig. 4, R16 is Rg,on, while R17 is Rg,off.

5
 +15V_ISO
+15V_ISO
+15V_ISO
R20
+15V
R13 8
R10 R15 2
R8 C4 R12 7 C12
R9 STATUS
C' 3 7 +
11 + TP8
TP12 R7 6 1 R27 C23 6
10 13 R11 3 TP3
12
R14 U2/2 5
Z1 U2/1 Z2 U6
Q2 C'
TP7 R18
D1 R6 U3/1 GND_ISO
1 R19
3 J3
2 5 8 GND_ISO
TP6 4 10 TP9
C3 6 9 D2 R17
R5 U3/2 U3/3
1 7,6 G'
PWM +15V C6 TP10
STATUS 4 8 R16 D3
R4
+15V 8 C2 I C8 C10
GND C5 2 5 G'
2 7 14
U4 E'
J1 12
11 GND_ISO
13 J2
R1 C1 6 TP5 U3/4
7
3
5
1 7,6 E'
PWM Q1
TP1 U1 C7 TP11
R2
4 8
R3 LED O/P
ON H NI C9 C11
2 5
OFF L U5
GND
+15V
TP16 U8 TP17 +15V_ISO
C22 T1 D4
1 2 3
U7
R26 C15 C17 C19 R25
C15

14 2,12,15
R24

R21
8,11
C16 C18 LD2
C20

C13 3 TP13 R23

6
D5 TP15
TP18
POT1

1,4,7,9
LD1 5 10,13,16 GND_ISO
Q3
R22
C14 TP14

GND TP4

(a)

(b)

Fig. 4 (a) Gate-drive Card (b) Zener Card

Under healthy condition, if the drive signal is ‘HIGH’, then the output of the NAND

gate (U3/4) is ‘LOW’. Correspondingly, the voltage at the gate terminal is ‘HIGH’ (due to inverting

6
buffer), and the voltage at the emitter terminal is ‘LOW’ (due to non-inverting buffer). This results

in the gate-emitter voltage being +15V. Similarly, when the drive is ‘LOW’ or the opto-coupler

output is ‘LOW’, the Vge applied is -15 V.

A 10 µF WIMA capacitor [13] is connected to each of the two buffers as

recommended in the datasheet of the inverting and non-inverting buffers [12]. The driver stage

made up of these two buffers is capable of supplying a peak current of up to 6A.

3.3 Protection:

The on-state Vge equals the output of the isolated power supply. Hence, if the power

supply output decreases for some reason, the on-state Vge also reduces correspondingly. This could

lead to a high on-state Vce drop as measured earlier [6]-[9]. A comparator circuit based on LM339,

(U2/2) [14], is used to detect such a situation. The status signal (Status_Iso) is made ‘LOW’ if the

voltage is less than 13 V.

To protect the IGBT from Vge over-voltage, two back-to-back connected zener

diodes are used as shown in Fig. 4(b). Since these should be very close to the gate and emitter

terminals of the device, these are assembled on a separate board, called ‘zener card’, which sits on

the gate and emitter terminals of the device.

The zener card also contains a fast-recovery diode, which is used to sense the

collector voltage for short-circuit protection, based on ‘de-saturation technique’. When current

through the device increases, Vce increases as stated earlier. The collector voltage is sensed using a

fast-recovery diode, D6, and is fed to the non-inverting terminal (C') of a comparator, LM339

(U2/1) [14]. A zener, Z1, provides the reference voltage corresponding to allowable Vce for safe

operation. The reference voltage is set at 6.2 V here. Under healthy condition, the output of the

comparator is ‘LOW’. When the voltage at terminal C' (due to increase in Vce) goes beyond the

reference voltage, the output of the comparator becomes ‘HIGH’, indicating a fault.

7
3.4 Status Signal:

The comparator circuit (U2/1) detects a short-circuit or a fault whenever the gate-

drive is high and Vce is greater than 6.2 V. This could happen during the turn-on transition of the

device, when the gate-drive is ‘HIGH’ and the Vce is yet to reduce below the reference voltage.

Hence the status signal is held ‘HIGH’ for a short duration after the gate-drive has a low-to-high

transition, regardless of the collector voltage. This short duration of time is termed ‘blanking time’

(Fig. 3). To achieve this, the isolated drive signal is delayed by R5 and C3, as shown in Fig. 4. This

is fed to a NAND gate (U3/1), along with the output of the comparator (U2/1), as shown in Fig. 4.

When there is neither Vce fault nor Vge under-voltage, the isolated status signal

(‘Status_Iso’ in Fig. 3), available at the output of NAND gate (U3/3), is ‘HIGH’. The status is

‘LOW’, when there is a Vce fault or Vge under-voltage. This signal is fed to the opto-coupler (U6),

and is available as the status signal, which is an output of the gate-drive circuit. This signal can be

used by a central protection circuit to shut down the pulses to all the IGBTs in a converter in the

event of a fault [15].

3.5 Isolated Power Supply:

The power supply to the isolated side (power circuit side) is provided by a fly-back

converter as mentioned earlier. The fly-back converter has a two winding inductor, whose windings

are electrically isolated. The details of the inductor are given in Table-I. The switching device used

is a MOSFET (Q3), IRFZ44 [16]. A MOSFET driver TL494 (U7) [17] drives the MOSFET at a

frequency of 80 kHz and a duty ratio of 0.45. The output of the fly-back converter is regulated

using a linear regulator LM7815, (U8) [18]. The specification of this converter is +15 V output,

0.4A average current and 2.5A peak current. In the diagram in Fig. 4, the nodes connected to the

isolated power supply (+15V_ISO) are indicated by a thick circle dot. The nodes connected to the

control side supply (+15V) are indicated by a thick square-shaped dot.

The components details for the gate-drive card and zener card are given in Table-I.

Details of the design of the drive circuit are available in reference [15].
8
 Table-I: Bill of Materials

Sl no Part Name Value Quantity Description

1 C14 2.2nF 1 Disc capacitor
2 C13,C17,C19,C20 0.1µF 4 Disc capacitor
3 C15,C18,C16 10 µF 3 Electrolyte capacitor
4 R22 4.7kΩ, 0.25W 1 Metal Film Resistor
5 POT1 10 kΩ, 0.25W 1 POT
6 R23 8.2Ω, 0.25W 1 Metal Film Resistor
7 R26 220Ω, 0.25W 1 Metal Film Resistor
8 R21 1 kΩ,1W 1 Metal Film Resistor
9 D1, D2, D3, D5,D4 1N4148 5 Diode
10 Q3 IRFZ44 1 MOSFET
11 U7 UC494 1 Pulse generator
12 U8 LM7815 1 Positive voltage regulator
EE25/9/6, 56:70,
13 T1 1 Fly-back transformer
Lp=544µH
14 R1, R27 820Ω, 0.25W 1 Metal Film Resistor
15 R2, R18, R10 15 kΩ, 0.25W 3 Metal Film Resistor
16 R3, R19 6.8 kΩ, 0.25W 2 Metal Film Resistor
17 R4, R20 1.2 kΩ, 0.25W 2 Metal Film Resistor
18 R5 4.7 kΩ, 0.25W 1 Metal Film Resistor
19 R6 82Ω, 0.25W 1 Metal Film Resistor
20 R7, R14 330Ω, 0.25W 2 Metal Film Resistor
21 R8, R9, R15 2.2 kΩ, 0.25W 3 Metal Film Resistor
22 R11, R12,R24 10 kΩ, 0.25W 2 Metal Film Resistor
23 R13 680 kΩ, 0.25W 1 Metal Film Resistor
24 R16, R17 27Ω, 0.25W 2 Metal Film Resistor
25 C1, C23 10nF 1 Disc capacitor
C2, C4, C5, C6, C7, C8,
26 100nF 8 Disc capacitor
C9, C12,C22
27 C3 1nF 1 Disc capacitor
28 C10, C11 1000nF 2 WIMA Capacitor
29 U1, U6 HCPL3101 2 Optical Isolator
30 U2 LM339 1 Comparator
31 U3 CD4011 1 Quad NAND gate
32 U4 MIC4429 1 Inverting Buffer
33 U5 MIC4420 1 Non-inverting Buffer
34 Q1, Q2 2N2222 2 NPN transistor
35 Z1 6.2V, 0.5W 1 Zener Diode
36 Z2 4.7V, 0.5W 1 Zener Diode
37 Z3, Z4 15 V, 0.5 W 2 Zener Diode
38 D6 MUR1100E 1 Fast recovery diode
39 R28 100 kΩ, 0.25 W 1 Metal Film Resistor

4. Experimental set-up:

The experimental set up for testing the gate-drive circuit under normal operating

condition as well as short-circuit condition is shown in Fig. 5. The drive circuit is tested on a

SEMIKRON make half-bridge IGBT module SKM75GB123D [6]. The top device is switched as a

9
chopper, while the bottom device is kept off by shorting its gate and emitter terminals as shown in

Fig. 5(a). The anti-parallel diode of the lower IGBT acts as the free-wheeling diode.

Pre-charging resistors (RD) are used to limit the high charging current during initial

charging of the dc capacitors. Subsequently, once the capacitors are charged close to the steady

state value, these resistors are shorted and by-passed by the contactor shown in Fig. 5(a).

RD
3
Vdc/2 4
Q1
Gate 5
3 Ph driver
Supply 1

6 SW

Q2
Vdc/2
2, 7 LOAD

Fig. 5 (a) Experimental set-up: power circuit

Status
Signal
Protection and C
PWM Signal
Delay card Gate Driver G
Generator
E
Drive
Signal

Fig. 5 (b) Control circuit

To test the short-circuit protection feature of the gate-drive circuit, a switch (SW) is

connected across the load as shown in Fig. 5(a). Once the load is shorted, the device is expected to

be turned off in less than 10 µs by the drive circuit. This duration is much smaller than the charging

cycle of the capacitors through the rectifier. The fault current is driven by the stored energy in the

capacitors, and is not drawn from the mains. Hence the fuses are rated for normal operation (10 A).

For some reasons, if the device is not switched off in less than 10 µs or in the event of any other

persistent fault, the fuses serve to isolate the power circuit from the mains.

The control side of the set-up is shown in Fig. 5(b). The PWM signal is generated

using a square wave oscillator or a function generator. The drive signal is fed to the protection and

10
delay card, which incorporates several protection features required for a voltage source inverter

[15]. The main function of this card here is to latch the status signal produced by the gate-drive card

whenever the signal goes low (unhealthy condition), and prevent further pulses being fed to the

gate-drive card.

5. Test under normal condition:

The IGBT gate-drive circuit is first tested under normal condition with the Semikron

make SKM75GB120D device switched as a chopper. The gate resistances Rg,on and Rg,off are both

22 Ω as recommended in the datasheet [6]. The load is a coil having a resistance of 60Ω.

Fig.6 Turn-on characteristics of IGBT with Rg,on=22Ω (Channel-1: Vge [5 volts/div], Channel-2:
Vce [250 volts/div], horizontal axis: 500ns/div)

5.1 Turn-on characteristic:

The experimental turn-on characteristics of the IGBT are shown in Fig. 6 and Fig. 7.

The gate-emitter voltage Vge and collector-emitter voltage Vce during turn-on are shown in Fig. 6,

while Fig. 7 shows the gate current during turn-on.

11
 Theoretically, as explained in text book [10], when the drive signal goes high

(+15V), the gate-emitter voltage Vge rises exponentially from -15 V to Vge,I0, which is effectively

the steady voltage in the Miller plateau region as shown in Fig. 1. The response has a time constant

of Rg*(Cge+Cgc) [10]. However, according to Semikron application manual [7], Vge rises with three

distinct slope in three different intervals to reach the Miller Plateau level, Vge,I0. These slopes are

seen in the measured Vge, shown in Fig. 6. As seen from the figure, Vge rises initially with a steep

slope for a very short duration (less than 50 ns), followed by a moderate slope over a longer

duration (200-300 ns). Finally, for a duration of 100 ns approximately, Vge rises with an

intermediate value of slope to reach Vge,I0. The measured Vge shows a spike during the first interval,

which could be attributed to parasitic inductances and PCB layout. This spike is not of serious

concern since it is much below the threshold voltage.

While the freewheeling diode is turning off, it draws a significant amount of reverse

recovery current from the DC bus through the device [10]. This reverse recovery current results in

certain overshoot in the Vge characteristics at the starting of Miller Plateau region as shown in Fig.

6. In the Miller plateau region, Vge remains constant at Vge,I0. The observed Vge, I0 is roughly 8.5 V,

which is close to but less than the indicated value of 10 V in the datasheet [6]. This could be

attributed to the load current being fairly low (roughly 15% of the rated current). Since Vge, I0

increases with load current [19], it could be expected to be higher for load currents close to the

rated device current. There are some oscillations in Vge in this region due to stray inductances.

These oscillations reduce with increase in Rg,on as will be shown later in this section.

The turn-on transition is characterized by four switching intervals, namely turn-on

delay time (td,on), collector current rise time (tr), and collector-emitter voltage fall times (tfv1 and

tfv2), as illustrated in Fig. 1. Out of these switching intervals, td,on and tr are very important and are

usually specified in the datasheet [6].

According to Semikron apllication manual [7] and ABB application note [8], the

turn-on delay time is defined as the time interval, measured from the instant when the gate-emitter

voltage (Vge) reaches 10% of its final value to the instant the collector current (ic) increases to 10%
12
of the load current. The rise time, according to [7] and [8], is defined as the time interval following

the turn-on delay, during which ic increases from 10% to 90% of the load current. Alternatively, the

turn-on delay time and collector current rise time could be defined based on the gate-emitter

voltage [10]. The turn-on delay time (td,on) can be measured from the instant gate-emitter voltage

starts rising to the instant gate-emitter voltage is equal to the threshold voltage (when collector

current starts rising). Similarly, the rise time (tr) is defined as the interval starting when Vge= Vge,th

extending up to the beginning of the Miller plateau region, i.e., Vge=Vge,Io. These alternative

definitions based on Vge are used in this work to measure td,on and tr. For an Rg,on of 22Ω, the

measured td,on is 270 ns, and the measured tr is around 50 ns as seen from Fig. 6.

Fig.7 Gate-drive current [22V:1A] during turn-on with Rg,on=22Ω.

The collector-emitter voltage (Vce) fall times, tfv1 and tfv2, illustrated in Fig. 1, are

usually not specified in the datasheet. But the interval tfv1 is useful for switching loss calculation,

since collector-emitter voltage is still significant during this interval. The interval tfv2 completes the

turn-on transition. If this interval is too long and Vce is not low enough, the Vce sensing circuit

could sense this as a short-circuit, leading to nuisance trip. The blanking time has to be significantly

13
higher than the total turn-on transition time (including tfv2) to avoid such nuisance trip. As the

device voltage reduces to very close to Vce,sat by the end of the Miller Plateau region [10], the

duration of the Miller Plateau can be taken as (tfv1+tfv2). From the captured waveform (Fig. 6), the

measured (tfv1+tfv2), or the total time duration of the Miller plateau region, is around 800 ns. It is

seen that the complete turn-on time of the device is 1120 ns for a gate resistance of 22Ω.

The gate current during turn-on is presented in terms of the voltage across the gate

resistance Rg,on in Fig. 7. Theoretically, the peak current is expected to be 30V/22Ω =1.36 A.

However, the measured peak value is around 0.93A. One could observe a pulse of high gate current

for a duration of around 300 ns, which is effectively the sum of turn-on delay time and collector

current rise time. As in Vge, oscillations are observed in the Miller plateau region. In this region, the

measured gate current is very close to its theoretical value, i.e., (15-10)/22 ≅ 0.2A.

(a) (b)
Fig. 8 (a) Turn-on characteristics of IGBT with Rg,on=10Ω (Channel-1: Vge [5 volts/div], Channel-2:
Vce [250 volts/div], horizontal axis: 500ns/div)
(b) Turn-on characteristics of IGBT with Rg,on= 47Ω (Channel-1: Vge [5 volts/div], Channel-
2: Vce [250 volts/div], horizontal axis: 500ns/div)

Table II: Measured turn-on switching intervals for different values of gate resistance.

Rg, Ω td,on, ns tr,on , ns (tfv1+tfv2) , ns Total Turn-on time, ns

10 150 40 600 790
22 270 50 800 1120
27 380 50 900 1330
47 500 60 1450 2010

14
 An experimental study is carried out on the variation of various switching times with

Rg,on. Fig. 8(a) and Fig. 8(b) show the turn-on characteristics of the device with gate turn-on

resistances of 10Ω and 47Ω, respectively. The various measured switching intervals are presented

in Table-II. It is seen that the switching intervals during turn-on greatly depend on gate resistance.

In particular, td,on and (tfv1+tfv2) increase significantly with increase in gate resistance. The total

turn-on time, which is effectively the time interval between the instant when Vge starts to increase

from -15V and the instant when Miller plateau ends, also increases with increase in gate turn-on

resistance. When the total turn-on transition time becomes close to the blanking time, the chances

of nuisance trip increase. In fact, increase in the nuisance trip with increase in Rg,on has already

been reported based on experimental study in an earlier publication [1].

It is also observed that the initial spike, when gate-emitter voltage starts rising from -

15 V, is less for 47Ω of gate resistance compared to 10Ω of gate resistance. Similarly the three

slopes observed between Vge=-15V and Vge= Vge,I0, are also reduced with increase in Rg,on. The

oscillation in the Miller plateau region decreases significantly with increase in gate resistance as

seen from Fig. 8.

5.2 Turn-off characteristic:

Fig. 9 and Fig. 10 show the experimental turn-off characteristics of the IGBT. The

gate-emitter voltage Vge and the collector-emitter voltage Vce during turn-off are shown in Fig. 9,

while Fig. 10 shows the gate current during turn-off.

Theoretically, the Vge is expected to decrease exponentially as in a first order

system [10]. However, there are two distinct stages seen during the reduction of Vge from +15 V to

the Miller plateau value of Vge,I0 [7]. Fig. 9 shows a very steep slope (for 30 ns approximately),

followed by a relatively lower slope for 100 ns approximately. During the first slope, spikes are

seen due to parasitic elements.

In the Miller plateau region, the Vge observed is about +7 V as against the datasheet

value of +10 V. As discussed in section 5.1, the Miller plateau voltage is low due to low collector
15
current. After the Miller plateau region, there are some oscillations in Vge as it goes negative. These

oscillations decrease with increase in Rg,off as shown later in this section. Since these oscillations are

well below the threshold voltage, these do not affect the turn-off process.

Fig. 9 Turn-off Characteristics of IGBT with Rg,off=22Ω (Channel-1: Vge [5 volts/div] vs. time,
Channel-2: Vce [250 volts/div], horizontal axis: 500ns/div)

The turn-off transition is also characterized by four switching intervals, namely turn-

off delay time (td,off), collector-emitter voltage rise time (trv), and collector current fall times (tfi1 and

tfi2), as illustrated in Fig. 2. Out of these intervals, td,off and tfi1 (which is usually denoted as tf) are

very important, and are usually specified in the datasheet [6].

According to [7] and [8], the turn-off delay time (td,off) is defined as the time

interval, measured from the instant when the gate voltage is 90 % of its initial value to the instant

when the collector current is 90 % of its initial value (before the transition). The fall time (tf) is

defined as the time interval during which the collector current reduces from 90 % to 10 % of its

initial value [7, 8]. One practice is to connect the points at which the collector current is 90% and

60% of its initial value on the current oscillogram by a straight line, and extend it to 10% of the

initial value. The duration over which this straight line falls from 90% to 10% is regarded as the fall
16
time [8].Alternatively, according to [10], the turn-off delay time (td,off) is defined as the time

interval between the instant when Vge starts decreasing and the instant when Vce starts to rise. The

collector-emitter voltage rise time (trv), which is a part of td,off as per [7] and [8], is defined in [10]

as the time interval during which the collector voltage rises from Vce,sat to the full dc bus voltage.

The turn-off delay time (td,off) observed is around 300 ns, and trv is around 400 ns, for Rg,off=22Ω.

After the voltage rises to its full value, the collector current starts falling with

different slopes during two different intervals (tfi1 and tfi2) as shown in Fig. 2. These intervals tfi1

and tfi2 are important for switching loss calculation. Also, the total turn-off time depends on these

two parameters. As the device current cannot be sensed, the current fall times (tfi1 and tfi2) cannot be

measured individually. However, the total current fall time (tfi1 + tfi2) can be measured as the time

interval starting from the instant when Vce rises to its full dc bus voltage to the instant when Vge

goes to -15V. From Fig. 9, the measured total current fall time is 1.6 µs and the turn-off process is

completed within 2.3 µs.

Fig.10 Gate-drive current [22V:1A] during turn-off with Rg,off=22Ω

17
 The gate current during turn-off is presented in terms of the voltage across turn-off

gate resistor, Rg,off, as shown in Fig. 10. The peak gate turn-off current is 0.98 A, while it is

expected to be 1.36A. Theoretically, gate turn-off current at Miller Plateau is [10-(-15)]/22= 1.14A,

but the measured current is around 0.84A.

(a) (b)

Fig. 11 (a) Turn-off characteristics of IGBT with Rg,off=10Ω (Channel-1: Vge [5 volts/div],
Channel-2: Vce [250 volts/div], horizontal axis: 500ns/div)
(b) Turn-off characteristics of IGBT with Rg,off=47Ω (Channel-1: Vge [5 volts/div], Channel-2: Vce
[250 volts/div], horizontal axis: 500ns/div)

Table III: Measured turn-off switching intervals for different values of gate resistance.

R g, Ω td,off , ns trv,off, ns (tfi1+tfi2), ns Total Turn-on time, ns

10 200 250 1300 1750
22 300 400 1600 2300
27 400 380 2200 2980
47 600 410 3300 4310

As in turn-on transition, the variation of various switching times with Rg,off during

turn-off transition is also studied experimentally. Fig. 11(a) and Fig. 11(b) show the turn-off

characteristics of the device with gate turn-off resistances of 10Ω and 47Ω, respectively. Table-III

presents the various switching time intervals for different values of gate turn-off resistances,

namely 10Ω, 22Ω, 27Ω and 47Ω. It is seen that the switching intervals during turn-off vary with

variation of gate turn-off resistance, Rg,off. The various switching times along with total turn-off

time (time taken to fall Vge from +15 V to -15 V) increase with increase in gate turn-off resistance,

Rg,off. The magnitude of the initial spike, when gate-emitter voltage starts falling from +15 V,

18
decreases with increase in gate turn-off resistance as seen from Fig. 11. Also, with increase in gate

resistance, there is some reduction in the oscillations when Vge goes to negative value.

The measured switching times tally reasonably well with the values indicated in

datasheet for Rg=22Ω both during turn-on and turn-off.

6. Test under short-circuit condition:

Short-circuit protection scheme is concerned with the protection of the entire system

by switching off the power transferring devices within the maximum allowable time for which the

devices can carry the short-circuit current.

The IGBT can be subjected to two types of faults. A fault can occur when the device

is conducting, and this is called fault under load (FUL). In the other case, the IGBT is gated on into

a fault. This is known as hard switched fault (HSF). A device has to be protected from both types of

faults, i.e., FUL and HSF. The fault is detected by ‘de-saturation technique’ as explained in section

3.3.

6.1 Hard switched fault:

The experimental set-up is shown in Fig. 6. The load is a coil of 60Ω resistance.

With the gate pulses turned off, the dc bus is charged to 600V, and the manual switch SW is closed

to short the load. The gate pulses are then turned on. Now, the device turns on into a short-circuit.

When the gate pulse goes high, a blanking time is provided as discussed in section-

3.4. During this blanking time, any fault is ignored and the status signal is maintained high. The

blanking time should be higher than the device turn-on time and lower than 10 µs as shown in (1).

(Tturn − on + Tdg ) < Tblank < 10µs − ( Tturn − off + Tdg ) (1)

Where, Tturn-on =Total turn-on time of the device

Tdg = Gate-drive circuit delay

Tblank = Blanking time

Tturn-off =Total turn-off time of the device

19
 Fig. 12 Voltage across gate and emitter terminal, Vge, with collector terminal left open.

Fig. 12 shows the voltage across the gate and emitter terminals when the collector voltage

sensing terminal of the gate-drive card (C’ of Fig. 4(a)) is kept open. The time interval starting from

the instant when Vge starts rising from -15V to the instant when Vge starts decreasing from +15V is

the blanking time. As seen from Fig. 12, the drive circuit is set to provide a blanking time of 4.5 µs.

In the event of a HSF, the gate voltage is turned off soon after the blanking interval as seen

from Fig. 12 to Fig. 14. Fig. 13 and Fig. 14 present the transients under short-circuit condition with

Rg = 22Ω and Rg = 47Ω, respectively.

Fig. 13(a) shows the measured Vge and the voltage across the device during short-circuit.

The corresponding measured voltage across the shorting switch SW is shown in Fig. 13(b). As the

device is turned on into a fault and the short-circuit protection scheme is disabled during the

blanking time, the gate-drive circuit does not respond to the fault immediately. During the blanking

time, the device is on and the current through the device increases. The voltage across the device

(Vce) decreases initially, but subsequently starts increasing due to the fault as seen from Fig. 13(a).

20
As Vce is greater than the reference voltage (6.2 volts), the gate-drive circuit senses a fault and the

gate voltage is turned off soon after the blanking time ends.

When Vge is reducing, an over-voltage spike is observed in the device voltage Vce due to

high di/dt and stray inductance in the power circuit. Once Vge becomes low, the device voltage is

equal to the dc bus voltage, and the switch is totally off.

Fig. 13 (a) Turn-off transient under short-circuit condition (HSF) when Rg,off = 22Ω. (Channel-1:
Vge [10 V/div], Channel -2: Vce [250 V/div], horizontal axis: 1µs/div)

Fig. 13(b) shows the measured Vge and the voltage across the shorting switch, Vsw,

during the short-circuit. The shorting switch presents itself as an inductance Lsw to the short-circuit

current. Hence the voltage across the switch essentially indicates the rate of change of the short-

circuit current. The current rises at a fast rate, and eventually saturates in a few microseconds.

Fig. 13(b) shows that Vge starts decreasing after around 4.5 µs. The time taken to turn off

the device after the fault is detected is approximately 1.5 µs. The total time taken to make Vge = -15

volts from the turning on instant is approximately 6 µs, which is quite less than the short-circuit

current withstand time (10 µs) of the IGBT.

21
 Fig. 13(b) Turn-off transient under short-circuit condition (HSF) when Rg,off = 22Ω. (Channel-1:
Vge [20 volts/div], Channel -2: voltage across shorting switch, SW [50 volts/div], horizontal axis:
1µs/div)

A few hundred of microseconds after the pulse is made low, the measured Vge is seen to be

increasing for a short while, before eventually settling down to -15V, as shown by Fig. 13(a) and

Fig 13(b). In other words, the device tends to re-turn on while being switched off after the detection

of fault. This is due to the consequently high dv/dt of the collector-emitter voltage and

displacement current flows through the gate-collector capacitance, which increases the gate-emitter

voltage [7].

The same experiment is carried out with a gate resistance of 47Ω. The results are presented

in Fig. 14(a) and Fig. 14(b). The tendency of the device to re-turn on is very much reduced now.

But the complete turn-off time of the device after fault is detected is 3 µs, which is higher than that

with a gate turn-off resistance of 22Ω. The over-voltage spike is also very much reduced now.

22
Fig. 14(a) Turn-off waveform under short-circuit condition (HSF) when Rg,off = 47Ω. (Channel-1:
Vge [10 volts/div], Channel -2: Vce [1000 volts/div], horizontal axis: 1µs/div)

Fig. 14(b) Turn-off waveform under short-circuit condition (HSF) when Rg,off = 47Ω. (Channel-1:
Vge [10 volts/div], Channel -2: voltage across shorting switch, SW [50 volts/div], horizontal axis:
1µs/div)

23
6.2 Fault under load:

This experiment is conducted on the same test set up, shown in Fig. 5. Initially the

SW switch is kept ‘OFF’. When the IGBT (upper) is in conduction, the SW switch is closed, and

the load is shorted. The short-circuit causes the collector current to increase steeply, with a di/dt

determined by DC-link voltage Vdc and the inductance of the short-circuit loop.

Fig. 15(a) shows the transients in Vge and Vce during FUL for a gate resistance of

22Ω. As the fault has been created during the on period of the device, the gate-drive circuit does

not have to wait due to blanking time to react. Soon after the fault is created, Vce increases rapidly.

When Vce increases beyond the reference voltage set in the circuit (6.2V), the gate-drive circuit

senses a short-circuit, and switches the device off as seen from Fig. 15.

When the device is being switched off, an over-voltage spike is seen in the Vce

waveform before it settles down to the dc bus value. This over-voltage spike is due to fast change in

current and stray inductance in the power circuit.

Fig. 15(a) Turn-off waveform under short-circuit condition (FUL) when Rg,off = 22Ω. (Channel-1:
Vge [10 volts/div], Channel -2: Vce [1000 volts/div], horizontal axis: 500ns/div)

24
Fig. 15(b) Turn-off waveform under short-circuit condition (FUL) when Rg,off = 22Ω. (Channel-1:
Vge [10 volts/div], Channel -2: voltage across shorting switch, SW [250 volts/div], horizontal axis:
500 ns/div)

Fig. 15(b) shows the measured Vge and the voltage across the shorting switch SW

(Vsw) during the short-circuit test with a gate resistance of 22Ω. During the pre-fault condition, the

voltage across switch (SW) equals the dc bus voltage. The moment fault is created, Vsw reduces

sharply to a low value as shown by the oscillogram. From this instant, it takes around 2µs for Vge to

change it from +15 V to -15 V. This is much less than the IGBT’s short-circuit current withstand

time of 10 µs.

Fig. 16(a) presents the transients in Vge and Vce with a gate resistance of 47Ω, and

the transients in Vsw and Vge are shown in Fig. 16(b). The magnitude of the over-voltage spike in

the Vce transient, before it settles down to the dc bus voltage, is less for higher value of gate turn-off

resistance as seen from Fig. 15(a) and Fig. 16(a). It is observed that, in case of 22Ω gate turn-off

resistance, the overshoot in Vce is around 400 volts, while it is around 250 volts for an Rg,off of

resistance is 47Ω.

25
Fig. 16(a) Turn-off waveform under short-circuit condition (FUL) when Rg,off = 47Ω. (Channel-1:
Vge [10 volts/div], Channel -2: Vce [1000 volts/div], horizontal axis: 500ns/div)

Fig. 16(b) Turn-off waveform under short-circuit condition (FUL) when Rg,off = 47Ω.
(Channel-1: Vge [10 volts/div], Channel -2: voltage across shorting switch, SW [500 volts/div],
horizontal axis: 1µs/div)

26
 The total turn-off time increases with increase in gate turn-off resistance as seen

from Fig. 15(b) and Fig. 16(b). The total turn-off time for the latter case is approximately 3 µs.

As in the case of HSF, there is a possibility of re-turning on of the device while

being switched off after detection of a fault under load (FUL) as well. This is seen from the

measured Vge presented in Fig. 15 and Fig. 16. Again, as with HSF, the possibility reduces with

increase in gate turn-off resistance as seen from experimental results in Fig. 15 and Fig. 16.

7. Conclusion:

An IGBT gate-drive circuit is designed, fabricated and tested. The drive circuit has

the capability to protect an IGBT from short-circuit condition and under-voltage (gate-emitter

voltage) condition. The drive circuit presented will be helpful to students and practicing engineers,

building a voltage source inverter or any other power converter using IGBTs. The circuit can also

serve as a reference design for development of drive circuits for IGBT’s of different ratings.

The driver circuit is tested on a SEMIKRON SKM75GB123D half-bridge module,

operated in the chopper mode with a DC bus voltage of 600 V. Since there are practical difficulties

in sensing the device current, particularly due to the sandwich bus-bar structure of inverters, a test

procedure that does not require any sensing of current is presented. A reasonable measurement of

the various intervals in switching transition is possible, simply based on the measured gate-emitter

and collector-emitter voltages, and without the measured collector current. The test results under

normal condition and short-circuit condition are presented. The short-circuit test results clearly

demonstrate the capability of the drive circuit to protect the device against both hard switched fault

and fault under load. Further, the effect of gate resistances on switching transients during normal as

well as fault conditions is studied experimentally. The results of short-circuit test indicate that it is

better to use comparatively higher values of gate resistance to turn off a device under fault than the

gate resistance used under normal condition.

27
References:

[1] G. Narayanan, S. R. Murulidhara, A. S. Anand and V. Ramanarayanan, “Protection of insulated

gate bipolar transistors against short circuit,” special Issue on Power Electronics at IISc-2, Vol.

80, no. 5, September- October 2000.

[2] Chokhawala. R, Catt J and Pelly. B., “Gate drive consideration for IGBT modules”, IEEE-IAS

’92 conference Rec., 1992, Houston, Texas, pp. 1186-1195

[3] Chokhawala. R, Catt J and Kiraly. L., “A discussion on IGBT short circuit behaviour and fault

protection schemes”, IEEE-APEC’93 conf. Rec., 1993, san Diego, California, USA, pp.393-401

[4] Vinod John, Bum-Seok Suh, and Thomas A. Lipo, “Fast-Clamped Short-Circuit Protection of IGBT’s”,

IEEE Transaction on Industry Apllications, vol. 35, no. 2, March/April 1999

[5] P. K. Nandi, “Study of short circuit performance of IGBT and development of base drives for

IGBT”, ME thesis, Dept. of EE, IISc, January 1995.

[6] Datasheet: SKM75GB123D, Semikron International, URL: www. semikron.com

[7] Application manual: IGBT and MOSFET power modules, Semikron International

[8] Björn Backlund, Raffael Schnell, Ulrich Schlapbach, Roland Fischer and Evgeny Tsyplakov,

“Application Note: Applying IGBTs”, ABB Switzerland Ltd, April 2009

[9] Datasheet: HCPL-316J, Avago Technologies, URL: www. avagotech.com

[10] Ned Mohan, Underland, and Robbins, “Power Electronics: Converters, Applications and

Design”, 3rd edition, John Wiley publications, pages 626-640

[11] Datasheet: HCPL-3101, Agilent (Hewlett Packard), URL: www.datasheetcatalog.com

/agilent(hewlett-packard)

[12] Datasheet: MIC4429/4420, Micrel, URL: www.micrel.com

[13] Datasheet: WIMA Capacitor, Wima, URL: www.wima.com

[14] Datasheet: LM339; National Semiconductor, URL: www.national.com

[15] K. S. Bhanuprasad, “Drive and protection circuit for high current IGBT”, ME thesis, Dept. of

EE, IISc, July 2006.

[16] Datasheet: IRFZ44, International Rectifier, URL: www.irf.com

28
[17] Datasheet: TL494, Texas Instrument, URL: www.ti.com

[18] Datasheet: LM7815, Fairchild Semiconductor, URL: www.fairchildsemi.com

[19] Salvatore Musumeci, Angelo Raciti, Antonio Testa, Agostino Galluzzo, and Maurizio Melito,

“Switching-Behavior Improvement of Insulated Gate-Controlled Devices”, IEEE Transaction on Power

Electronics, vol 12, no. 4, July 1997

29