Deshdeepak Nautiyal

Contact No: +91-9591183105 Email:deepakn97@gmail.com

Synopsis

VLSI Hardware Engineer with substantial experience of RTL verification for complex ASIC
products. Main areas include,
➢ Experience of development of coverage-driven constrained random test environments at IP
,subsystem and SOC level
➢ Experience in Verification planning, test planning and coverage closure
➢ Sound Understanding and experience in verifying various complex protocols such as
ARM architecture ,DDR ,SATA and AMBA ACE ,based ASICs
➢ Good knowledge of System Verilog (SV), UVM, based component, sequences, cover
groups, checkers.
➢ Good experience of Veloce Emulation flow

Work Experience

April 2017 – Present: Qualcomm India Private Limited, Noida

Senior Engineer, Data Center Server SOC verification Group.

August 2015 – April 2017: Mentor Graphics India Private Limited, Noida
Senior member of technical staff, Veloce Emulation Transactor Group.

October 2012 – August 2015: Sankalp Semiconductor Private Limited, Bangalore

Verification Engineer, Digital Business Unit

Overall Experience of 5 Yrs 6 Months in the field of Digital Frontend Verification.

Core Skills

HVLs : System Verilog , UVM

HDLs : Verilog
Protocol : AMBA ACE, AXI4 , DDR3, DDR4, DFI 3.0, DFI 4.0, SATA
Software Languages : C,C++
EDA Tool : Questa ,Ncsim (Cadence) , and VCS
Emulation tools : Veloce (Mentor Graphics)
Scripting language : Shell,Perl,Make
Operating system : Linux,Unix,Windows

Projects Experience

1) Verification of Centriq Server SOC.

Language: System Verilog, UVM, C based environment
Tools used: VCS Simulator ,Vplanner
Duration: April 2017 – Present

Description:Centriq is ARM based multicore chip ,having ARM-v8 based 82 processing cores
,One Boot core and one Debug processor core, PCIE ,USB ,Ethernet ,DDR etc connected 34
subsystems and ARM coresight based debug architecture
.
Roles & Responsibilities :
A) Server debug subsystem ( SDSS) SOC verification :

➢ Understanding specification of SDSS (Server debug subsystem).

➢ Defining and implementing verification plan and testplan
➢ Worked on Debug and config access (DAP), Interrupts ,Trace ,trigger ,reset and clock
architecture verification.
➢ Developing UVM based self-checking environment.
➢ I was the only person responsible for this task and achieved this objective before
the deadline.

B) Debug features verification of Complete SOC :

➢ Understanding specification of all debug component (e.g DAP ,CTI ,TPIU, ETB and
ETR ) in each subsystem
➢ Defining and implementing verification plan and testplan
➢ Writing self checking C based tests to verify Trigger network built on ARM
coresight Cross trigger interface across on SOC
➢ Verifying ATB Trace ,QATB trace ,generic trace ,source to sink verification
➢ Verifying Debug and config access initiated from boot processor in different
addressing mode to all subsystems
➢ Wrote test cases and checkers for ROM table verification .
➢ I was one of the two person responsible for complete Debug verification on this
complex chip .

2) Verification of ACE Transactor

Language: System Verilog, UVM,
Tools used: Veloce Emulator ,Questa .`
Organization: Mentor Graphics India Pvt Ltd, Noida
Duration: May 2015 – October 2015

Description:ACE, defined as part of the AMBA 4 specification, extends AXI with additional
signaling introducing system wide coherency. This transactor a behavioral model of ACE master
,was having in built software based cache memory and hardware synthesizable ACE transactor .

Roles & Responsibilities

➢ Understanding Coherency and Cache memory concepts in ARM architecture.
 ➢ Defining and implementing verification plan and verification environment
architecture
➢ Generating AXI transaction and snoop transaction based test cases ,causing change
in cache states ,coherency .
➢ Developing UVM based self-checking environment for this transactor.
➢ Generate various IP level and system level test suite
➢ Provide customer support for various issues/features

3) Verification of AMBA Emualtion Transactors

Language: System Verilog, UVM
Tools used: Veloce Emulator ,Questa and VCS
Organization :Mentor Graphics India Pvt Ltd,Noida
Duration :August 2015 – April 2017

Description:The ARM Advanced Microcontroller Bus Architecture (AMBA) is an open-standard,

on-chip interconnect specification for the connection and management of functional blocks in
system-on-a-chip (SoC) designs. My responsibilities include IP level and system level verification
of various AMBA protocol transactors ,including AXI4 Master ,AXI4 slave ,ACE master ,ACELITE
master.

Roles & Responsibilities

➢ Development of Testplan and verification Plan
➢ Definingand implement verification environment
➢ Writing unified UVM-SV based environment which will support both simulation and
emulation
➢ Generate various IP level and system level test suite
➢ Provide customer support for various issues/features

4) Verification of DDR Controller PHY (CPHY)

Language: System Verilog, UVM
Tools used: NCSIM, Questa and VCS
Organization :For RAMBUS chip technology (Customer site from Sankalp Semiconductor )
Duration :Feb 2015–August 2015

Description: This DDR CPHY is a multi modal PHY, supports 4 DDR protocols (DDR3,
DDR4,LPDDR3 and LPDDR4) from the channel side and also supports DFI 2.1.1 , DFI 3.1 and DFI
4.0 protocols from the memory Controller side .

Roles & Responsibilities

➢ Development of Register abstraction layer for CPHY
➢ Writing sequences and testcases for different power states of CPHY.
 ➢ Miscellaneous feature verification including burst read/write, burst chop feature,
and frequency change feature.

5) Timing Verification of Single Port SRAM memory model

Language: System Verilog ,UVM
Tools used :NCSIM ,Questa,and VCS
Customer :ST Microelectronics Greater Noida, (Customer site from Sankalp Semiconductor )
Duration :Sept 2014 –January 2015

Description: Single port SRAM is a high speed embedded memory with inbuilt Scan chains ,BIST
functionalitiesand redundancy at the architectural level.

Roles & Responsibilities

➢ Created testplan
➢ Was involved in planning of the novel architecture for timing based verification
environment using SV UVM.
➢ Developed UVC components Driver ,Monitor and sequencer
➢ Was involved in writing functional coverage subscriber.

6) Functional Verification of Dual port SRAM memory model

Language: System Verilog ,UVM
Tools used : NCSIM ,Questa,and VCS
Customer: ST Microelectronics ,Greater Noida , (Customer site from Sankalp Semiconductor )
Duration : May 2014 –August 2014

Description: DPHD RAM is a dual port high density static RAM ,which also supports DFT
features such as BIST ,Scan Chains and Scan Bypass other than memory read write operations .

Roles & Responsibilities

➢ Created testplan
➢ Wrote UVM sequences to generate various scenarios such as contention,
redundancy, bypass and test mode etc.
➢ Developed UVC component Driver, Monitor and Sequencer.
➢ Developed Scoreboard checker.
➢ Developed Shell script for automatic generation of scan chains for different cuts and
configuration.

7) Verification of SATA Host Controller Adapter

Language: System Verilog ,UVM,UVM register model
Tools :NCSIM and Questa
Customer: Sankalp & KPIT Semiconductor in house product
Duration: October 2012-Dec 2013

Description:SATA Host Controller Adapter is 1st generation SATA controller which works on 1.5
Gbit/s-150 MB/s .The SATA host adapter supports an OCP configuration bus and DMA Interface
on CPU side,while a single SATA port on device side. SATA port can plug third party PHY layer
and can be connected via this PHY to the SATA device (optical disk or drive).

Roles & Responsibilities

➢ Extracted features and Created Verification plan, Test Plan and coverage plan
➢ Developed UVM based register model.
➢ Developed SV assertions for Link Layer Primitives.
➢ Register model based Coverage and scoreboard.
➢ Developed sequences and test cases to generate interesting scenarios.
➢ Regression, functional and code coverage closure.

Education

Education College / School Discipline Academic year Percentage

Bachelors of GBPEC, Pauri Garhwal Electronics & 2008-2012 71.94

Technology under Uttarakhand Communication
Technical University
Intermediate G.G.D.S.V.M. , 2007 84.6
Uttarkashi,
Uttarakhand
High school G.G.D.S.V.M. , 2005 82.3
Uttarkashi,
Uttarakhand

Personal Details

Name : Deshdeepak Nautiyal

Father’s Name : Mr. Nagendra Dutt Nautiyal
Date Of Birth : July 5, 1991
Address : V-602 suprectech Ecocity sector 137 Noida
Nationality : Indian
Languages : English, Hindi
Hobbies : Creative Writing
Marital Status : Married

Declaration
I hereby declare that all the information furnished above is true to the best of my knowledge
and belief.
Deshdeepak Nautiyal