REG.

NO:

M.E./M.TECH. DEGREE EXAMINATIONS 2017 – ‘18

M.P.NACHIMUTHU M.JAGANATHAN ENGINEERING COLLEGE

An ISO 9001:2008 Certified Institution
CHENNIMALAI, ERODE – 638 112.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
INTERNAL TEST – II
M.E. VLSI DESIGN

Subject: AP5094 & Signal Integrity for High Speed Design Semester: II
Date : Branch: VLSI Design
Time : 1Hour 30 Minutes Maximum: 50 Marks
Answer ALL Questions
PART – A (10 x 2 = 20 Marks)

1. Define return path.

2. How to cross a gap in return path?
3. Differentiate SSN/SSO.
4. Define skin effect.
5. What is inter symbol interference?
6. Mention the effect of ISI on signal integrity.
7. How to minimize the effect of ISI?
8. Define differential signals.
9. How to calibrate one port measurement?
10. Define IBIS model.
PART - B (3 x 10 = 30 Marks)

11. a. Describe in detail about s-parameters and their measurements. (10)

(or)
b. Differentiate common mode analysis and differential mode analysis. (10)
12 a. Discuss in detail about SSN/SSO. (10)
(or)
b. (i) Discuss intersymbol interference. (5)
(ii)Explain mutual inductance-how connectors create cross talk. (5)
13. a. Describe in detail about series inductance –how connector create EMI. (10)
(or)
b. Explain clock jitter and how it measures.

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