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5 4 3 2 1

2012 S-Series Richie 13.3"


D

UMA/DIS Muxless Schematic D

Intel Chief River Platform


C
Ivy Bridge (rPGA989) C

Panther Point PCH

B REV:-1 B

2012-03-15

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DY:No stuff Title

Cover Page
DIS_PX:Only DIS install Size
A4
Document Number Rev
2012 S-Series Richie 13.3 -1
Date: Wednesday, March 14, 2012 Sheet 1 of 103
5 4 3 2 1
5 4 3 2 1

S-Series Richie Block Diagram SYSTEM DC/DC


TPS51461RGER
INPUTS OUTPUTS
48
CPU DC/DC
ISL95832HRTZ
INPUTS OUTPUTS
42~44

DCBATOUT +VCCSA DCBATOUT VCC_CORE

(Muxless) VRAM
128MBx16 884
VRAM
128MBx16 894
SYSTEM DC/DC
TPS51211DSCR 45

D
INPUTS OUTPUTS D

DDR III Slot 0 GDDR5 GDDR5 DCBATOUT 1D05V_S0


DDRIII 1600/1333 Channel A
1600/1333 14 Intel CPU SYSTEM DC/DC
Ivy Bridge-M TPS51123RGER 41
Project code:91.4RS01.001
DDR III Slot 1 DDRIII 1600/1333 Channel B Dual Core SV INPUTS OUTPUTS
1600/1333 15 35W PCIe x 16
Thames Pro PCB P/N:11241 5V_AUX_S5
3D3V_AUX_S5
4,5,6,7,8,9,10
18W S3 Package DCBATOUT 5V_S5
3D3V_S5
83,84,85,86,87

X8501 SYSTEM DC/DC


FDI*2 DMI2.0*4 27MHz TPS51216RUKR 46

RGB CRT
2.7GT/s 5GT/s INPUTS OUTPUTS
1D5V_S3
DCBATOUT 0D75V_S0
DDR_VREF_S3

GFX DC/DC
USB3.0 x 3 USB3.0 CRT ISL95832HRTZ 42~44
62 RGB CRT 50
C C
INPUTS OUTPUTS
FingerPrinter DCBATOUT VCC_GFXCORE
64
USB 2.0 INTEL HDMI
HDMI 1.451
VGA
PCH UP1527QQDD 92
USB2.0 x 1 61 LCD INPUTS OUTPUTS
Panther Point-M LVDS 49
DCBATOUT VGA_CORE
X1701
CAMERA 32.768KHz CHARGER
49 PCB 8 LAYER BQ24736RGRR 40
SMBus
Thermal Sensor
L1: Top INPUTS OUTPUTS
Mini-Card GMT G781 28
X1801 USB 3.0/2.0/1.1 ports (14) GND AD+
SIM Card 54
L2: BT+ DCBATOUT
54
WWAN 25MHz ETHERNET (10/100/1000Mb) L3: Signal 26
High Definition Audio SATA II 6Gb/s
HDD 56 L4: Signal
SYSTEM DC/DC
JMicron RT8068AZQWID 47
SD/MMC/MS PCIE Serial Peripheral I/F(dual output) L5: VCC
33
JMB709 32
INPUTS OUTPUTS
ACPI 1.1 L6: Signal
LPC I/F SATA II 6Gb/s
ODD 56 3D3V_S5 1D8V_S0
B L7: GND B
LAN SATA ports (6) L8: Bottom SYSTEM DC/DC
RJ45 CONN Realtek 8151FH PCIE
93
PCIE ports (8) FDMC7696
35 10/100/1000 34 LPC Bus INPUTS
26 OUTPUTS
X3401
1D5V_S3 1V_VGA_S0
25MHz
XDP
26 SPI/PECI Switches
KBC
INPUTS OUTPUTS
1D5V_S3 1D5V_S0
17,18,19,20,21,22,23,24,25 SPI
SMSC KBC1126 27 5V_S5 5V_S0
INT MIC AUDIO CODEC HD Audio 3D3V_S5 3D3V_S0
31
Pre-AMP IDT92HD87
PCB LAYER
USB2.0

PCIe

SMBus

EXT MIC 29
TLV2462
31 30
L1:Top L5:Vcc
SPI Flash L2:GND L6:Signal
Headphone L3:Signal L7:GND
31 8MB 60 Battery Touch Int.
L4:Signal L8:Bottom
A Mini-Card Pad KB <Core Design> A
39 69 69
Speaker WLAN
802.11abg/n
Accelerometer Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
HP3DC2 65 Taipei Hsien 221, Taiwan, R.O.C.
31 Blue Tooth
53 Title

Block Diagram
Size Document Number Rev
A3 -1
2012 S-Series Richie 13.3
25 Date: W ednesday, March 14, 2012 Sheet 2 of 103
5 4 3 2 1
5 4 3 2 1

PCH Strapping Chief River Schematic Checklist Rev0.72


Processor Strapping Chief River Schematic Checklist Rev0.72
Pin Name Strap Description Configuration (Default value for each bit is Default
Name Schematics Notes 1 unless specified otherwise) Value
SPKR The signal has a weak internal pull-down.
Note: the internal pull-down is disabled after PLTRST# deasserts. If the signal is sampled high, this indicates that the system is
strapped to the "No Reboot" mode (Cougar Point will disable the TCO Timer system reboot feature). Connect a series 1K ohm resistor on the critical CFG[0] trace in a manner
CFG[0] which does not introduce any stubs to CFG[0] trace. Route as needed
This signal has a weak internal pull-up.
INIT3_3V# Note: The internal pull-up is disabled after PLTRST# deasserts. from the opposite side of this series isolation resistor to the debug port.
NOTE: This signal should not be pulled low. Leave as "No Connect". ITP will drive the net to GND.
D D
Integrated 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when high CFG[2] PCIe Static x16
NOTE: This signal should always be pulled high CFG2 is for Lane Numbering 1: Normal Operation; Lane # definition matches socket pin map definition
INTVRMEN External 1.05 V VRM Enable / Disable. Integrated 1.05 V VRMs is enabled when Low. 0:Lane Reversed
the 16x Reversal. 1
NOTE: This signal should be pulled down to GND through 330 kOhms resistor
1:Disabled - No Physical Display Port attached to Embedded DisplayPort
GNT3#/GPIO55 Display Port 0:Enabled - An external Display Port device is connected to the Embedded
GNT2#/GPIO53 GNT[3:0]# functionality is not available on Mobile. Used as GPIO only. Pull-up resistors are not required on these signals. If CFG[4] Presence strap
pull-ups are used, they should be tied to the Vcc3_3 power rail. Display Port Pull down to GND through a 1KΩ ± 5% resistor to enable port 1
GNT1#/GPIO51
This signal is a strap for selecting DMI and FDI termination voltage.
For Ivy Bridge processor only implementation: 00 = 1 x 8, 2 x 4 PCI Express
DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms ±5% resistor. CFG[6:5] PCIE Port Bifurcation 01 = reserved
DF_TVS Straps 11
For future processor compatibility: 10 = 2 x 8 PCI Express
It needs to be connected to PROC_SELECT through a 11 = 1 x 16 PCI Express
1.0 kOhms ±5% series resistor. The PROC_SELECT signal would need a 2.2 kOhms ±5% pull-up resistor to PCH VccDFTERM.
Reserved configuration
This Signal has a weak internal pull-up. CFG[17:7] lands. A test point may
Note: the internal pull-up is disabled after PLTRST# deasserts. This field determines the destination of accesses to the BIOS
memory range. Also controllable via Boot BIOS Destination bit (Chipset Config Registers: Offset 3410h:Bit 10). This strap is used
be placed on the board
in conjunction with Boot BIOS Destination Selection 1 strap. for these lands.
Bit11 Bit 10 Boot BIOS Destination
0 1 Reserved
SATA1GP/ 1 0 PCI Voltage Rails
GPIO19 1 1 SPI POWER PLANE VOLTAGE DESCRIPTION
0 0 LPC ACTIVE IN
5V_S0 5V
NOTE: If option 00 LPC is selected BIOS may still be placed on LPC, but all platforms with Cougar Point require SPI flash 3D3V_S0 3.3V
C connected directly to the Cougar Point's SPI bus with a valid descriptor in order to boot. 1D8V_S0 1.8V C

NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or via Boot 1D5V_S0 1.5V
1D05V_S0 1.05V
BIOS Destination Bit will not affect SPI accesses initiated by Management Engine or Integrated GbE LAN. VCCSA 1.0V S0 CPU Core Rail
NOTE: PCI Boot BIOS destination is not supported on mobile. 0D75V_S0 0.9 - 0.675V Graphics Core Rail
VCC_CORE 0.75V
VCC_GFXCORE 0.35V to 1.5V
VGA_CORE 0.4 to 1.25V
Reserved. 1D8V_VGA_S0 1.8V
SATA2GP/ This signal has a weak internal pull-down. 3D3V_VGA_S0 3.3V
GPIO36 NOTE: The internal pull-down is disabled after PLTRST# deasserts. 1D5V_VGA_S0 1V
NOTE: This signal should not be pulled high when strap is sampled. PCIe Routing 1V_VGA_S0

Reserved 1D5V_S3 5V
DDR_VREF_S3 1.5V S3
This signal has a weak internal pull-down.
SATA3GP/ NOTE: The internal pull-down is disabled after PLTRST# deasserts. LANE1 X
GPIO37 NOTE: This signal should not be pulled high when strap is sampled.
BT+ 9V-14.1V
High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking isolation logic. This is an LANE2 X DCBATOUT 9V-19.5V
5V_S5 5V
active-low-signal. When deasserted the external docking switch is in isolate mode. When asserted the external docking switch 5V_AUX_S5 5V All S states AC Brick Mode only
HDA_DOCK_EN# electrically connects the Intel? HD Audio dock signals to the corresponding Cougar Point signals. This signal can instead be LANE3 Card Reader 3D3V_S5 3.3V
/GPIO33 used as GPIO33. 3D3V_AUX_S5 3.3V

Signal has a weak internal pull-down. If strap is sampled low, the security measures defined in the Flash Descriptor will be in LANE4 Mini Card1(WLAN)
3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states
effect (default). If sampled high, the Flash Descriptor Security will be overridden. This strap should only be asserted high via
external pull-up in manufacturing/debug environments ONLY. LANE5 X
HDA_SDO Note: The weak internal pull-down is disabled after PLTRST# deasserts. Asserting the HDA_SDO high on the rising edge of 3D3V_AUX_S5 3.3V G3, Sx Powered by Li Coin Cell in G3
RSMRST# will also halt Intel Management Engine after chipset bring up and disable runtime Intel Management Engine features. and 3D3V_S5 in Sx
This is a debug mode and must not be asserted after manufacturing/ debug.
LANE6 LAN
B B

This signal has a weak internal pull-down. LANE7 X


HDA_SYNC On Die PLL VR is supplied by 1.5 V from VCCVRM when sampled high, 1.8 V from VCCVRM when sampled low.
Needs to be pulled High for Chief River platform. LANE8 X
TLS Confidentiality
Low (0) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality
GPIO15 High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality
This signal has a weak internal pull-down.
USB 2.0 Table USB3.0 Table
NOTE: The weak internal pull-down is disabled after RSMRST# deasserts.
Pair Device
SMBus ADDRESSES
NOTE: A strong pull-up may be needed for GPIO functionality USB
0 FREE Pair Device
L_DDC_DATA LVDS Detected. I 2 C / SMBus Addresses Ref Des Chief River CRV
When '1'- LVDS is detected; When '0'- LVDS is not detected. This signal has a weak internal pull-down. 1 USB 3.0 I/O CONN. 1 1 FREE Device Address Hex Bus
NOTE: The internal pull-down is disabled after PLTRST# deasserts. 2 USB 3.0 I/O CONN. 2
SDVO_CTRLDATA Port B Detected
2 I/O CONN. 1
3 USB 3.0 I/O CONN. 3 DIMM1 PCH_SMB_CLK/PCH_SMB_DATA
When '1'- Port B is detected; When '0'- Port B is not detected. This signal has a weak internal pull-down. 3 I/O CONN. 2 DIMM2 PCH_SMB_CLK/PCH_SMB_DATA
NOTE: The internal pull-down is disabled after PLTRST# deasserts. Touch-Pad PCH_SMB_CLK/PCH_SMB_DATA
4 FREE 4 I/O CONN. 3
DDPC_CTRLDATA Port C Detected.
When '1'- Port C is detected; When '0'- Port C is not detected This signal has a weak internal pull-down. 5 BT WLAN combo N/A PCH_SML0_CLK/PCH_SML0_DATA

DDPD_CTRLDATA
NOTE: The internal pull-down is disabled after PLTRST# deasserts
Port D Detected.
6 FREE SATA Table
7 KBC PCH_SML1CLK/PCH_SML1DATA
When '1'- Port D is detected; When '0'- Port D is not detected This signal has a weak internal pull-down. FREE SATA G781_Thermal IC 1001100 PCH_SML1CLK/PCH_SML1DATA
NOTE: The internal pull-down is disabled after PLTRST# deasserts. 8 GPU_Thames PRO 0X41 PCH_SML1CLK/PCH_SML1DATA
DSWVRMEN Deep S4/S5 Well On-Die Voltage Regulator Enable
Fingerprint Pair Device G-Sensor 0X52 PCH_SML1CLK/PCH_SML1DATA
A A
If strap is sampled high, the Integrated Deep S4/S5 Well (DSW) On-Die VR mode is enabled. 9 USB 2.0 I/O CONN. 1
<Core Design>
The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is 10 Camera 0 HDD
GPIO28 disabled. If not used, 8.2-kΩ to 10-kΩ pull-up to +V3.3A power-rail.
Note: This signal has a weak internal pull-up. The internal pull-up is disabled after RSMRST# deasserts. 11 FREE 1 ODD Wistron Corporation
GPIO29 is multiplexed with SLP_LAN#. If Intel LAN is implemented on the platform, SLP_LAN# must be used to control the power 12 WWAN 2 N/A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
GPIO29/ to the PHY LAN (no other implementation is supported). If integrated Intel LAN is not supported on the platform, GPIO29 can be Taipei Hsien 221, Taiwan, R.O.C.
SLP_LAN# used as a normal GPIO. A soft strap determines the functionality of GPIO29, either as SLP_LAN# or GPIO. By default, the soft 13 FREE 3 N/A
Title
strap enables SLP_LAN# functionality on the pin. If the soft trap is changed to enable GPIO functionality, 4 N/A
then SLP_LAN# functionality is no longer available, and the signal can be used as a normal GPIO (default to GPI). Table of Content
5 N/A Size Document Number Rev
Custom
2012 S-Series Richie 13.3 -1
Date: Wednesday, March 14, 2012 Sheet 3 of 103
5 4 3 2 1
5 4 3 2 1

CPU(1/7)
IVY BRIDGE PROCESSOR (DMI,DP,PEG,FDI)
D PEG Compensation D
1D05V_S0
CPU1A 1 OF 9
J22 PEG_COMP 1 2
IVY-BRIDGE PEG_ICOMPI R401 24D9R2F-L-GP
19 DMI_TXN[3:0] PEG_ICOMPO J21
DMI_TXN0 B27 H22
DMI_TXN1 DMI_RX#0 PEG_RCOMPO
Note: B25 DMI_RX#1
Signal Routing Guideline:
Intel DMI supports both Lane DMI_TXN2 A25 PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
DMI_TXN3 DMI_RX#2 PEG_RXN15 PEG_RXN[0..15] 83
B24 K33
Reversal and polarity inversion DMI_RX#3 PEG_RX#0
M35 PEG_RXN14 PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
but only at PCH side. This is 19 DMI_TXP[3:0] PEG_RX#1
DMI_TXP0 B28 L34 PEG_RXN13
DMI_TXP1 DMI_RX0 PEG_RX#2 PEG_RXN12
enabled via a soft strap. B26 DMI_RX1 PEG_RX#3 J35

DMI
DMI_TXP2 A24 J32 PEG_RXN11
DMI_TXP3 DMI_RX2 PEG_RX#4 PEG_RXN10
B23 DMI_RX3 PEG_RX#5 H34
H31 PEG_RXN9
19 DMI_RXN[3:0] DMI_RXN0 PEG_RX#6 PEG_RXN8
G21 DMI_TX#0 PEG_RX#7 G33
DMI_RXN1 E22 G30 PEG_RXN7
DMI_RXN2 DMI_TX#1 PEG_RX#8 PEG_RXN6
F21 DMI_TX#2 PEG_RX#9 F35
DMI_RXN3 D21 E34 PEG_RXN5
DMI_TX#3 PEG_RX#10 PEG_RXN4
19 DMI_RXP[3:0] PEG_RX#11 E32
DMI_RXP0 G22 D33 PEG_RXN3
DMI_RXP1 DMI_TX0 PEG_RX#12 PEG_RXN2
D22 DMI_TX1 PEG_RX#13 D31

PCI EXPRESS* - GRAPHICS


DMI_RXP2 F20 B33 PEG_RXN1
DMI_RXP3 DMI_TX2 PEG_RX#14 PEG_RXN0
C21 DMI_TX3 PEG_RX#15 C32

PEG_RXP15 PEG_RXP[0..15] 83
PEG_RX0 J33
L35 PEG_RXP14
PEG_RX1
C 19 FDI_TX_N[7:0] FDI_TX_N0 A21
PEG_RX2 K34
H35
PEG_RXP13
PEG_RXP12 C
FDI_TX_N1 FDI0_TX#0 PEG_RX3 PEG_RXP11
Note: H19 FDI0_TX#1 PEG_RX4 H32
Intel FDI supports both Lane FDI_TX_N2 E19 G34 PEG_RXP10
FDI_TX_N3 FDI0_TX#2 PEG_RX5 PEG_RXP9
F18 G31

Intel(R) FDI
Reversal and polarity inversion FDI_TX_N4 B21
FDI0_TX#3 PEG_RX6
F33 PEG_RXP8
but only at PCH side. This is FDI_TX_N5 FDI1_TX#0 PEG_RX7 PEG_RXP7
C20 FDI1_TX#1 PEG_RX8 F30
enabled via a soft strap. FDI_TX_N6 D18 E35 PEG_RXP6
FDI_TX_N7 FDI1_TX#2 PEG_RX9 PEG_RXP5
E17 FDI1_TX#3 PEG_RX10 E33
F32 PEG_RXP4
PEG_RX11 PEG_RXP3
19 FDI_TX_P[7:0] PEG_RX12 D34
FDI_TX_P0 A22 E31 PEG_RXP2
FDI_TX_P1 FDI0_TX0 PEG_RX13 PEG_RXP1
G19 FDI0_TX1 PEG_RX14 C33
FDI_TX_P2 E20 B32 PEG_RXP0
FDI_TX_P3 FDI0_TX2 PEG_RX15
G18 FDI0_TX3 PEG_TXN[0..15] 83
FDI_TX_P4 B20 M29 PEG_C_TXN15 DIX_PX C401 1 2 SCD22U16V2KX-GP PEG_TXN15
FDI_TX_P5 FDI1_TX0 PEG_TX#0 PEG_C_TXN14
C19 FDI1_TX1 PEG_TX#1 M32 DIX_PX C402 1 2 SCD22U16V2KX-GP PEG_TXN14
FDI_TX_P6 D19 M31 PEG_C_TXN13 DIX_PX C403 1 2 SCD22U16V2KX-GP PEG_TXN13
FDI_TX_P7 FDI1_TX2 PEG_TX#2 PEG_C_TXN12
F17 FDI1_TX3 PEG_TX#3 L32 DIX_PX C404 1 2 SCD22U16V2KX-GP PEG_TXN12
L29 PEG_C_TXN11 DIX_PX C405 1 2 SCD22U16V2KX-GP PEG_TXN11
PEG_TX#4 PEG_C_TXN10
Note: 19 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#5 K31 DIX_PX C406 1 2 SCD22U16V2KX-GP PEG_TXN10
Lane reversal does not apply to J17 K28 PEG_C_TXN9 DIX_PX C407 1 2 SCD22U16V2KX-GP PEG_TXN9
19 FDI_FSYNC1 FDI1_FSYNC PEG_TX#6 PEG_C_TXN8
FDI sideband signals. PEG_TX#7 J30 DIX_PX C408 1 2 SCD22U16V2KX-GP PEG_TXN8
H20 J28 PEG_C_TXN7 DIX_PX C409 1 2 SCD22U16V2KX-GP PEG_TXN7
19 FDI_INT FDI_INT PEG_TX#8 PEG_C_TXN6
PEG_TX#9 H29 DIX_PX C410 1 2 SCD22U16V2KX-GP PEG_TXN6
DP Compensation, within 500mil J19 G27 PEG_C_TXN5 DIX_PX C411 1 2 SCD22U16V2KX-GP PEG_TXN5
19 FDI_LSYNC0 FDI0_LSYNC PEG_TX#10 PEG_C_TXN4
19 FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#11 E29 DIX_PX C412 1 2 SCD22U16V2KX-GP PEG_TXN4
F27 PEG_C_TXN3 DIX_PX C413 1 2 SCD22U16V2KX-GP PEG_TXN3
PEG_TX#12 PEG_C_TXN2
PEG_TX#13 D28 DIX_PX C414 1 2 SCD22U16V2KX-GP PEG_TXN2
1D05V_S0 F26 PEG_C_TXN1 DIX_PX C415 1 2 SCD22U16V2KX-GP PEG_TXN1
B 4mil
PEG_TX#14
PEG_TX#15 E25 PEG_C_TXN0 DIX_PX C416 1 2 SCD22U16V2KX-GP PEG_TXN0 B
R402 1 2 24D9R2F-L-GP DP_COMP A18 EDP_COMPIO PEG_C_TXP15 PEG_TXP[0..15] 83
12mil A17 EDP_ICOMPO PEG_TX0 M28 DIX_PX C417 1 2 SCD22U16V2KX-GP PEG_TXP15
B16 M33 PEG_C_TXP14 DIX_PX C418 1 2 SCD22U16V2KX-GP PEG_TXP14
EDP_HPD PEG_TX1 PEG_C_TXP13
PEG_TX2 M30 DIX_PX C419 1 2 SCD22U16V2KX-GP PEG_TXP13
NOTE: EDP_HPD L31 PEG_C_TXP12 DIX_PX C420 1 2 SCD22U16V2KX-GP PEG_TXP12
PEG_TX3 PEG_C_TXP11
Select a Fast FET similar to 2N7002E whose rise/ C15 EDP_AUX PEG_TX4 L28 DIX_PX C421 1 2 SCD22U16V2KX-GP PEG_TXP11
D15 K30 PEG_C_TXP10 DIX_PX C422 1 2 SCD22U16V2KX-GP PEG_TXP10
EDP_AUX# PEG_TX5
eDP

fall time is less than 6 ns. PEG_TX6 K27 PEG_C_TXP9 DIX_PX C423 1 2 SCD22U16V2KX-GP PEG_TXP9
J29 PEG_C_TXP8 DIX_PX C424 1 2 SCD22U16V2KX-GP PEG_TXP8
If HPD on eDP interface is PEG_TX7 PEG_C_TXP7
C17 EDP_TX0 PEG_TX8 J27 DIX_PX C425 1 2 SCD22U16V2KX-GP PEG_TXP7
disabled, connect it to CPU VCCIO via a 10-kΩ pull-Up F16 H28 PEG_C_TXP6 DIX_PX C426 1 2 SCD22U16V2KX-GP PEG_TXP6
EDP_TX1 PEG_TX9 PEG_C_TXP5
resistor on the motherboard. C16 EDP_TX2 PEG_TX10 G28 DIX_PX C427 1 2 SCD22U16V2KX-GP PEG_TXP5
G15 E28 PEG_C_TXP4 DIX_PX C428 1 2 SCD22U16V2KX-GP PEG_TXP4
This signal can be left as no connect if entire eDP interface is disabled. EDP_TX3 PEG_TX11
F28 PEG_C_TXP3 DIX_PX C429 1 2 SCD22U16V2KX-GP PEG_TXP3
PEG_TX12 PEG_C_TXP2
C18 EDP_TX#0 PEG_TX13 D27 DIX_PX C430 1 2 SCD22U16V2KX-GP PEG_TXP2
E16 E26 PEG_C_TXP1 DIX_PX C431 1 2 SCD22U16V2KX-GP PEG_TXP1
EDP_TX#1 PEG_TX14 PEG_C_TXP0
D16 EDP_TX#2 PEG_TX15 D25 DIX_PX C432 1 2 SCD22U16V2KX-GP PEG_TXP0
F15 EDP_TX#3
Signal Routing Guideline:
EDP_ICOMPO keep W/S=12/15 mils and routing
length less than 500 mils. 62.10040.821
EDP_COMPIO keep W/S=4/15 mils and routing 1ST = 62.10055.551
length less than 500 mils.
2nd = 62.10055.321
3rd = 62.10055.731
A NOTE.
<Core Design>
A
Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort. BOM Note:1st/2nd/3rd Add in BOM
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(1/7): DMI/PEG/FDI
Size Document Number Rev
A3 -1
2012 S-Series Richie 13.3
Date: W ednesday, March 14, 2012 Sheet 4 of 103
5 4 3 2 1

CPU(2/7)
IVY BRIDGE PROCESSOR (CLK,MISC,JTAG)
CPU1B 2 OF 9
1D05V_S0 20120116PV-R
IVY-BRIDGE
RN501 0R4P2R-PAD
A28 CPU_BCLK_P 2 3
BCLK CLKOUT_DMI_P 18

MISC

CLOCKS
D D
C26 A27 CPU_BCLK_N 1 4
22 H_SNB_IVB# PROC_SELECT# BCLK# CLKOUT_DMI_N 18

1
R501 1D05V_S0

RN
62R2F-GP TPAD14-OP-GP
TP501
T P501 1 TP_SKTOCC#_R AN34
SKTOCC# CLK_DP_P_R 1
A16 4 RN504
Q501 DPLL_REF_CLK CLK_DP_N_R 2
A15 3 SRN1KJ-7-GP

2
DPLL_REF_CLK#
27 KBC_PROCHOT G
TPAD14-OP-GP
D TP502 1 H_CATERR# AL33
H_PROCHOT# 42 CATERR#

1
R525 S

THERMAL
100KR2J-1-GP
2N7002K-2-GP AN33 R8 CPUDRAMRST#
22,27 H_PECI PECI SM_DRAMRST#
84.2N702.J31

DDR3
MISC
2
2nd = 84.07002.I31 H_PROCHOT# H_PROCHOT#_D AL32 SM_RCOMP_0
3rd = 84.2N702.W31 1
R508
2
56R2F-1-GP PROCHOT# SM_RCOMP0
AK1
SM_RCOMP_1
A5
SM_RCOMP1 SM_RCOMP_2
SM_RCOMP2 A4

AN32
PM_DRAM_PWRGD Traces impedance= 50 ohm 22,85 H_THRMTRIP# THERMTRIP#

1 2 H_CPUPWRGD_R
R518 10KR2J-3-GP AP29 XDP_PRDY# 1 TP503 TPAD14-OP-GP
3D3V_S0 3D3V_S5 1D5V_S0 PRDY# XDP_PREQ#
AND GATE PREQ#
AP27

AR26 XDP_TCK
TCK
1

PWR MANAGEMENT
C503 AR27 XDP_TMS

JTAG & BPM


TMS
1

R523 SCD1U10V2KX-5GP
19 H_PM_SYNC
R519 1 2 0R0402-PAD-1-GP H_PM_SYNC_R AM34 AP30 XDP_TRST#
PM_SYNC TRST#
1

1
200R2F-L-GP
C
R524 C502 AR28 XDP_TDI C
2

200R2F-L-GP SC1U6D3V2KX-GP TDI XDP_TDO


U501 AP26
2

2
TDO
19 PM_DRAM_PWRGD 1 5 22 H_CPUPWRGD
R520 1 2 0R0402-PAD-1-GP H_CPUPWRGD_R AP33
IN B VCC UNCOREPWRGOOD
2

27,37,42,50,96 PWR_GOOD 2 IN A
AL35 XDP_DBRESET# 19
PM_DRAM_PWRGD_M PM_DRAM_PWRGD_R DBR#
3 4 1 2 V8
GND OUT Y R512 130R2F-1-GP SM_DRAMPWROK
AT28 XDP_BPM0_R 1 TP510 TPAD14-OP-GP
74VHC1G09DFT2G-GP BPM#0 XDP_BPM1_R TP511 TPAD14-OP-GP
BPM#1 AR29 1
73.01G09.AAH AR30 XDP_BPM2_R 1 TP512 TPAD14-OP-GP
BUF_CPU_RST# BPM#2 XDP_BPM3_R TP513 TPAD14-OP-GP
2nd = 73.01G09.0AB AR33
RESET# BPM#3
AT30
XDP_BPM4_R
1
3rd = 73.01G09.BAH AP32 1 TP514 TPAD14-OP-GP
R502 BPM#4 XDP_BPM5_R TP515 TPAD14-OP-GP
DY BPM#5
AR31
XDP_BPM6_R
1
1 2 AT31 1 TP516 TPAD14-OP-GP
0R2J-2-GP BPM#6 XDP_BPM7_R TP517 TPAD14-OP-GP
AR32 1
1D05V_S0 BPM#7
3D3V_S0
1

R526
75R2J-1-GP
1

C504
2

U502 SCD1U10V2KX-5GP 3D3V_S0 1D05V_S0


DDR3 Compensation Signals
2

1 NC#1 VCC 5 PUT CLOSE CPU


SM_RCOMP_0

2
2 SM_RCOMP_1
17,21,32,34,53,54,56,71,83,96,97 PLT_RST# A SM_RCOMP_2
R1111
3 4 BUF_CPU_RST#_R 1 2 R1110 51R2J-2-GP
GND Y

1
1KR2J-1-GP
1

1
B R517 R510 R504 R503 B

1
74LVC1G07GW-GP R521

200R2F-L-GP

25D5R2F-GP

140R2F-GP
43R2J-GP 750R2F-GP XDP_TDO
Buffered reset to CPU
DY

2
1D5V_S3 XDP_DBRESET#
S3 Power Reduction Circuit
2

2
1st = 73.01G07.AHG
1 2 SM_DRAMRST#
2nd = 73.01G07.AHG DY

1
3rd = 73.17S07.0AG R527
1K5R2F-2-GP R522 R513
CPUDRAMRST# 1 2 CPUDRAMRST#_R 1KR2F-3-GP
DY 0R2J-2-GP

2
Q502
DMN5L06K-7-GP
R514 1D05V_S0
PU/PD for JTAG signals
S D 1 2 DDR3_DRAMRST# 14,15,97
3D3V_S5
DEEP S3 20120116PV-R 84.05067.031 1KR2J-1-GP
1

XDP_TMS R506 1 2 51R2J-2-GP


1

R515 2ND = 84.00138.F31


G

R529 DY R530 4K99R2F-L-GP XDP_TDI R509 1 2 51R2J-2-GP


20KR2J-L2-GP 1 2 20120112 PV-R
XDP_PREQ# R505 1 DY 2 51R2J-2-GP
PCH_DDR_EN# 8
2

0R0402-PAD
2

C501 XDP_TCK R507 1 2 51R2J-2-GP


R528 SCD047U25V2KX-GP
2

18 PCH_DDR_RST# 1 2 PCH_DDR_EN# 8
DY_DS3 XDP_TRST# R511 1 2 51R2J-2-GP
20KR2J-L2-GP

A A
27,46 KBC_DDR_RST#
<Core Design>
G

Q503
DMN5L06K-7-GP Wistron Corporation
S D 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
DY_DS3
Title
84.05067.031
2ND = 84.07002.I31
3rd = 84.2N702.W31
CPU(2/7) : CLK/MISC/JTAG
Size Document Number Rev
Custom
2012 S-Series Richie 13.3 -1
Date: Wednesday, March 14, 2012 Sheet 5 of 103
5 4 3 2 1
5 4 3 2 1

CPU(3/7)
IVY BRIDGE PROCESSOR (DDR3)

D D

CPU1C 3 OF 9 CPU1D 4 OF 9

IVY-BRIDGE IVY-BRIDGE
SA_CK0 AB6 SB_CK0 AE2
14 M_A_DQ[63:0] M_A_DIM0_CLK_DDR0 14 15 M_B_DQ[63:0] M_B_DIM0_CLK_DDR0 15
SA_CLK#0 AA6 SB_CLK#0 AD2
M_A_DQ0 M_A_DIM0_CLK_DDR#0 14 M_B_DQ0 M_B_DIM0_CLK_DDR#0 15
C5 V9 C9 R9
M_A_DQ1 SA_DQ0 SA_CKE0 M_A_DIM0_CKE0 14 M_B_DQ1 SB_DQ0 SB_CKE0 M_B_DIM0_CKE0 15
D5 SA_DQ1 A7 SB_DQ1
M_A_DQ2 D3 M_B_DQ2 D10
M_A_DQ3 SA_DQ2 M_B_DQ3 SB_DQ2
D2 SA_DQ3 C8 SB_DQ3
M_A_DQ4 D6 AA5 M_B_DQ4 A9 AE1
M_A_DQ5 SA_DQ4 SA_CK1 M_A_DIM0_CLK_DDR1 14 M_B_DQ5 SB_DQ4 SB_CK1 M_B_DIM0_CLK_DDR1 15
C6 AB5 A8 AD1
M_A_DQ6 SA_DQ5 SA_CLK#1 M_A_DIM0_CLK_DDR#1 14 M_B_DQ6 SB_DQ5 SB_CLK#1 M_B_DIM0_CLK_DDR#1 15
C2 V10 D9 R10
M_A_DQ7 SA_DQ6 SA_CKE1 M_A_DIM0_CKE1 14 M_B_DQ7 SB_DQ6 SB_CKE1 M_B_DIM0_CKE1 15
C3 SA_DQ7 D8 SB_DQ7
M_A_DQ8 F10 M_B_DQ8 G4
M_A_DQ9 SA_DQ8 M_B_DQ9 SB_DQ8
F8 SA_DQ9 F4 SB_DQ9
M_A_DQ10 G10 AB4 M_B_DQ10 F1 AB2
M_A_DQ11 SA_DQ10 SA_CK2 M_B_DQ11 SB_DQ10 SB_CK2
G9 AA4 G1 AA2
M_A_DQ12 SA_DQ11 SA_CLK#2 M_B_DQ12 SB_DQ11 SB_CLK#2
F9 W9 G5 T9
M_A_DQ13 SA_DQ12 SA_CKE2 M_B_DQ13 SB_DQ12 SB_CKE2
F7 SA_DQ13 F5 SB_DQ13
M_A_DQ14 G8 M_B_DQ14 F2
M_A_DQ15 SA_DQ14 M_B_DQ15 SB_DQ14
G7 G2
M_A_DQ16 SA_DQ15 M_B_DQ16 SB_DQ15
K4 SA_DQ16 SA_CK3 AB3 J7 SB_DQ16 SB_CK3 AA1
M_A_DQ17 K5 AA3 M_B_DQ17 J8 AB1
M_A_DQ18 SA_DQ17 SA_CLK#3 M_B_DQ18 SB_DQ17 SB_CLK#3
K1 W10 K10 T10
M_A_DQ19 SA_DQ18 SA_CKE3 M_B_DQ19 SB_DQ18 SB_CKE3
J1 SA_DQ19 K9 SB_DQ19
M_A_DQ20 J5 M_B_DQ20 J9
M_A_DQ21 SA_DQ20 M_B_DQ21 SB_DQ20
J4 J10
M_A_DQ22 SA_DQ21 M_B_DQ22 SB_DQ21
J2 AK3 K8 AD3
C M_A_DQ23 SA_DQ22 SA_CS#0 M_A_DIM0_CS#0 14 M_B_DQ23 SB_DQ22 SB_CS#0 M_B_DIM0_CS#0 15 C
K2 SA_DQ23 SA_CS#1 AL3 K7 SB_DQ23 SB_CS#1 AE3
M_A_DQ24 M_A_DIM0_CS#1 14 M_B_DQ24 M_B_DIM0_CS#1 15
M8 AG1 M5 AD6
M_A_DQ25 SA_DQ24 SA_CS#2 M_B_DQ25 SB_DQ24 SB_CS#2
N10 AH1 N4 AE6
M_A_DQ26 SA_DQ25 SA_CS#3 M_B_DQ26 SB_DQ25 SB_CS#3
N8 SA_DQ26 N2 SB_DQ26
M_A_DQ27 N7 M_B_DQ27 N1
M_A_DQ28 SA_DQ27 M_B_DQ28 SB_DQ27
M10 M4
M_A_DQ29 SA_DQ28 M_B_DQ29 SB_DQ28
M9 SA_DQ29 SA_ODT0 AH3 N5 SB_DQ29 SB_ODT0 AE4
M_A_DIM0_ODT0 14 M_B_DIM0_ODT0 15

DDR SYSTEM MEMORY B


M_A_DQ30 N9 AG3 M_B_DQ30 M2 AD4
DDR SYSTEM MEMORY A

M_A_DQ31 SA_DQ30 SA_ODT1 M_A_DIM0_ODT1 14 M_B_DQ31 SB_DQ30 SB_ODT1 M_B_DIM0_ODT1 15


M7 SA_DQ31 SA_ODT2 AG2 M1 SB_DQ31 SB_ODT2 AD5
M_A_DQ32 AG6 AH2 M_B_DQ32 AM5 AE5
M_A_DQ33 SA_DQ32 SA_ODT3 M_B_DQ33 SB_DQ32 SB_ODT3
AG5 SA_DQ33 AM6 SB_DQ33
M_A_DQ34 AK6 M_B_DQ34 AR3
M_A_DQ35 SA_DQ34 M_B_DQ35 SB_DQ34
AK5 SA_DQ35 AP3 SB_DQ35
M_A_DQ36 AH5 M_B_DQ36 AN3
SA_DQ36 M_A_DQS#[7:0] 14 SB_DQ36 M_B_DQS#[7:0] 15
M_A_DQ37 AH6 C4 M_A_DQS#0 M_B_DQ37 AN2 D7 M_B_DQS#0
M_A_DQ38 SA_DQ37 SA_DQS#0 M_A_DQS#1 M_B_DQ38 SB_DQ37 SB_DQS#0 M_B_DQS#1
AJ5 G6 AN1 F3
M_A_DQ39 SA_DQ38 SA_DQS#1 M_A_DQS#2 M_B_DQ39 SB_DQ38 SB_DQS#1 M_B_DQS#2
AJ6 J3 AP2 K6
M_A_DQ40 SA_DQ39 SA_DQS#2 M_A_DQS#3 M_B_DQ40 SB_DQ39 SB_DQS#2 M_B_DQS#3
AJ8 M6 AP5 N3
M_A_DQ41 SA_DQ40 SA_DQS#3 M_A_DQS#4 M_B_DQ41 SB_DQ40 SB_DQS#3 M_B_DQS#4
AK8 AL6 AN9 AN5
M_A_DQ42 SA_DQ41 SA_DQS#4 M_A_DQS#5 M_B_DQ42 SB_DQ41 SB_DQS#4 M_B_DQS#5
AJ9 SA_DQ42 SA_DQS#5 AM8 AT5 SB_DQ42 SB_DQS#5 AP9
M_A_DQ43 AK9 AR12 M_A_DQS#6 M_B_DQ43 AT6 AK12 M_B_DQS#6
M_A_DQ44 SA_DQ43 SA_DQS#6 M_A_DQS#7 M_B_DQ44 SB_DQ43 SB_DQS#6 M_B_DQS#7
AH8 AM15 AP6 AP15
M_A_DQ45 SA_DQ44 SA_DQS#7 M_B_DQ45 SB_DQ44 SB_DQS#7
AH9 AN8
M_A_DQ46 SA_DQ45 M_B_DQ46 SB_DQ45
AL9 AR6
M_A_DQ47 SA_DQ46 M_B_DQ47 SB_DQ46
AL8 AR5
M_A_DQ48 SA_DQ47 M_B_DQ48 SB_DQ47
AP11 M_A_DQS[7:0] 14 AR9 M_B_DQS[7:0] 15
M_A_DQ49 SA_DQ48 M_A_DQS0 M_B_DQ49 SB_DQ48 M_B_DQS0
AN11 SA_DQ49 SA_DQS0 D4 AJ11 SB_DQ49 SB_DQS0 C7
M_A_DQ50 AL12 F6 M_A_DQS1 M_B_DQ50 AT8 G3 M_B_DQS1
M_A_DQ51 SA_DQ50 SA_DQS1 M_A_DQS2 M_B_DQ51 SB_DQ50 SB_DQS1 M_B_DQS2
AM12 K3 AT9 J6
M_A_DQ52 SA_DQ51 SA_DQS2 M_A_DQS3 M_B_DQ52 SB_DQ51 SB_DQS2 M_B_DQS3
AM11 N6 AH11 M3
M_A_DQ53 SA_DQ52 SA_DQS3 M_A_DQS4 M_B_DQ53 SB_DQ52 SB_DQS3 M_B_DQS4
AL11 AL5 AR8 AN6
M_A_DQ54 SA_DQ53 SA_DQS4 M_A_DQS5 M_B_DQ54 SB_DQ53 SB_DQS4 M_B_DQS5
AP12 AM9 AJ12 AP8
B M_A_DQ55 SA_DQ54 SA_DQS5 M_A_DQS6 M_B_DQ55 SB_DQ54 SB_DQS5 M_B_DQS6 B
AN12 SA_DQ55 SA_DQS6 AR11 AH12 SB_DQ55 SB_DQS6 AK11
M_A_DQ56 AJ14 AM14 M_A_DQS7 M_B_DQ56 AT11 AP14 M_B_DQS7
M_A_DQ57 SA_DQ56 SA_DQS7 M_B_DQ57 SB_DQ56 SB_DQS7
AH14 AN14
M_A_DQ58 SA_DQ57 M_B_DQ58 SB_DQ57
AL15 SA_DQ58 AR14 SB_DQ58
M_A_DQ59 AK15 M_B_DQ59 AT14
M_A_DQ60 SA_DQ59 M_B_DQ60 SB_DQ59
AL14 AT12
M_A_DQ61 SA_DQ60 M_A_A0 M_A_A[15:0] 14 M_B_DQ61 SB_DQ60 M_B_A0 M_B_A[15:0] 15
AK14 AD10 AN15 AA8
M_A_DQ62 SA_DQ61 SA_MA0 M_A_A1 M_B_DQ62 SB_DQ61 SB_MA0 M_B_A1
AJ15 W1 AR15 T7
M_A_DQ63 SA_DQ62 SA_MA1 M_A_A2 M_B_DQ63 SB_DQ62 SB_MA1 M_B_A2
AH15 W2 AT15 R7
SA_DQ63 SA_MA2 M_A_A3 SB_DQ63 SB_MA2 M_B_A3
SA_MA3 W7 SB_MA3 T6
V3 M_A_A4 T2 M_B_A4
SA_MA4 M_A_A5 SB_MA4 M_B_A5
V2 T4
SA_MA5 M_A_A6 SB_MA5 M_B_A6
SA_MA6 W3 SB_MA6 T3
AE10 W6 M_A_A7 AA9 R2 M_B_A7
14 M_A_BS0 SA_BS0 SA_MA7 M_A_A8 15 M_B_BS0 SB_BS0 SB_MA7 M_B_A8
AF10 SA_BS1 SA_MA8 V1 AA7 SB_BS1 SB_MA8 T5
14 M_A_BS1 M_A_A9 15 M_B_BS1 M_B_A9
V6 W5 R6 R3
14 M_A_BS2 SA_BS2 SA_MA9 M_A_A10 15 M_B_BS2 SB_BS2 SB_MA9 M_B_A10
AD8 AB7
SA_MA10 M_A_A11 SB_MA10 M_B_A11
V4 R1
SA_MA11 M_A_A12 SB_MA11 M_B_A12
W4 T1
SA_MA12 M_A_A13 SB_MA12 M_B_A13
AE8 AF8 AA10 AB10
14 M_A_CAS# SA_CAS# SA_MA13 M_A_A14 15 M_B_CAS# SB_CAS# SB_MA13 M_B_A14
AD9 V5 AB8 R5
14 M_A_RAS# SA_RAS# SA_MA14 M_A_A15 15 M_B_RAS# SB_RAS# SB_MA14 M_B_A15
14 M_A_WE# AF9 SA_WE# SA_MA15 V7 15 M_B_WE# AB9 SB_WE# SB_MA15 R4

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(3/7) : DDR3
Size Document Number Rev
Custom
2012 S-Series Richie 13.3 -1
Date: Wednesday, March 14, 2012 Sheet 6 of 103
5 4 3 2 1
5 4 3 2 1

CPU(4/7)
IVY BRIDGE PROCESSOR (POWER)
CPU1F POWER 6 OF 9

8.5A
IVY-BRIDGE
1D05V_S0
D 53A PROCESSOR UNCORE POWER D
PROCESSOR CORE VCC_CORE

POWER AG35
VCC1
AG34 AH13
VCC2 VCCIO1
AG33 VCC3 VCCIO2 AH10
AG32 AG10
VCC4 VCCIO3
AG31 VCC5 VCCIO4 AC10
AG30 Y10 C729 C730 C731 C732 C715 C716 C717 C718 C733 C734 C719 C720
VCC6 VCCIO5

1
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC22U6D3V5MX-2GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC22U6D3V5MX-2GP
C713 C722 C727 C736 C714 AG29 U10
VCC7 VCCIO6
1

1
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC10U6D3V3MX-GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
AG28 VCC8 VCCIO7 P10
AG27 L10

2
VCC9 VCCIO8
AG26 J14
2

2
VCC10 VCCIO9
AF35 J13
VCC11 VCCIO10
AF34 J12
Place Bottom AF33
AF32
VCC12
VCC13
VCC14
VCCIO11
VCCIO12
VCCIO13
J11
H14
AF31 H12
VCC15 VCCIO14
AF30 VCC16 VCCIO15 H11
AF29 G14
VCC17 VCCIO16
AF28 G13
VCC18 VCCIO17

PEG AND DDR


C735 C721 C726 C728 C723 AF27 G12
VCC19 VCCIO18
1

1
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC10U6D3V3MX-GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD34 F12
2

2
VCC22 VCCIO21
AD33 VCC23 VCCIO22 F11
AD32 E14
VCC24 VCCIO23
AD31 E12
VCC25 VCCIO24
AD30 VCC26
AD29 VCC27 VCCIO25 E11
AD28 D14
VCC28 VCCIO26
AD27 D13
C VCC29 VCCIO27 C
AD26 VCC30 VCCIO28 D12
AC35 D11
VCC31 VCCIO29
AC34 C14
VCC32 VCCIO30
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 C11
VCC35 VCCIO33
AC30 VCC36 VCCIO34 B14
AC29 B12
VCC37 VCCIO35
AC28 VCC38 VCCIO36 A14
AC27 A13
VCC39 VCCIO37
AC26 VCC40 VCCIO38 A12
AA35 A11
VCC41 VCCIO39
AA34
Place Top C742 C703 C709 AA33
VCC42
VCC43 VCCIO40
J23
1

1
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

C701 C741 AA32


VCC44
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V3MX-GP

AA31
VCC45
AA30
2

VCC46
AA29
VCC47
AA28
VCC48
AA27 VCC49
AA26
VCC50
CORE SUPPLY
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
C738 C702 C706 C707 C708 VCC54
Y31
VCC55
1

1
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

Y30 VCC56
Y29
VCC57
Y28
2

VCC58
Y27
VCC59 Route these three net together
Y26
VCC60
V35
VCC61
SVID

B H_CPU_SVIDALRT# R705 1 B
V34 VCC62 VIDALERT# AJ29 2 43R2J-GP VR_SVID_ALERT# 42
V33 AJ30 H_CPU_SVIDCLK
VCC63 VIDSCLK H_CPU_SVIDDAT H_CPU_SVIDCLK 42
V32 AJ28 H_CPU_SVIDDAT 42
VCC64 VIDSOUT
V31 VCC65
V30
C740 C739 C704 C712 C710 C711 VCC66
V29 1 2 1D05V_S0
VCC67
1

1
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

V28 R703 130R2F-1-GP


VCC68
V27
VCC69
V26
2

VCC70
U35 VCC71
U34 VCC72
U33
VCC73
U32 VCC74
U31
VCC75 reserve PAD for ESD
U30 VCC76
U29
VCC77
U28
VCC78
U27
U26
VCC79 DY DY
VCC80 VCC_CORE
R35

0R2J-2-GP

0R2J-2-GP
VCC81
2

2
R34
VCC82
R33 VCC83

1
R32
VCC84 PUT CLOSE CPU
R31 VCC85
R30 R706
1

1
VCC86 D701 D702
R29 100R2F-L1-GP-U
VCC87
SENSE LINES

R28

2
VCC88 VCCSENSE
R27 AJ35
VCC89 VCC_SENSE VSSSENSE VCCSENSE 42
R26 AJ34
VCC90 VSS_SENSE VSSSENSE 42
P35
VCC91
P34
VCC92

1
P33 VCC93
A A
P32 B10
VCC94 VCCIO_SENSE VTT_SENSE 45 R704
P31 VCC95 VSS_SENSE_VCCIO A10 <Core Design>
VSSP_SENSE 45
P30 VCC96 100R2F-L1-GP-U
P29

2
VCC97
P28 VCC98 Wistron Corporation
1

P27
VCC99 R707 R708 1D05V_S0 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
P26 VCC100
10R2F-L-GP
10R2F-L-GP

Differential Sense feedback Taipei Hsien 221, Taiwan, R.O.C.

Title
2

CPU(4/7) : PWR
PUT CLOSE CPU Size Document Number Rev
Custom
2012 S-Series Richie 13.3 -1
Date: Wednesday, March 14, 2012 Sheet 7 of 103
5 4 3 2 1
5 4 3 2 1

CPU(5/7) VCCGT_SENSE

IVY BRIDGE PROCESSOR (GRAPHICS POWER) VSSGT_SENSE

D801 D802 M3 - Processor Generated SO-DIMM VREF_DQ

1
33A

0R2J-2-GP

0R2J-2-GP
VCC_GFXCORE CPU1G
POWER 7 OF 9 R820
1st = 84.05067.031
2nd = 84.00138.F31
3rd = 84.05067.031

S
1 2 100R2F-L1-GP-U VCC_GFXCORE

2
DY DY PCH_DDR_EN#
Under Socket and Closed to CPU G

SENSE
LINES
AT24 IVY-BRIDGE AK35 R810
D VAXG1 VAXG_SENSE VCCGT_SENSE 42 Q802 D
AT23 VAXG2 VSSAXG_SENSE AK34 VSSGT_SENSE 42 0R2J-2-GP
C820 C821 C822 C823 C824 C825 AT21 AP2302GN-HF-GP
VAXG3 DY
1

1
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
AT20 R819 reserve PAD for ESD

1
D
VAXG4
AT18 1 2 100R2F-L1-GP-U 20120112 PV-R
VAXG5
AT17
2

2
VAXG6 DDR_VREF_S3_B4
AR24 VAXG7 14 M_VREF_DQ_DIMM0
AR23 CAD Note: +V_SM_VREF should DDR_VREF_S3_D1
VAXG8 15 M_VREF_DQ_DIMM1
AR21 VAXG9 have 10 mil trace width
AR20 VAXG10
AR18 AL1 +V_SM_VREF_CNT

D
VAXG11 SM_VREF Q803
AR17 VAXG12

VREF

2
AP24 B4:VREF_DQ CHA AP2302GN-HF-GP
VAXG13

1
AP23 D1:VREF_DQ CHB C801 C802 R814
VAXG14
AP21
VAXG15 DY DY 5 PCH_DDR_EN# G 0R2J-2-GP

SCD1U16V2ZY-2GP

SC2D2U10V3ZY-1GP
AP20 B4 DDR_VREF_S3_B4 1st = 84.05067.031
DY

2
VAXG16 SA_DIMM_VREFDQ DDR_VREF_S3_D1
AP18 D1 2nd = 84.00138.F31

1
S
VAXG17 SB_DIMM_VREFDQ
AP17 VAXG18 3rd = 84.05067.031

1
AN24
VAXG19 R815 R816
AN23
AN21
VAXG20
VAXG21
1KR2F-3-GP 1KR2F-3-GP 12~16A
AN20
VAXG22 DY DY 1D5V_S0

DDR3 -1.5V RAILS


AN18

2
VAXG23
AN17 VAXG24 33OU*1 10U*6

GRAPHICS
VCC_GFXCORE AM24 AF7
VAXG25 VDDQ1 C803 C804 C805 C806 C807 C808
AM23 AF4
VAXG26 VDDQ2

1
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
AM21 VAXG27 VDDQ3 AF1
AM20 AC7 TC803
VAXG28 VDDQ4 ST330U2D5VBM-1-GP
Closed to CPU Socket AM18 AC4

2
VAXG29 VDDQ5
AM17 VAXG30 VDDQ6 AC1 80.3371V.A2L
C826 C827 C828 C829 C830 C831 AL24 Y7
VAXG31 VDDQ7
1

1
SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

AL23
VAXG32 VDDQ8
Y4 2nd = 77.22771.00L
AL21 Y1
C VAXG33 VDDQ9 C
AL20 U7 20120131PVR
2

VAXG34 VDDQ10
AL18 U4
VAXG35 VDDQ11
AL17 U1
VAXG36 VDDQ12
AK24 VAXG37 VDDQ13 P7
AK23 VAXG38 VDDQ14 P4
AK21 P1
VAXG39 VDDQ15
AK20 VAXG40
AK18
VAXG41
AK17
AJ24
VAXG42
VAXG43
6A
AJ23 VAXG44
AJ21 VCCSA
VAXG45
AJ20 VAXG46
AJ18
VAXG47
AJ17 M27

SA RAIL
VAXG48 VCCSA1
AH24 M26
VAXG49 VCCSA2 C813 C814 C815 TC802
AH23 L26
VAXG50 VCCSA3

1
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SE330U2D5VDM-1GP
AH21 J26
VAXG51 VCCSA4
AH20
VAXG52 VCCSA5
J25 DY VCCSA
AH18 J24 1st = 77.23371.13L

2
VAXG53 VCCSA6
AH17
VAXG54 VCCSA7
H26 2ND = 79.33719.L01
1.5A VCCSA8
H25 R0801 need be close to pin H23.

1
DY R801
100R2J-2-GP
1D8V_S0
1.8V RAIL

2
H23 VCCUSA_SENSE
VCCSA_SENSE VCCUSA_SENSE 48

B6
VCCPLL1
MISC

A6 C22 H_FC_C22
B C819 C816 C817 C818 VCCPLL2 VCCSA_VID0 VCCSA_SEL H_FC_C22 48 B
A2 VCCPLL3 VCCSA_VID1 C24
VCCSA_SEL 48
1

1
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

1
R804 R806
2

DY A19 H_VCCP_SEL
VCCIO_SEL 1KR2J-1-GP 1KR2J-1-GP

2
SNB: No Connect
IVB: VSS R817
0R2J-2-GP
2 1 H_SNB_IVB#_PWRCTRL 45
H_VCCP_SEL Voltage DY

2
1 1.05V R818
DY 0R2J-2-GP

0 1.0V
1

S3 Power Reduction Circuit Processor VREF_DQ Implementation


1D5V_S3 DDR_VREF_S3 20120112 PV-R
R811 DY
1

R821 R807 1 2
1KR2F-3-GP 1 2 0R2J-2-GP
A A
DY 0R0402-PAD Q801 <Core Design>
DMN5L06K-7-GP
2

+V_SM_VREF +V_SM_VREF_CNT
84.05067.031
D S
Wistron Corporation
1

R822 1st = 84.2N702.J31 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
+V_SM_VREF_G

1KR2F-3-GP 2ND = 84.07002.I31 R803 Taipei Hsien 221, Taiwan, R.O.C.


DY 3rd = 84.2N702.W31 100KR2J-1-GP
G

DY Title
R802 DY
CPU(5/7) : GFX/PWR
2

5 PCH_DDR_EN# 1 2 1 2
0R2J-2-GP C832 Size Document Number Rev
Custom
19,27,29,34,35,36,37,45,46,47,48,92,93 PM_SLP_S3# 20120112 PV-R R823 1 2 0R0402-PAD SC470P50V2KX-3GP
2012 S-Series Richie 13.3 -1
Date: Wednesday, March 14, 2012 Sheet 8 of 103
5 4 3 2 1
5 4 3 2 1

CPU(6/7)
IVY BRIDGE PROCESSOR (GND)
CPU1H 8 OF 9 CPU1I 9 OF 9
D D
AT35 VSS1 VSS81 AJ22
AT32 VSS2 VSS82 AJ19
AT29 IVY-BRIDGE AJ16 T35 IVY-BRIDGE F22
VSS3 VSS83 VSS161 VSS234
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30
AT22 VSS6 VSS86 AJ7 T32 VSS164 VSS237 E27
AT19 VSS7 VSS87 AJ4 T31 VSS165 VSS238 E24
AT16 VSS8 VSS88 AJ3 T30 VSS166 VSS239 E21
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18
AT10 VSS10 VSS90 AJ1 T28 VSS168 VSS241 E15
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6
AR16 VSS17 VSS98 AH25 P3 VSS175 VSS248 E5
AR13 VSS18 VSS99 AH22 P2 VSS176 VSS249 E4
AR10 VSS19 VSS100 AH19 N35 VSS177 VSS250 E3
AR7 VSS20 VSS101 AH16 N34 VSS178 VSS251 E2
AR4 VSS21 VSS102 AH7 N33 VSS179 VSS252 E1
AR2 VSS22 VSS103 AH4 N32 VSS180 VSS253 D35
AP34 VSS23 VSS104 AG9 N31 VSS181 VSS254 D32
AP31 VSS24 VSS105 AG8 N30 VSS182 VSS255 D29
AP28 VSS25 VSS106 AG4 N29 VSS183 VSS256 D26
AP25 VSS26 VSS107 AF6 N28 VSS184 VSS257 D20
AP22 VSS27 VSS108 AF5 N27 VSS185 VSS258 D17
AP19 VSS28 VSS109 AF3 N26 VSS186 VSS259 C34
C AP16 AF2 M34 C31 C
VSS29 VSS110 VSS187 VSS260
AP13 VSS30 VSS111 AE35 L33 VSS188 VSS261 C28
AP10 VSS31 VSS112 AE34 L30 VSS189 VSS262 C27
AP7 VSS32 VSS113 AE33 L27 VSS190 VSS263 C25
AP4 VSS33 VSS114 AE32 L9 VSS191 VSS264 C23
AP1 VSS34 VSS115 AE31 L8 VSS192 VSS265 C10
AN30 VSS35 VSS116 AE30 L6 VSS193 VSS266 C1
AN27 VSS36 VSS117 AE29 L5 VSS194 VSS267 B22
AN25 AE28 L4 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 VSS40 VSS121 AE9 L1 VSS198 VSS271 B13
AN13 VSS41 VSS122 AD7 K35 VSS199 VSS272 B11
AN10 VSS42 VSS123 AC9 K32 VSS200 VSS273 B9
AN7 VSS43 VSS124 AC8 K29 VSS201 VSS274 B8
AN4 VSS44 VSS125 AC6 K26 VSS202 VSS275 B7
AM29 VSS45 VSS126 AC5 J34 VSS203 VSS276 B5
AM25 VSS46 VSS127 AC3 J31 VSS204 VSS277 B3
AM22 VSS47 VSS128 AC2 H33 VSS205 VSS278 B2
AM19 VSS48 VSS129 AB35 H30 VSS206 VSS279 A35
AM16 VSS49 VSS130 AB34 H27 VSS207 VSS280 A32
AM13 VSS50 VSS131 AB33 H24 VSS208 VSS281 A29
AM10 VSS51 VSS132 AB32 H21 VSS209 VSS282 A26
AM7 VSS52 VSS133 AB31 H18 VSS210 VSS283 A23
AM4 VSS53 VSS134 AB30 H15 VSS211 VSS284 A20
AM3 VSS54 VSS135 AB29 H13 VSS212 VSS285 A3
AM2 VSS55 VSS136 AB28 H10 VSS213
AM1 VSS56 VSS137 AB27 H9 VSS214
AL34 VSS57 VSS138 AB26 H8 VSS215
B B
AL31 VSS58 VSS139 Y9 H7 VSS216
AL28 VSS59 VSS140 Y8 H6 VSS217
AL25 VSS60 VSS141 Y6 H5 VSS218
AL22 VSS61 VSS142 Y5 H4 VSS219
AL19 VSS62 VSS143 Y3 H3 VSS220
AL16 VSS63 VSS144 Y2 H2 VSS221
AL13 VSS64 VSS145 W35 H1 VSS222
AL10 VSS65 VSS146 W34 G35 VSS223
AL7 VSS66 VSS147 W33 G32 VSS224
AL4 VSS67 VSS148 W32 G29 VSS225
AL2 VSS68 VSS149 W31 G26 VSS226
AK33 VSS69 VSS150 W30 G23 VSS227
AK30 VSS70 VSS151 W29 G20 VSS228
AK27 VSS71 VSS152 W28 G17 VSS229
AK25 VSS72 VSS153 W27 G11 VSS230
AK22 VSS73 VSS154 W26 F34 VSS231
AK19 VSS74 VSS155 U9 F31 VSS232
AK16 VSS75 VSS156 U8 F29 VSS233
AK13 VSS76 VSS157 U6
AK10 VSS77 VSS158 U5
AK7 VSS78 VSS159 U3
AK4 VSS79 VSS160 U2
AJ25 VSS80

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(6/7) : GND
Size Document Number Rev
A3 -1
2012 S-Series Richie 13.3
Date: W ednesday, March 14, 2012 Sheet 9 of 103
5 4 3 2 1
5 4 3 2 1

CPU(7/7)
IVY BRIDGE PROCESSOR (RESERVED) CFG4
Display Port Presence Strap 0:Enable eDP

1
D DY R1006 D
1KR2J-1-GP CFG4 1:(Default) Disabled; No Physical Display Port
attached to Embedded Display Port

2
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
CPU1E 5 OF 9

IVY-BRIDGE
CFG7
VCC_DIE_SENSE AH27 VCC_DIE_SENSE 1 TP1004 TPAD14-OP-GP

1
AK28 CFG0 VSS_DIE_SENSE AH26
AK29 DY R1009
CFG2 CFG1
AL26 CFG2 1KR2J-1-GP
AL27 CFG3
CFG4 AK26 L7

2
CFG5 CFG4 RSVD#L7
AL29 CFG5 RSVD#AG7 AG7
CFG6 AL30 AE7
CFG7 CFG6 RSVD#AE7
AM31 CFG7 RSVD#AK2 AK2
AM32 CFG8

CFG
AM30 CFG9 RSVD#W8 W8
AM28 CFG10
AM26 CFG11 PEG DEFER TRAINING
AN28 CFG12 RSVD#AT26 AT26
AN31 CFG13 RSVD#AM33 AM33
AN26 CFG14 RSVD#AJ27 AJ27 CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion
AM27 CFG15 0: PEG Wait for BIOS for training
AK31 CFG16
C AN29 C
CFG17

VCC_GFXCORE T8
RSVD#T8
VCC_CORE 49D9R2F-GP
DY R1001 VAXG_VAL_SENSE RSVD#J16 J16

49D9R2F-GP
1 DY 2
R1002 VSSAXG_VAL_SENSE
AJ31 VAXG_VAL_SENSE RSVD#H16 H16
1 2 AH31 VSSAXG_VAL_SENSE RSVD#G16 G16
49D9R2F-GP 1 DY 2 R1003 VCC_VAL_SENSE AJ33
49D9R2F-GP R1004 VSS_VAL_SENSE VCC_VAL_SENSE
1 DY 2 AH33 VSS_VAL_SENSE

AJ26 RSVD#AJ26 RSVD_NCTF#AR35 AR35

RESERVED
RSVD_NCTF#AT34 AT34
AT33 CFG2
RSVD_NCTF#AT33
RSVD_NCTF#AP35 AP35 PEG Static Lane Reversal

1
RSVD_NCTF#AR34 AR34
R1005 1:(Default) Normal Operation; Lane #
1KR2J-1-GP CFG2 definition matches socket pin map definition
F25 RSVD#F25
F24 0:Lane Reversed

2
RSVD#F24
F23 RSVD#F23
D24 RSVD#D24 RSVD_NCTF#B34 B34
G25 RSVD#G25 RSVD_NCTF#A33 A33
G24 RSVD#G24 RSVD_NCTF#A34 A34
E23 RSVD#E23 RSVD_NCTF#B35 B35
D23 C35 CFG6 CFG5
RSVD#D23 RSVD_NCTF#C35
C30 RSVD#C30

1
A31 RSVD#A31
B30 DY R1007 DY R1008
B RSVD#B30 B
B29 RSVD#B29 1KR2J-1-GP 1KR2J-1-GP
D30 RSVD#D30 RSVD#AJ32 AJ32
B31 AK32

2
RSVD#B31 RSVD#AK32
A30 RSVD#A30
C29 RSVD#C29

BCLK_ITP AN35 CLK_XDP_ITP_P1 TP1024 TPAD14-OP-GP


J20 RSVD#J20 BCLK_ITP# AM35 CLK_XDP_ITP_N1 TP1025 TPAD14-OP-GP
B18 RSVD#B18
PCIE Port Bifurcation Straps

J15 RSVD#J15 RSVD_NCTF#AT2 AT2 CFG[6:5] 11: (Default) x16 - Device 1 functions 1 and 2 disabled
RSVD_NCTF#AT1 AT1 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
RSVD_NCTF#AR1 AR1
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(7/7): CFG/RSVD/DDR3_VREF
Size Document Number Rev
A3 -1
2012 S-Series Richie 13.3
Date: W ednesday, March 14, 2012 Sheet 10 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_XDP
Size Document Number Rev
A3 -1
2012 S-Series Richie 13.3
Date: W ednesday, March 14, 2012 Sheet 11 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RESERVED
Size Document Number Rev
A3 -1
2012 S-Series Richie 13.3
Date: W ednesday, March 14, 2012 Sheet 12 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RESERVED
Size Document Number Rev
A3 -1
2012 S-Series Richie 13.3
Date: W ednesday, March 14, 2012 Sheet 13 of 103
5 4 3 2 1
5 4 3 2 1

DIMM1 M_A_DQS#[7:0] 6

M_A_DQS[7:0] 6
DIMM1 M_A_A[15:0] 6
M_A_A0 98 NP1
M_A_A1 A0 NP1
97 A1 NP2 NP2
M_A_A2 96
M_A_A3 A2
95 A3 RAS# 110 M_A_RAS# 6
M_A_A4 92 113 M_A_WE# 6
M_A_A5 A4 WE#
91 A5 CAS# 115 M_A_CAS# 6
M_A_A6 90
M_A_A7 A6
D 86 A7 CS0# 114 M_A_DIM0_CS#0 6 D
M_A_A8 89 121 M_A_DIM0_CS#1 6
M_A_A9 A8 CS1#
85 A9
M_A_A10 107 73 M_A_DIM0_CKE0 6 SA0_DIM0
M_A_A11 A10/AP CKE0
M_A_A12
84 A11 CKE1 74 M_A_DIM0_CKE1 6
SA1_DIM0
Note:
83 A12
M_A_A13 119 101 M_A_DIM0_CLK_DDR0 6
If SA0 DIM0 = 0, SA1_DIM0 = 0
M_A_A14 A13 CK0
80 A14 CK0# 103 M_A_DIM0_CLK_DDR#0 6 SO-DIMMA SPD Address is 0xA0

2
1
M_A_A15 78 A15 RN1402 SO-DIMMA TS Address is 0x30
79 A16/BA2 CK1 102 M_A_DIM0_CLK_DDR1 6
6 M_A_BS2
CK1# 104 M_A_DIM0_CLK_DDR#1 6 SRN10KJ-5-GP
6 M_A_BS0 109 BA0
6 M_A_BS1
108 BA1 DM0 11 If SA0 DIM0 = 1, SA1_DIM0 = 0
28 SO-DIMMA SPD Address is 0xA2

3
4
6 M_A_DQ[63:0] M_A_DQ0 DM1
5 DQ0 DM2 46
M_A_DQ1 7 DQ1 DM3 63 SO-DIMMA TS Address is 0x32
M_A_DQ2 15 136
M_A_DQ3 DQ2 DM4
17 DQ3 DM5 153
M_A_DQ4 4 170
M_A_DQ5 DQ4 DM6
6 DQ5 DM7 187
M_A_DQ6 16 RN1401 0R4P2R-PAD
M_A_DQ7 DQ6 SODIMM1_1_SMB_DATA_R
18 DQ7 SDA 200 2 3 PCH_SMBDATA 15,18,31,65
M_A_DQ8 21 202 SODIMM1_1_SMB_CLK_R 1 4
DQ8 SCL PCH_SMBCLK 15,18,31,65
M_A_DQ9 23
M_A_DQ10 DQ9
33 DQ10 EVENT# 198 TS#_DIMM0_1 15

RN
M_A_DQ11 35
M_A_DQ12 DQ11
22 DQ12 VDDSPD 199 3D3V_S0
M_A_DQ13 24 3D3V_S0
DQ13

1
M_A_DQ14 34 197 SA0_DIM0 C1401 C1402
M_A_DQ15 DQ14 SA0 SA1_DIM0
36 DQ15 SA1 201

SCD1U16V2ZY-2GP

SC2D2U6D3V3KX-GP
M_A_DQ16 39

2
DQ16

1
M_A_DQ17 41 77
M_A_DQ18 DQ17 NC#77 R1402
51 DQ18 NC#122 122
C M_A_DQ19 53 125 1D5V_S3 10KR2J-3-GP C
M_A_DQ20 DQ19 NC#125/TEST
40
M_A_DQ21 42
DQ20
75 Thermal EVENT

2
M_A_DQ22 DQ21 VDD
50 DQ22 VDD 76
M_A_DQ23 52 81
M_A_DQ24 DQ23 VDD
57 DQ24 VDD 82
M_A_DQ25 59 87
M_A_DQ26 DQ25 VDD TS#_DIMM0_1
67 DQ26 VDD 88
M_A_DQ27 69 93
DDR_VREF_S3 1D5V_S3 M_A_DQ28 DQ27 VDD
56 DQ28 VDD 94
M_A_DQ29 58 99 SODIMM A DECOUPLING
M_A_DQ30 DQ29 VDD
68 DQ30 VDD 100
M_A_DQ31 70 105
DQ31 VDD
1

R1403 M_A_DQ32 129 106 1D5V_S3


R1401 1KR2F-3-GP M_A_DQ33 DQ32 VDD
131 DQ33 VDD 111
0R2J-2-GP M_A_DQ34 141 112
M_A_DQ35 DQ34 VDD
DY M_A_DQ36
143 DQ35 VDD 117
130 118
2

M_VREF_CA_DIMM0 M_A_DQ37 DQ36 VDD


132 DQ37 VDD 123
M_A_DQ38 140 124 C1407 C1408 C1409 C1410 C1411 C1412
DQ38 VDD
1

1
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
DY M_A_DQ39 142 DQ39
1

R1405 C1403 C1404 M_A_DQ40 147 2


1KR2F-3-GP SCD1U10V2KX-4GP SC2D2U6D3V3KX-GP M_A_DQ41 DQ40 VSS
149 3
2

2
M_A_DQ42 DQ41 VSS
157 DQ42 VSS 8
M_A_DQ43 159 9
M_A_DQ44 DQ43 VSS
146 13
2

M_A_DQ45 DQ44 VSS


148 DQ45 VSS 14
M_A_DQ46 158 19
M_A_DQ47 DQ46 VSS
160 DQ47 VSS 20
M_A_DQ48 163 25
DDR_VREF_S3 1D5V_S3 M_A_DQ49 DQ48 VSS
165 DQ49 VSS 26
M_A_DQ50 175 31 C1413 C1414 C1415 C1416 C1417 C1418 C1419
DQ50 VSS

1
M_A_DQ51 177 32
DQ51 VSS
1

SCD1U10V2KX-5GP
B M_A_DQ52 164 37 B
DQ52 VSS
1

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
R809 R1406 M_A_DQ53 166 38

2
1KR2F-3-GP M_A_DQ54 DQ53 VSS
0R2J-2-GP 174 DQ54 VSS 43
DY M_A_DQ55 176 44 Layout Note:
M_A_DQ56 DQ55 VSS
181 48
2

M_A_DQ57 DQ56 VSS Place these Caps near


183 49
2

M_A_DQ58 DQ57 VSS


M_VREF_DQ_DIMM0 M_A_DQ59
191 DQ58 VSS 54 SO-DIMMA.
193 DQ59 VSS 55
M_A_DQ60 180 60
DQ60 VSS
1

R1407 DY M_A_DQ61 182 61


1KR2F-3-GP C1405 C1406 M_A_DQ62 DQ61 VSS
192 DQ62 VSS 65
SCD1U10V2KX-4GP SC2D2U10V3ZY-1GP M_A_DQ63 194 66
2

DQ63 VSS
VSS 71
M_A_DQS#0 10 72
2

M_A_DQS#1 DQS0# VSS


27 DQS1# VSS 127
M_A_DQS#2 45 128
M_A_DQS#3 DQS2# VSS
62 DQS3# VSS 133
M_A_DQS#4 135 134
M_A_DQS#5 DQS4# VSS
152 DQS5# VSS 138
M_A_DQS#6 169 139
M_A_DQS#7 DQS6# VSS
186 DQS7# VSS 144
VSS 145
M_A_DQS0 12 150
M_A_DQS1 DQS0 VSS
29 DQS1 VSS 151
0D75V_S0 M_A_DQS2
Place these caps 47 DQS2 VSS 155
M_A_DQS3 64 156
close to VTT1 and M_A_DQS4 137
DQS3 VSS
161
M_A_DQS5 DQS4 VSS
VTT2. C1422 C1423 M_A_DQS6
154 DQS5 VSS 162
171 DQS6 VSS 167
1

C1420 C1421 DY DY M_A_DQS7 188 168


DQS7 VSS
VSS 172
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

116 173
2

6 M_A_DIM0_ODT0 ODT0 VSS


6 M_A_DIM0_ODT1
120 ODT1 VSS 178
A
VSS 179 A
M_VREF_CA_DIMM0 126 184
VREF_CA VSS
8 M_VREF_DQ_DIMM0
1 VREF_DQ VSS 185 <Core Design>
VSS 189
5,15,97 DDR3_DRAMRST#
30 RESET# VSS 190
0D75V_S0 VSS
VSS
195
196 Wistron Corporation
203 205 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VTT1 VSS Taipei Hsien 221, Taiwan, R.O.C.
204 VTT2 VSS 206
Title
DDR3-204P-168-GP
Bom Not: 1st/2nd/3rd Add in BOM 1st = 62.10024.I91 H=9.2mm Size
DDR3 SO-DIMM1
Document Number Rev
2nd = 62.10017.U01 Custom
3rd = 62.10024.H81 2012 S-Series Richie 13.3 -1
Date: Wednesday, March 14, 2012 Sheet 14 of 103
5 4 3 2 1
5 4 3 2 1

M_B_A0
M_B_A1
98
97
DIMM2

A0 NP1 NP1
NP2
DIMM2
6 M_B_A[15:0] A1 NP2
M_B_A2 96
M_B_A3 A2
6 M_B_DQS#[7:0] 95 A3 RAS# 110 M_B_RAS# 6
M_B_A4 92 113 M_B_WE# 6
M_B_A5 A4 WE# 3D3V_S0
6 M_B_DQS[7:0] 91 A5 CAS# 115 M_B_CAS# 6
M_B_A6 90
M_B_A7 A6
86 A7 CS0# 114 M_B_DIM0_CS#0 6
M_B_A8 89 121 M_B_DIM0_CS#1 6
M_B_A9 A8 CS1#
85 A9
M_B_A10 107 73 M_B_DIM0_CKE0 6
M_B_A11 A10/AP CKE0
84 A11 CKE1 74 M_B_DIM0_CKE1 6
D M_B_A12 83 D
M_B_A13 A12
119 A13 CK0 101 M_B_DIM0_CLK_DDR0 6
M_B_A14 80 103 M_B_DIM0_CLK_DDR#0 6 RN1502
M_B_A15 A14 CK0# SB1_DIM0
78 A15 1 4
79 102 M_B_DIM0_CLK_DDR1 6 SB0_DIM0 2 3 Note:
6 M_B_BS2 A16/BA2 CK1
CK1# 104 M_B_DIM0_CLK_DDR#1 6 SO-DIMMB SPD Address is 0xA4
109 SRN10KJ-5-GP SO-DIMMB TS Address is 0x34
6 M_B_BS0 BA0
6 M_B_BS1
108 BA1 DM0 11
6 M_B_DQ[63:0] DM1 28
M_B_DQ0 5 46
M_B_DQ1 DQ0 DM2
7 DQ1 DM3 63
M_B_DQ2 15 136
M_B_DQ3 DQ2 DM4
17 DQ3 DM5 153
M_B_DQ4 4 170
DQ4 DM6

RN
M_B_DQ5 6 187
M_B_DQ6 DQ5 DM7 RN1501 0R4P2R-PAD
16 DQ6
M_B_DQ7 18 200 SODIMM0_1_SMB_DATA_R 1 4
DQ7 SDA PCH_SMBDATA 14,18,31,65
M_B_DQ8 21 202 SODIMM0_1_SMB_CLK_R 2 3
DQ8 SCL PCH_SMBCLK 14,18,31,65
M_B_DQ9 23
M_B_DQ10 DQ9 3D3V_S0
33 DQ10 EVENT# 198 TS#_DIMM0_1 14
M_B_DQ11 35
M_B_DQ12 DQ11
22 DQ12 VDDSPD 199
M_B_DQ13 24 DQ13

1
M_B_DQ14 34 197 SB0_DIM0 C1504 DY C1505
M_B_DQ15 DQ14 SA0 SB1_DIM0
36 DQ15 SA1 201

SCD1U16V2ZY-2GP
M_B_DQ16 39 SC2D2U10V3ZY-1GP

2
M_B_DQ17 DQ16
41 DQ17 NC#1 77
M_B_DQ18 51 122
M_B_DQ19 DQ18 NC#2 1D5V_S3
53 DQ19 NC#/TEST 125
M_B_DQ20 40
M_B_DQ21 DQ20
42 DQ21 VDD1 75
M_B_DQ22 50 76
M_B_DQ23 DQ22 VDD2
52 DQ23 VDD3 81
C M_B_DQ24 57 82 C
M_B_DQ25 DQ24 VDD4
59 DQ25 VDD5 87
M_B_DQ26 67 88
M_B_DQ27 DQ26 VDD6
69 DQ27 VDD7 93
M_B_DQ28 56 94
M_B_DQ29 DQ28 VDD8
58 DQ29 VDD9 99
M_B_DQ30 68 100
M_B_DQ31 DQ30 VDD10
70 DQ31 VDD11 105
M_B_DQ32 129 106
DDR_VREF_S3 1D5V_S3 M_B_DQ33 DQ32 VDD12
131 DQ33 VDD13 111
M_B_DQ34 141 112
M_B_DQ35 DQ34 VDD14
143 DQ35 VDD15 117
M_B_DQ36 130 118 SODIMM B DECOUPLING
DQ36 VDD16
1

R1506 M_B_DQ37 132 123


R1501 1KR2F-3-GP M_B_DQ38 DQ37 VDD17 1D5V_S3
140 DQ38 VDD18 124
0R2J-2-GP M_B_DQ39 142
M_B_DQ40 DQ39
DY M_B_DQ41
147 DQ40 VSS 2
149 3
2

M_B_DQ42 DQ41 VSS


157 DQ42 VSS 8
M_VREF_CA_DIMM1 M_B_DQ43 159 9
M_B_DQ44 DQ43 VSS C1508 C1509 C1510 C1511 C1512 C1513
146 DQ44 VSS 13
1

1
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
DY M_B_DQ45 148 14 TC1401
DQ45 VSS
1

1
SE330U2D5VDM-1GP
R1507 C1506 C1507 M_B_DQ46 158 19
1KR2F-3-GP SCD1U10V2KX-4GP SC2D2U6D3V3KX-GP M_B_DQ47 DQ46 VSS
160 20 1st = 77.23371.13L
2

2
M_B_DQ48 DQ47 VSS
163 25 2ND = 79.33719.L01

2
M_B_DQ49 DQ48 VSS
165 DQ49 VSS 26 3rd = 77.23371.13L
M_B_DQ50 175 31
2

M_B_DQ51 DQ50 VSS


177 DQ51 VSS 32
M_B_DQ52 164 37
M_B_DQ53 DQ52 VSS
166 DQ53 VSS 38
M_B_DQ54 174 43
M_B_DQ55 DQ54 VSS
176 DQ55 VSS 44
DDR_VREF_S3 1D5V_S3 M_B_DQ56 181 48 C1516 C1517 C1518 C1519 C1521 C1520 C1522
DQ56 VSS

1
B M_B_DQ57 183 49 Layout Note: B
M_B_DQ58 DQ57 VSS
191 54
DQ58 VSS Place these Caps near

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
M_B_DQ59 193 55

2
DQ59 VSS
1

R1508 M_B_DQ60 180 60 SO-DIMMB.


R808 1KR2F-3-GP M_B_DQ61 DQ60 VSS
182 DQ61 VSS 61
0R2J-2-GP M_B_DQ62 192 65
M_B_DQ63 DQ62 VSS
DY 194 DQ63 VSS 66
71
2

M_VREF_DQ_DIMM1 M_B_DQS#0 VSS


10 DQS0# VSS 72
M_B_DQS#1 27 127
DQS1# VSS
1

DY M_B_DQS#2 45 128
DQS2# VSS
1

R1509 C1514 C1515 M_B_DQS#3 62 133


1KR2F-3-GP SCD1U10V2KX-4GP SC2D2U10V3ZY-1GP M_B_DQS#4 DQS3# VSS
135 134
2

M_B_DQS#5 DQS4# VSS


152 DQS5# VSS 138
M_B_DQS#6 169 139
M_B_DQS#7 DQS6# VSS
186 144
2

DQS7# VSS
VSS 145
M_B_DQS0 12 150
M_B_DQS1 DQS0 VSS
29 DQS1 VSS 151
M_B_DQS2 47 155
M_B_DQS3 DQS2 VSS
64 DQS3 VSS 156
M_B_DQS4 137 161
M_B_DQS5 DQS4 VSS
154 DQS5 VSS 162
M_B_DQS6 171 167
M_B_DQS7 DQS6 VSS
188 DQS7 VSS 168
VSS 172
6 M_B_DIM0_ODT0
116 ODT0 VSS 173
6 M_B_DIM0_ODT1
120 ODT1 VSS 178
VSS 179
M_VREF_CA_DIMM1 126 184
VREF_CA VSS
8 M_VREF_DQ_DIMM1
1 VREF_DQ VSS 185
VSS 189
Place these caps 0D75V_S0 5,14,97 DDR3_DRAMRST#
30 RESET# VSS 190
A
VSS 195 A
close to VTT1 and 196
VSS
VTT2. 203 VTT1 VSS 205 <Core Design>
204 VTT2 VSS 206

C1523 C1501 C1502 C1503 DDR3-204P-85-GP-U Wistron Corporation


1

1
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


DY DY Taipei Hsien 221, Taiwan, R.O.C.
62.10017.U21 H=5.2mm
2

Title
2nd = 62.10017.T91
3rd = 62.10024.I61
Size Document Number
DDR3 SO-DIMM2 Rev
Custom
2012 S-Series Richie 13.3 -1
Date: Wednesday, March 14, 2012 Sheet 15 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RESERVED
Size Document Number Rev
A3 -1
2012 S-Series Richie 13.3
Date: W ednesday, March 14, 2012 Sheet 16 of 103
5 4 3 2 1
A B C D E

RTC_X1 RTC_AUX_S5 R1705 PCH(1/9)


1
20KR2J-L2-GP
2 INTVRMEN- Integrated
SUS 1.05V VRM Enable LPC_AD[3:0] 27,71

1
R1706
1 2 RTC_X2 C1701 1 DY 2 PCH_INTVRMEN High - Enable internal VRs
10MR2J-L-GP SC1U10V2KX-1GP R1707 330KR2J-L1-GP

2
PCH1A 1 OF 10
X1701 RTC_AUX_S5
X-32D768KHZ-34GPU R1708 RTC_X1 A20 C38 LPC_AD0
RTCX1 FWH0/LAD0 LPC_AD1
4 1 2 FWH1/LAD1 A38 4

LPC
1 4 RTC_X2 C20 B37 LPC_AD2
RTCX2 FWH2/LAD2

2
20KR2J-L2-GP C37 LPC_AD3
FWH3/LAD3
1

1
C1702 C1703 G1701 RTC_RST# D20
7pF20PPM RTCRST#
SC6P50V2CN-1GP

SC6P50V2CN-1GP
C1704 SRTC_RST# D36 LPC_FRAME#_R 1 2
SC1U10V2KX-1GP GAP-OPEN FWH4/LFRAME# R1726 22R2J-2-GP LPC_FRAME# 27,71
2 3 54,97 INTRUDER# G22
2

2
SRTCRST#
20120312MV E36

1
LDRQ0#

RTC
RTC_AUX_S5 R1709
1 2 1MR2J-1-GP K22 K36
INTRUDER# LDRQ1#/GPIO23 PCH_GPIO23 TP1701 TPAD14-OP-GP
1
R1710
1 2 330KR2J-L1-GP PCH_INTVRMEN C17 V5
INTVRMEN SERIRQ SIRQ 27,71
RN1701
82.30001.661 29,97 HDA_SDOUT_CODEC 1 8
29,97 HDA_RST#_CODEC 2 7 SATA0RXN AM3 SATA_RXN0 56
2ND = 82.30001.B21 HDA_BIT_CLK
29,97 HDA_BITCLK_CODEC 3 6 N34 HDA_BCLK SATA0RXP AM1 SATA_RXP0 56 HDD

SATA 6G
29 HDA_SYNC_CODEC 4 5 SATA0TXN AP7 SATA_TXN0 56
HDA_SYNC L34 AP5
SRN33J-7-GP HDA_SYNC SATA0TXP SATA_TXP0 56
R1711 1 2 PCH_HDA_SPKR T10 AM10
29 HDA_SPKR SPKR SATA1RXN SATA_RXN1 56
0R0402-PAD AM8
SATA1RXP SATA_RXP1 56
20120112 PV-R PCH_HDA_RST# K34
HDA_RST# SATA1TXN AP11
AP10
SATA_TXN1 56 ODD
HDA_SYNC_C SATA1TXP SATA_TXP1 56
E34 HDA_SDIN0 SATA2RXN AD7
SATA2RXP AD5
G34 HDA_SDIN1 SATA2TXN AH5
SATA2TXP AH4
C34 HDA_SDIN2
3D3V_S5

IHDA
29 HDA_SDIN0_CODEC SATA3RXN AB8
A34 HDA_SDIN3 SATA3RXP AB10
3 AF3 3
HDA_SDO_R SATA3TXN
SATA3TXP AF1
1

HDA_SDO A36
R1725 HDA_SDO

SATA
SATA4RXN Y7
1KR2J-1-GP 1KR2J-1-GP Y5
R1712 1 HDD_HALTLED_R SATA4RXP
68 HDD_HALTLED 2 C36 HDA_DOCK_EN#/GPIO33 SATA4TXN AD3
AD1
2

ISO_PREP# SATA4TXP
N32 HDA_DOCK_RST#/GPIO13
Y3
BAT_GRNLED#_S

SATA5RXN
SATA5RXP Y1
SATA5TXN AB3
PCH_JTAG_TCK_BUF J3 AB1
JTAG_TCK SATA5TXP
PCH_JTAG_TMS H7 Y11 1D05V_S0
JTAG_TMS SATAICOMPO

JTAG
PCH_JTAG_TDI K5 Y10 SATA_COMP R1713 1 2 37D4R2F-GP
10KR2J-3-GP JTAG_TDI SATAICOMPI
R1701
84.00084.F31 PCH_JTAG_TDO H1
S

JTAG_TDO 1D05V_S0
2nd = 84.BSS84.B31 SATA3RCOMPO AB12
27,82 BAT_GRNLED# 1 2BAT_GRNLED#_G G
AB13 SATA3_COMP R1714 1 2 49D9R2F-GP 3D3V_S0
BSS84-7-F-GP SATA3COMPI
Q1701

1
T3 AH1 RBIAS_SATA3 1 2
D

60 PCH_SPI_CLK SPI_CLK SATA3RBIAS R1715 750R2F-GP


Y14 NEED TO PLACE CLOSE TO PCH R1716
BAT_GRNLED#_D

60 PCH_SPI_CS#0 SPI_CS0# 10KR2J-3-GP


T1

2
27,71 SPI_CS1# SPI_CS1#

SPI
P3 SATA_LED#
2 SATALED# SATA_LED# 68 2

60 PCH_SPI_MOSI V4 SPI_MOSI SATA0GP/GPIO21 V14 SATA0GP_GPIO21 22

60 PCH_SPI_MISO U3 SPI_MISO SATA1GP/GPIO19 P1 SATA_ODD_DET# 56


10KR2J-3-GP
R1702 84.00084.F31 PANTHER-GP-NF
S

3D3V_S5
5,21,32,34,53,54,56,71,83,96,97 PLT_RST# 1 2PLT_RST#_G G 2nd = 84.BSS84.B31 R1724 1 2 1KR2J-1-GP HDA_SYNC
BSS84-7-F-GP
Q1702 R1729 1
RTC Battery 3D3V_AUX_S5
2 10KR2J-3-GP ISO_PREP#
RTC_AUX_S5
D

U1701

2
For Flash Descriptor Security Override HW strap 3D3V_S5 +RTC_VCC
RTC1 3
PCHXDP R1717 1 2 210R2F-L-GP PCH_JTAG_TMS
PCHXDP R1718 1 2 210R2F-L-GP PCH_JTAG_TDO 1 +RTC_VCC 1 2 RTC_PW R 1
PWR

1
PCHXDP R1719 1 2 210R2F-L-GP PCH_JTAG_TDI 2 R1720 1KR2J-1-GP
5V_S0 GND C1705
NP1 NP1
CH715FGP-GP-U SC1U10V3ZY-6GP
NO REBOOT STRAP RN1703 NP2

2
PCH_JTAG_TDO NP2
1 8
PCH_JTAG_TDI
83.R0304.D81
No Reboot Strap R710 2 7
2ND = 83.00040.E81
Low = Default PCHXDP 3 6 PCH_JTAG_TMS BAT-060003HA002M213ZL-GP-U
4
3

HDA_SPKR High = No Reboot 4 5 62.70014.001 20120210PV-R


RN1702
3D3V_S0 SRN100J-4-GP
1 SRN10KJ-5-GP
R1721 1
2nd = 62.70001.061 <Core Design> 1
PCHXDP 2 51R2J-2-GP PCH_JTAG_TCK_BUF
R1727 1 DY 2 1KR2J-1-GP HDD_HALTLED_R
HDA_SPKR R1728 1 2 20KR2J-L2-GP HDA_SDO 20120314 MV
1 2
Wistron Corporation
1
2

R1722 10KR2J-3-GP HDA_SDO_G


20120315 MV 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
DY HDA_SDO_G U1704
Taipei Hsien 221, Taiwan, R.O.C.
HDA_SYNC_C 1 6 HDA_SYNC LAYOUT NOTE:
Title
84.2N702.A3F JTAG_TMS TERMINATIONS NEED TO BE PLACED NEAR PCH
SIRQ
2 5 2nd = 84.2N702.E3F JTAG_TDI TERMINATIONS NEED TO BE PLACED NEAR PCH PCH(1/9) : HDA/JTAG/SATA
1
R1723
2
10KR2J-3-GP HDA_SDO HDA_SDO_R
3rd = 84.2N702.F3F JTAG_TDO TERMINATIONS NEED TO BE PLACED NEAR XDP Size Document Number Rev
3 4
JTAG_TCK TERMINATIONS NEED TO BE PLACED NEAR PCH A3 -1
2012 S-Series Richie 13.3
2N7002KDW -GP Date: W ednesday, March 14, 2012 Sheet 17 of 103
A B C D E
A B C D E

PCH1B PCH(2/9) 2 OF 10 R1806 2 1


3D3V_S5

10KR2J-3-GP
3D3V_S0

4
3
BG34 PERN1
BJ34 E12 RN1803 3D3V_S0
PERP1 SMBALERT#/GPIO11 FPR_OFF 64,97
AV32 PETN1 SRN2K2J-1-GP
AU32 H14 PCH_SMB_CLK
PETP1 SMBCLK 3D3V_S5
BE34 C9 PCH_SMB_DATA

1
2
PERN2 SMBDATA
BF34 PERP2
BB32 R1807 1 2
PETN2 U1801
AY32 1KR2J-1-GP
PETP2

SMBUS
4 A12 14,15,31,65 PCH_SMBDATA 1 6 PCH_SMB_DATA 4
SML0ALERT#/GPIO60 PCH_DDR_RST# 5
32 PCIE_RXN3_MEDIA BG36 PERN3
BJ36 C8 PCH_SML0_CLK 2 5
Media 32 PCIE_RXP3_MEDIA C1805 1 2 SCD1U10V2KX-5GP PCIE_TXN3_C AV34
PERP3 SML0CLK
32 PCIE_TXN3_MEDIA PETN3
32 PCIE_TXP3_MEDIA C1806 1 2 SCD1U10V2KX-5GP PCIE_TXP3_C AU34 G12 PCH_SML0_DATA PCH_SMB_CLK 3 4 PCH_SMBCLK 14,15,31,65
PETP3 SML0DATA
BF36 2N7002KDW -GP
53 PCIE_RXN4_W LAN PERN4
WLAN 53 PCIE_RXP4_W LAN C1809 1
BE36 PERP4 84.2N702.A3F
53 PCIE_TXN4_W LAN 2 SCD1U10V2KX-5GP PCIE_TXN4_C AY34 PETN4 SML1ALERT#/PCHHOT#/GPIO74 C13 PCH_GPIO74 2nd = 84.2N702.E3F
C1807 1 2 SCD1U10V2KX-5GP PCIE_TXP4_C 3D3V_S5
53 PCIE_TXP4_W LAN BB34 PETP4 PCH_SML1CLK
3rd = 84.2N702.F3F
SML1CLK/GPIO58 E14

PCI-E*
BG37 PERN5

1
BH37 M16 PCH_SML1DATA
PERP5 SML1DATA/GPIO75 R1801
AY36 PETN5
BB36 PETP5 10KR2J-3-GP

34 PCIE_RXN6_LAN BJ38 84.2N702.J31

2
PERN6
LAN 34 PCIE_RXP6_LAN
C1810 1
BG38 PERP6 2nd = 84.07002.I31
2 SCD1U10V2KX-5GP PCIE_TXN6_C

Controller
34 PCIE_TXN6_LAN
C1811 1
AU36 PETN6 CL_CLK1 M7 3rd = 84.2N702.W31
34 PCIE_TXP6_LAN 2 SCD1U10V2KX-5GP PCIE_TXP6_C AV36 PETP6 2N7002K-2-GP
DIS_PX

Link
BG40 PERN7 CL_DATA1 T11 G PE_PW RGD 22,86,92,93,96,97
BJ40 PERP7
AY40 PETN7 D
BB40 PETP7 CL_RST1# P10 3D3V_AUX_S5
S 3D3V_S5
BE38 PERN8

4
3
2
1
BC38 PERP8 Q1801
AW38 RN1802
3 PETN8 3
AY38 PETP8 SRN2K2J-4-GP
R1808
M10 CLKREQ_PEG_A# 2 1 10KR2J-3-GP
PEG_A_CLKRQ#/GPIO47 DY

RN
Y40

5
6
7
8
CLKOUT_PCIE0N RN1810 PCH_SML1DATA
Y39 CLKOUT_PCIE0P
AB37 CLKOUT_PEG_A_N 1 4 3D3V_S5
GPIO73 CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLK_PCIE_VGA# 83 PCH_SML1CLK

CLOCKS
J2 PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P AB38 2 3 CLK_PCIE_VGA 83
0R4P2R-PAD 20120116PV-R
20120212 MV AB49 AV22 U1802
CLKOUT_PCIE1N CLKOUT_DMI_N CLKOUT_DMI_N 5 PCH_SML1DATA
20120112 PV-R AB47 CLKOUT_PCIE1P CLKOUT_DMI_P AU22 CLKOUT_DMI_P 5 1 6
PCH_KBC_DATA 27,28,85
R1804
1 2 GPIO18 M1 2 5
54 W W AN_DET# 0R2J-2-GP PCIECLKRQ1#/GPIO18
CLKOUT_DP_N AM12
AM13 CLOCK TERMINATION FOR FCIM 3 4 PCH_SML1CLK
CLKOUT_DP_P 27,28,85 PCH_KBC_CLK
AA48 CLKOUT_PCIE2N
AA47 RN1806
CLKOUT_PCIE2P CLK_BUF_EXP_N 2N7002KDW -GP
CLKIN_DMI_N BF18 1 4
GPIO20 V10 BE18 CLK_BUF_EXP_P 2 3 SRN10KJ-5-GP 84.2N702.A3F
PCIECLKRQ2#/GPIO20 CLKIN_DMI_P
RN1807
2nd = 84.2N702.E3F
CLK_BUF_CPYCLK_N
3rd = 84.2N702.F3F
32 CLK_PCIE_MEDIA# Y37 CLKOUT_PCIE3N CLKIN_GND1_N BJ30 2 3
Media 32 CLK_PCIE_MEDIA Y36 CLKOUT_PCIE3P CLKIN_GND1_P BG30 CLK_BUF_CPYCLK_P 1 4 SRN10KJ-5-GP

32 CLKREQ_MEDIA# A8 RN1808 3D3V_S5


PCIECLKRQ3#/GPIO25 CLK_BUF_DOT96_N
CLKIN_DOT_96N G24 1 4

4
3
2
1
E24 CLK_BUF_DOT96_P 2 3 SRN10KJ-5-GP
CLKIN_DOT_96P RN1801
53 CLK_PCIE_W LAN# Y43 CLKOUT_PCIE4N
WLAN Y45 RN1809 SRN2K2J-4-GP
2 53 CLK_PCIE_W LAN CLKOUT_PCIE4P CLK_BUF_CKSSCD_N 2
CLKIN_SATA_N AK7 1 4
L12 AK5 CLK_BUF_CKSSCD_P 2 3 SRN10KJ-5-GP
53 CLKRQ_W LAN# PCIECLKRQ4#/GPIO26 CLKIN_SATA_P

5
6
7
8
V45 K45 CLK_BUF_REF14 R1802 1 2 10KR2J-3-GP
CLKOUT_PCIE5N REFCLK14IN PCH_SML0_DATA
V46 CLKOUT_PCIE5P
All resistors need very close to PCH PCH_SML0_CLK
GPIO44 L14 H45 PCH_SMB_CLK
PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK PCH_SMB_DATA
CLK_PCI_FB 21
AB42 V47 XTAL25_IN
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49

GPIO56 E6 1D05V_S0
PEG_B_CLKRQ#/GPIO56
Y47 XCLK_RCOMP 1 2
XCLK_RCOMP R1803 90D9R2F-1-GP
34 CLK_PCIE_LAN# V40 CLKOUT_PCIE6N
LAN 34 CLK_PCIE_LAN V42 CLKOUT_PCIE6P

34 CLKREQ_LAN# T13 PCIECLKRQ6#/GPIO45


V38 K43 CLK_48_USB30 1 TP1801 TPAD14-OP-GP
FLEX CLOCKS

CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64
V37 CLKOUT_PCIE7P
F47 CLK_27_NSSC 1 TP1802 TPAD14-OP-GP
CLKRQ_W W AN# CLKOUTFLEX1/GPIO65
K12 PCIECLKRQ7#/GPIO46
H47 CLK_48_KBC_PCH_SIO 1 TP1803TPAD14-OP-GP
TPAD14-OP-GP
TP1805
T P1805 PCIE_CLK_XDP_N CLKOUTFLEX2/GPIO66
1 AK14 CLKOUT_ITPXDP_N
TPAD14-OP-GP
TP1806
T P1806 1 PCIE_CLK_XDP_P AK13 K49 CLK_14M_KBC_P 1 TP1804TPAD14-OP-GP
CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67
1 <Core Design> 1

PANTHER-GP-NF XTAL25_IN 1 2
RN1804 C1801
CLKREQ_LAN# 1 10
3D3V_S5 3D3V_S0 SC15P50V2JN-2-GP Wistron Corporation
1

PCH_GPIO74 2 9 CLKRQ_W LAN# 2 3 X1801 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
GPIO44 3 8 GPIO56 R1805 XTAL-25MHZ-155-GP Taipei Hsien 221, Taiwan, R.O.C.
CLKRQ_W W AN# 4 7 CLKREQ_MEDIA# 1MR2J-1-GP 82.30020.D41
GPIO73 Title
3D3V_S5 5 6 RN1805
GPIO18
2nd = 82.30020.G71
1 4 1 4 3rd = 82.30020.G61 PCH : PCI/USB/NVRAM/RSVD
2

SRN10KJ-L3-GP 2 3 GPIO20 C1802


XTAL25_OUT 1 2 SC18P50V2JN-1-GP Size Document Number Rev
SRN10KJ-5-GP A3 -1
2012 S-Series Richie 13.3
Date: W ednesday, March 14, 2012 Sheet 18 of 103
A B C D E
A B C D E

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)


(R1917 STUFFED,
PCH(3/9) R1901 UNSTUFFED

LOW Disabled
(R1901 STUFFED,
3 OF 10
R1917 UNSTUFFED
4 DMI_RXN[3:0] PCH1C
4 FDI_TX_N[7:0] 4 4
DMI_RXN0 BC24 BJ14 FDI_TX_N0
DMI_RXN1 DMI0RXN FDI_RXN0 FDI_TX_N1
BE20 DMI1RXN FDI_RXN1 AY14
DMI_RXN2 BG18 BE14 FDI_TX_N2
DMI_RXN3 DMI2RXN FDI_RXN2 FDI_TX_N3
4 DMI_RXP[3:0] BG20 DMI3RXN FDI_RXN3 BH13
BC12 FDI_TX_N4 RTC_AUX_S5
DMI_RXP0 FDI_RXN4 FDI_TX_N5
BE24 DMI0RXP FDI_RXN5 BJ12
DMI_RXP1 BC20 BG10 FDI_TX_N6
DMI_RXP2 DMI1RXP FDI_RXN6 FDI_TX_N7 R1917 1
BJ18 DMI2RXP FDI_RXN7 BG9 2 330KR2J-L1-GP
DMI_RXP3 BJ20 FDI_TX_P[7:0] 4
4 DMI_TXN[3:0] DMI3RXP FDI_TX_P0 DSW ODVREN R1901 1
FDI_RXP0 BG14 2 330KR2J-L1-GP
DMI_TXN0 AW24 BB14 FDI_TX_P1 DY
DMI_TXN1 DMI0TXN FDI_RXP1 FDI_TX_P2
AW20 DMI1TXN FDI_RXP2 BF14
DMI_TXN2 BB18 BG13 FDI_TX_P3
DMI_TXN3 DMI2TXN FDI_RXP3 FDI_TX_P4
4 DMI_TXP[3:0] AV18 DMI3TXN FDI_RXP4 BE12

DMI
FDI
BG12 FDI_TX_P5
DMI_TXP0 FDI_RXP5 FDI_TX_P6
AY24 DMI0TXP FDI_RXP6 BJ10
DMI_TXP1 AY20 BH9 FDI_TX_P7
DMI_TXP2 DMI1TXP FDI_RXP7
AY18 DMI2TXP
1D05V_S0 PUT CLOSE PCH DMI_TXP3 AU18 DMI3TXP
FDI_INT AW16 FDI_INT 4
R1902 1 2 49D9R2F-GP DMI_COMP_R BJ24 AV12 FDI_FSYNC0 4
DMI_ZCOMP FDI_FSYNC0
BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 4
1 2 RBIAS_CPY BH21 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 4
R1903 750R2F-GP
FDI_LSYNC1 BB10 FDI_LSYNC1 4
3 3

3D3V_S0
TPAD14-OP-GP
TP1903
T P1903 1 SUSACK#_R A18 DSW ODVREN 20120112 PV-R
DSWVRMEN
R1904 1 2 0R0402-PAD RSMRST#

System Power Management


C12 E22 PCH_DPW ROK R1905 1 DY 2 10KR2J-3-GP
SUSACK# DPWROK

R1906 2 1 0R0402-PAD PM_SYSRST#_R K3 B9


5 XDP_DBRESET# SYS_RESET# WAKE# PCIE_W AKE# 34,53

R1907 2 1 0R0402-PAD SYS_PW ROK_R P12 N3


42 VGATE SYS_PWROK CLKRUN#/GPIO32 PM_CLKRUN# 27

R1908 2 1 0R0402-PAD PM_PCH_PW ROK L22 G8 PCH_GPIO61 1 TP1901 TPAD14-OP-GP


27,97 PM_PW ROK PWROK SUS_STAT#/GPIO61 3D3V_S5
R1909 2 1 0R0402-PAD
RN1901
APW ROK L10 N14 ADP_PRES_OUT 1 8
APWROK SUSCLK/GPIO62 SUSCLK32_KBC 27 PW R_BTN_OUT# 2 7
PM_RI# 3 6
B13 D10 PM_SLP_S5# PCIE_W AKE# 4 5
5 PM_DRAM_PW RGD DRAMPWROK SLP_S5#/GPIO63
20120112 PV-R SRN10KJ-6-GP
C21 H4 SLP_S4#_R R1911 1 2 0R0402-PAD
27,41,97 RSMRST# RSMRST# SLP_S4# PM_SLP_S4# 46,62,97

K16 F4 SLP_S3#_R R1912 1 2 0R0402-PAD


27 SUS_PW R_ACK SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# R1910 1 PM_SLP_S3# 8,27,29,34,35,36,37,45,46,47,48,92,93 3D3V_S0
DY 2 0R2J-2-GP
2 2

E20 G10 PM_SLP_A#_R R1913 1 2 0R0402-PAD


27 PW R_BTN_OUT# PWRBTN# SLP_A# PM_SLP_A# 27 PM_CLKRUN# 1 2
R1915 8K2R2J-3-GP
H20 G16 SLP_SUS# 1 TP1905 TPAD14-OP-GP
27,85 ADP_PRES_OUT ACPRESENT/GPIO31 SLP_SUS#

PCH_GPIO72 E10 AP14


BATLOW#/GPIO72 PMSYNCH H_PM_SYNC 5 3D3V_S5

PM_RI# A10 K14 SLP_LAN# RN1902


RI# SLP_LAN#/GPIO29 PCH_GPIO72 1 4
SUS_PW R_ACK 2 3
PANTHER-GP-NF
SRN10KJ-5-GP

Intel ME-EC Interaction Signal List with and without M3 support


Platform With M3 Support AMT/ME COMPLIANCY TEST CONN.
Signal Name (e.g., Intel AMT) Platform Without M3 Support
APS1
9

SUSPWRDNACK(GPIO30) Required Required PM_SLP_S3# 1

PM_SLP_S4# 2
1 PM_SLP_S5# 3 <Core Design> 1
ACPRESENT(GPIO31) Required Required 3D3V_S5 PM_SLP_A# 4

ON_OFF#
5 DY
(Tie to SLP_S3#)
82,97 ON_OFF# 6
7 Wistron Corporation
SLP_LAN# 8 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SLP_A# Required Note: If SLP_S3# is not Taipei Hsien 221, Taiwan, R.O.C.
routed from PCH to EC, then 10
Title
SLP_A# becomes required ACES-CON8-13-GP-U1
from Intel ME-EC 20.F1295.008 PCH(3/9) : DMI/FDI/PM
Size Document Number Rev
prespecrive. A3
2012 S-Series Richie 13.3 -1
Date: W ednesday, March 14, 2012 Sheet 19 of 103
A B C D E
A B C D E

4
PCH(4/9) 4

3D3V_S0

PCH1D 4 OF 10
49,97 LCD_BL_EN J47 L_BKLTEN SDVO_TVCLKINN AP43

2
1
49,97 LCDVDD_EN M45 L_VDD_EN SDVO_TVCLKINP AP45

RN2002 P45 AM42


SRN2K2J-1-GP 49 BKLT_CTL L_BKLTCTL SDVO_STALLN
SDVO_STALLP AM40
49 LCD_SMBCLK T40 L_DDC_CLK
3 49 LCD_SMBDATA K47 AP39
4
L_DDC_DATA SDVO_INTN
SDVO_INTP AP40
L_CTRL_CLK T45
L_CTRL_DATA L_CTRL_CLK
P39 L_CTRL_DATA
1 2 LVD_IBG AF37 LVD_IBG SDVO_CTRLCLK P38
R2005 2K37R2F-GP AF36 M39
LVD_VBG SDVO_CTRLDATA
AE48 LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49
DDPB_AUXP AT47
DDPB_HPD AT40
49 TXCLKA_L- AK39 LVDSA_CLK#

LVDS
49 TXCLKA_L+ AK40 LVDSA_CLK DDPB_0N AV42
DDPB_0P AV40
3 AN48 AV45 3
49 TXOUTA_L0- LVDSA_DATA#0 DDPB_1N
49 TXOUTA_L1- AM47 LVDSA_DATA#1 DDPB_1P AV46

Digital Display Interface


49 TXOUTA_L2- AK47 LVDSA_DATA#2 DDPB_2N AU48
AJ48 LVDSA_DATA#3 DDPB_2P AU47
DDPB_3N AV47
49 TXOUTA_L0+ AN47 LVDSA_DATA0 DDPB_3P AV49
49 TXOUTA_L1+ AM49 LVDSA_DATA1
49 TXOUTA_L2+ AK49 LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
DDPC_CTRLDATA P42
3D3V_S0
AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
AH45 LVDSB_DATA#0 DDPC_HPD AT38
AH47 LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47

4
3
AF45 LVDSB_DATA#3 DDPC_0P AY49
AY43 RN2001
DDPC_1N
AH43 LVDSB_DATA0 DDPC_1P AY45 SRN2K2J-1-GP
AH49 LVDSB_DATA1 DDPC_2N BA47
AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 BB47

1
2
LVDSB_DATA3 DDPC_3N
DDPC_3P BB49

50 PCH_BLUE N48 CRT_BLUE DDPD_CTRLCLK M43 PCH_HDMI_CLK 51


50 PCH_GREEN P49 CRT_GREEN DDPD_CTRLDATA M36 PCH_HDMI_DATA 51
50 PCH_RED T49 CRT_RED
2 2

AT45 DPD_AUXN 1 TP2002TPAD14-OP-GP


DDPD_AUXN

CRT
50 CRT_DDC_CLK T39 AT43 DPD_AUXP 1 TP2001TPAD14-OP-GP
CRT_DDC_CLK DDPD_AUXP
50 CRT_DDC_DATA M40 CRT_DDC_DATA DDPD_HPD BH41 HDMI_PCH_DET 51,97

DDPD_0N BB43 HDMI_DATA2_R# 51


50 CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45 HDMI_DATA2_R 51
50 CRT_VSYNC M49 CRT_VSYNC DDPD_1N BF44 HDMI_DATA1_R# 51
DDPD_1P BE44 HDMI_DATA1_R 51
DDPD_2N BF42 HDMI_DATA0_R# 51
DAC_IREF T43 BE42 HDMI_DATA0_R 51
DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42 HDMI_CLK_R# 51
1

DDPD_3P BG42 HDMI_CLK_R 51


R2003
1KR2D-1-GP PANTHER-GP-NF
2

1 <Core Design> 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH(4/9) : LVDS/CRT/DDI
Size Document Number Rev
A3 -1
2012 S-Series Richie 13.3
Date: W ednesday, March 14, 2012 Sheet 20 of 103
A B C D E
A B C D E

GPIO Table
S 2012 Chief River PCH GPIO 52
Boot BIOS Strap
GNT1#/GPIO51 SATA1GP#/GPIO19 Boot BIOS Location PCH1E PCH(5/9) 5 OF 10
AY7
RSVD1
Richie U&D (13 inches) 1 0 0 LPC RSVD2 AV7
BG26 TP1 RSVD3 AU3
Rocky U&D (14 inches) 1 0 1 Reserved BJ26 TP2 RSVD4 BG4
BH25 TP3
Rocky U&D (15/17 inches) 0 1 0 PCI BJ16 TP4 RSVD5 AT10
BG16 TP5 RSVD6 BC8
1 1 SPI(Default) AH38 TP6
AH37 TP7 RSVD7 AU2
4 AK43 TP8 RSVD8 AT4 4
AK45 TP9 RSVD9 AT3
C18 TP10 RSVD10 AT1
N30 TP11 RSVD11 AY3
H3 TP12 RSVD12 AT5
AH12 TP13 RSVD13 AV3
AM4 TP14 RSVD14 AV1
3D3V_S0 AM5 BB1
TP15 RSVD15
Y13 BA3

R2113 1 2 PCH_GPIO51
USB3.0 Table K24
L24
TP16
TP17
TP18
RSVD16
RSVD17
RSVD18
BB5
BB3
10KR2J-3-GP AB46 BB7
USB AB45
TP19
TP20
RSVD19
RSVD20 BE8

RSVD
R2109 1 2 PCH_GPIO51
Pair Device RSVD21 BD4
BF6
10KR2J-3-GP RSVD22
1 FREE B21 AV5
DY TP21 RSVD23
2 I/O CONN. 1 M20
AY16
TP22 RSVD24 AV10
TP23
3 I/O CONN. 2 BG46 TP24 RSVD25 AT8

3D3V_S0 4 I/O CONN. 3 RSVD26 AY5


BA2
RSVD27
BE28 USB3RN1
DY
PE_GPIO0
62 USB3_RXN2 BC30 USB3RN2 RSVD28 AT12
1 2 62 USB3_RXN3 BE32 USB3RN3 RSVD29 BF3
10KR2J-3-GP BJ32
R2112
62 USB3_RXN4

62 USB3_RXP2
BC28
BE30
USB3RN4
USB3RP1
USB3RP2
USB2.0 Table
3 BF32 3
62 USB3_RXP3 USB3RP3
BG32 C24
62 USB3_RXP4
AV26
USB3RP4
USB3TN1
USBP0N
USBP0P A24 USB
62 USB3_TXN2 BB26 USB3TN2 USBP1N C25 USB_PN1 62 Pair Device
62 USB3_TXN3 AU28 USB3TN3 USBP1P B25 USB_PP1 62 USB 3.0 Conn. 1
3D3V_S0 62 USB3_TXN4 AY30 USB3TN4 USBP2N C26 USB_PN2 62 0 FREE
AU26 USB3TP1 USBP2P A26 USB_PP2 62 USB 3.0 Conn. 2
R2110 62 USB3_TXP2 AY26 USB3TP2 USBP3N K28 USB_PN3 62 1 USB 3.0 I/O CONN. 1
DY
CAMERA_ON
62 USB3_TXP3 AV28 USB3TP3 USBP3P H28 USB_PP3 62 USB 3.0 Conn. 3
1 2 62 USB3_TXP4 AW30 USB3TP4 USBP4N E28 2 USB 3.0 I/O CONN. 2
10KR2J-3-GP D28
USBP4P
RN2101
USBP5N C28 USB_PN5 53 3 USB 3.0 I/O CONN. 3
1 4 ACCEL_INT USBP5P A28 USB_PP5 53 BT WLAN combo
2 3 NMI_SMI_DBG# USBP6N C29 4 FREE
USBP6P B29
INT_PIRQA#
SRN8K2J-3-GP
INT_PIRQB#
K40
K38
PIRQA# USBP7N N28
M28
5 BT WLAN combo
PIRQB# USBP7P

PCI
INT_PIRQC#
RN2102 INT_PIRQD#
H38
G38
PIRQC# USBP8N L30
K30
USB_PN8 64
Fingerprint 6 FREE
3D3V_S0 PIRQD# USBP8P USB_PP8 64
INT_PIRQA# 20120112 PV-R
INT_PIRQD#
1
2
10
9 PE_GPIO1 PCH_GPIO50 C46
USBP9N G30
E30
USB_PN9 61
USB 2.0 Conn. 1 7 FREE
REQ1#/GPIO50 USBP9P USB_PP9 61

USB
INT_PIRQB# PCH_GPIO2 R2106 1 2 0R0402-PAD PLT_DET_R
3 8 27,69 PLT_DET C44 REQ2#/GPIO52 USBP10N C30 USB_PN10 49 8 Fingerprint
INT_PIRQC# 4 7 PLT_DET_R
PCH_GPIO50
92,93 PE_GPIO1
PE_GPIO1 E40 REQ3#/GPIO54 USBP10P A30 USB_PP10 49 Camera
3D3V_S0 5 6 USBP11N L32 9 USB 2.0 I/O CONN. 1
PCH_GPIO51 D47 K32
GNT1#/GPIO51 USBP11P
SRN8K2J-2-GP-U 49 CAMERA_ON E42 GNT2#/GPIO53 USBP12N G32 USB_PN12 54 10 Camera
83 PE_GPIO0 F46 GNT3#/GPIO55 USBP12P E32 USB_PP12 54 WWAN
USBP13N C32
A32
11 FREE
2 PCH_GPIO2 USBP13P 2
G42
G40
PIRQE#/GPIO2 12 WWAN
56,96 SATA_ODD_DA# PIRQF#/GPIO3 USB_BIAS R2101 1 2 22D6R2F-L1-GP
3D3V_S5 27,71 NMI_SMI_DBG#
C42
D44
PIRQG#/GPIO4 USBRBIAS# C33 13 FREE
65 ACCEL_INT PIRQH#/GPIO5

USBRBIAS B33
R2102 1 DY 2 PME# K10
10KR2J-3-GP PME#
PCI_PLTRST# C6 A14 OC0#_GPIO59
PLTRST# OC0#/GPIO59 OC1#_GPIO40
OC1#/GPIO40 K20
B17 OC2#_GPIO41
R2103 1 OC2#/GPIO41
27,97 CLK_PCI_KBC 2 22R2J-2-GP CLK_PCI_SIO_R H49 CLKOUT_PCI0 OC3#/GPIO42 C16 OC3#_GPIO42
R2105 1 2 22R2J-2-GP CLK_PCI_FB_R H43 L16 OC4#_GPIO43
18 CLK_PCI_FB TPAD14-OP-GP TP2108 CLK_OUT_PCI2 CLKOUT_PCI1 OC4#/GPIO43 OC5#_GPIO9
1 J48 CLKOUT_PCI2 OC5#/GPIO9 A16
TPAD14-OP-GP TP2106 1 CLK_OUT_PCI3 K42 D14
R2107 1 CLKOUT_PCI3 OC6#/GPIO10 LANLINK_STATUS 35
71,97 CLK_PCI_DEBUG 2 22R2J-2-GP CLK_PCI_KBC_R H40 CLKOUT_PCI4 OC7#/GPIO14 C14 OC7#_GPIO14

PANTHER-GP-NF
3D3V_S5

3D3V_S5

U2101 AND GATE RN2104


1 5 OC4#_GPIO43 8 1
A VCC OC1#_GPIO40
1 7 2 <Core Design> 1
PCI_PLTRST# 2 OC2#_GPIO41 6 3
B OC3#_GPIO42 5 4
PLT_RST#
3 GND Y 4 PLT_RST# 5,17,32,34,53,54,56,71,83,96,97
SRN10KJ-6-GP Wistron Corporation
1

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


U74LVC1G08G-AL5-R-GP-U R2108 RN2103 Taipei Hsien 221, Taiwan, R.O.C.
100KR2J-1-GP OC5#_GPIO9
73.01G08.EHG LANLINK_STATUS
8 1
Title
2nd = 73.7SZ08.EAH OC7#_GPIO14
7 2
3rd = 73.01G08.L04 6 3
PCH(5/9) : PCI/USB/NVM
2

R2104 DY OC0#_GPIO59 5 4
0R2J-2-GP 1 2DY Size Document Number Rev
SRN10KJ-6-GP A3 -1
2012 S-Series Richie 13.3
Date: W ednesday, March 14, 2012 Sheet 21 of 103
A B C D E
A B C D E

PE_PW RGD 1
RP2201
10
3D3V_S0

PCH(6/9) D3E_W AKE#


GPS_XMIT_OFF#
8
7
RN2205
1
2
3D3V_S0

OCP_OC# 2 9 GATEA20 6 3
LPC_RESET# 3 8 GPIO34 KBRST# 5 4
SATA_ODD_PW R_EN 4 7 W W AN_TRANSMIT_OFF# PCH1F 6 OF 10
3D3V_S0 5 6 RUNSCI_EC# SRN10KJ-6-GP
CRD_REQ#_R_R T7 C40
SRN10KJ-L3-GP 32 CRD_REQ#_R_R BMBUSY#/GPIO0 TACH4/GPIO68 SATA_ODD_PW R_EN 56,97

38 OCP_OC# A42 TACH1/GPIO1 TACH5/GPIO69 B41 D3E_W AKE# 32,97


3D3V_S5
4
R2204 1
DY 27 RUNSCI_EC# H36 TACH2/GPIO6 TACH6/GPIO70 C41 LPC_RESET# 27 4
2 10KR2J-3-GP PCH_GPIO24
28 THERM_SCI# E38 TACH3/GPIO7 TACH7/GPIO71 A40 GPS_XMIT_OFF# 54,97
R2205 1 2 10KR2J-3-GP GPI_INV_LIDW AKE GPI_INV_LIDW AKE C10 GPIO8
PCH_GPIO12 C4
R2207 LAN_PHY_PWR_CTRL/GPIO12 1D05V_S0
1 2 10KR2J-3-GP W LAN_TRANSMIT_OFF#
R2214 1 2 1KR2J-1-GP TLS_ENcrytion G2 P4
3D3V_S5 GPIO15 A20GATE GATEA20 27
AU16 H_PECI_R 1 DY 0R2J-2-GP
2
PECI H_PECI 5,27

1
SATA4GP_GPIO16 U2 R2209
SATA4GP/GPIO16 R2222
3D3V_S0 PCH_GPIO27 RCIN# P5 KBRST# 27,97 DY 56R2J-4-GP
1 2

GPIO
R2211 10KR2J-3-GP PE_PW RGD D40 AY11
18,86,92,93,96,97 PE_PW RGD TACH0/GPIO17 PROCPWRGD H_CPUPW RGD 5
FPR_LOCK#

CPU/MISC
1 2

2
R2212 DY 10KR2J-3-GP T5 AY10 PCH_THRMTRIP#_R R2210 1 2 390R2F-2GP
54,68 W W AN_TRANSMIT_OFF# SCLOCK/GPIO22 THRMTRIP# H_THRMTRIP# 5,85
PCH_GPIO24 E8 T14 INIT3_3V# 1 TP2203TPAD14-OP-GP
GPIO24 INIT3_3V#
PCH_GPIO27 E16 AY1 DF_TVS
GPIO27 DF_TVS
TPAD14-OP-GP
TP2206
T P2206 1 PCH_GPIO28 P8 PROC_SELECT
GPIO28
TS_VSS1 AH8
GPIO34 K1 1D8V_S0
STP_PCI#/GPIO34
TS_VSS2 AK11
BT_OFF# K4
53,97 BT_OFF# GPIO35

1
AH10
3
VRAM ID TABLE SATA2GP_GPIO36 V8 SATA2GP/GPIO36
TS_VSS3

TS_VSS4 AK10
R2201
2K2R2J-2-GP 3
SATA3GP_GPIO37 M5 SATA3GP/GPIO37

2
3D3V_S0 3D3V_S0 PCH_GPIO38 N2 P37
SLOAD/GPIO38 NC_1
1 2 H_SNB_IVB# 5
PCH_GPIO39 M3 R2202 1KR2J-1-GP
SDATAOUT0/GPIO39
2

PCH_GPIO39 PCH_GPIO38 V13 BG2 NCTF_VSS#BG2 TP22071 TPAD14-OP-GP


R2225 R2220 VENDER 64,97 FPR_LOCK# SDATAOUT1/GPIO48 VSS_NCTF_15#BG2
DMI & FDI Termination Voltage
10KR2J-3-GP 10KR2J-3-GP SATA5GP_GPIO49 V3 BG48 NCTF_VSS#BG48 TP22081 TPAD14-OP-GP
SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16#BG48
Hynix_Elpida Samsung_Elipda
D6 BH3 NCTF_VSS#BH3 TP22091 TPAD14-OP-GP SNB: "1"
0 1 Samsung
1

53 W LAN_TRANSMIT_OFF# GPIO57 VSS_NCTF_17#BH3


DF_TVS IVB: "0"
PCH_GPIO39 PCH_GPIO38 BH47 NCTF_VSS#BH47 TP22101 TPAD14-OP-GP
VSS_NCTF_18#BH47
1 0 Hynix TPAD14-OP-GP
TP2214
T P2214 1 NCTF_VSS#A4 A4 VSS_NCTF_1#A4 VSS_NCTF_19#BJ4 BJ4
2

NCTF
R2223 R2224 A44 BJ44
VSS_NCTF_2#A44 VSS_NCTF_20#BJ44
10KR2J-3-GP 10KR2J-3-GP
UMA_Samsung UMA_Hynix 1 1 Elpida A45 VSS_NCTF_3#A45 VSS_NCTF_21#BJ45 BJ45
1

A46 BJ46
0 0 UMA VSS_NCTF_4#A46 VSS_NCTF_22#BJ46
A5 VSS_NCTF_5#A5 VSS_NCTF_23#BJ5 BJ5

A6 VSS_NCTF_6#A6 VSS_NCTF_24#BJ6 BJ6

A4,A44,A45,A46,A5,A6,B3,B47,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
2
GDDR5/DDR3 TABLE TPAD14-OP-GP
TP2216
T P2216 1 NCTF_VSS#B3 B3 VSS_NCTF_7#B3 VSS_NCTF_25#C2 C2 NCTF_VSS#C2 1 TP2212TPAD14-OP-GP
2
TPAD14-OP-GP
TP2215
T P2215 1 NCTF_VSS#B47 B47 C48 NCTF_VSS#C48 1 TP2211TPAD14-OP-GP
3D3V_S5 VSS_NCTF_8#B47 VSS_NCTF_26#C48
20110822SI

D49,E1,E49,F1,F49
BD1 VSS_NCTF_9#BD1 VSS_NCTF_27#D1 D1
2012 Chief River PCH GPIO 12

NCTF TEST PIN:


1

BD49 D49 NCTF_VSS#D49 1 TP2213TPAD14-OP-GP


R2206 DY VSS_NCTF_10#BD49 VSS_NCTF_28#D49
Richie U&D (13 inches) 0 (13") GDDR5
10KR2J-3-GP BE1 VSS_NCTF_11#BE1 VSS_NCTF_29#E1 E1
Rocky U&D (14 inches) 1(14",15",17")DDR3
BE49 E49
2

PCH_GPIO12 VSS_NCTF_12#BE49 VSS_NCTF_30#E49


Rocky U&D (15/17 inches) 1(14",15",17")DDR3 TPAD14-OP-GP
TP2218
T P2218 1 NCTF_VSS#BF1 BF1 F1
VSS_NCTF_13#BF1 VSS_NCTF_31#F1
2

R2218 TPAD14-OP-GP
TP2217
T P2217 1 NCTF_VSS#BF49 BF49 F49
VSS_NCTF_14#BF49 VSS_NCTF_32#F49
10KR2J-3-GP

PANTHER-GP-NF
1

3D3V_S0
3D3V_S0

3D3V_S0 3D3V_S0
1 DY 2 BT_OFF# RN2202
R2216 10KR2J-3-GP 1 4 SATA0GP_GPIO21 17
1 2 SATA3GP_GPIO37 1 2 SATA2GP_GPIO36 RN2203 2 3 SATA4GP_GPIO16
SATA4GP_GPIO16 96
R2217 DY 200KR2J-L1-GP R2213 DY 200KR2J-L1-GP 1 4 SATA5GP_GPIO49
1 2 3 CRD_REQ#_R_R SRN10KJ-5-GP <Core Design> 1

SRN10KJ-5-GP

Wistron Corporation
FDI TERMINATION VOLTAGE OVERRIDE DMI TERMINATION VOLTAGE OVERRIDE 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
GPIO37 LOW - Tx, Rx terminated to same voltage GPIO36 LOW - Tx, Rx terminated to same voltage
(FDI_OVRVLTG) (DC Coupling Model DEFAULT) (DC Coupling Model DEFAULT)
PCH(6/9) : GPIO/NTCF/RSVD
Size Document Number Rev
A3 -1
2012 S-Series Richie 13.3
Date: W ednesday, March 14, 2012 Sheet 22 of 103
A B C D E
5 4 3 2 1

VCC_PCH: 6A
PCH(7/9) 3D3V_S0_LDO

U2301
5V_S0

1mA
5 1
D
PCH1G POWER 7 OF 10 OUT IN
GND 2
D

1
1D05V_S0

SCD01U16V2KX-3GP

SCD1U10V2KX-4GP
4 3 C2308
1.3A NC#4 EN

SC1U10V2KX-1GP
AA23 U48 C2322 C2323 C2325

2
VCCCORE1 VCCADAC SC2D2U6D3V3KX-GP TLV70233DBVR-GP
DY AC23

2
VCCCORE2

SC10U6D3V3MX-GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP
AD21 74.70233.03F

CRT
VCCCORE3

1
C2313 C2314 C2315 C2316 AD23 U47 2nd = 74.08818.B3F
VCCCORE4 VSSADAC
AF21 3rd = 74.09090.D3F

VCC CORE
VCCCORE5
AF23

2
VCCCORE6 3D3V_S0
AG21 VCCCORE7
AG23 VCCCORE8 1mA
AG24 VCCCORE9 VCCALVDS AK36
AG26 VCCCORE10
AG27 VCCCORE11 VSSALVDS AK37
AG29 VCCCORE12
AJ23 VCCCORE13 1D8V_S0

LVDS
AJ26 VCCCORE14 VCCTX_LVDS1 AM37
AJ27 VCCCORE15 60mA
AJ29 VCCCORE16 VCCTX_LVDS2 AM38
1D05V_S0 AJ31 VCCCORE17

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP
AP36 C2309
2.925A VCCTX_LVDS3

SC22U6D3V5MX-2GP
AP37 C2306 C2307
VCCTX_LVDS4
L2301 AN19

2
1D05V_S0 VCCIO28
DY
1 2 +V1.05S_VCCAPLL_EXP BJ22
IND-1UH-100-GP VCCAPLLEXP 266mA 3D3V_S0
C V33 C
VCC3_3_6

SCD1U10V2KX-4GP
HVCMOS
AN16 VCCIO15

1
SC10U6D3V3MX-GP
1
C2317 AN17 C2318
VCCIO16
DY V34

2
VCC3_3_7
2 AN21 VCCIO17
AN26 VCCIO18
1D05V_S0 AN27 AT16 +VCCAFDI_VRM
160mA
VCCIO19 VCCVRM3
AP21 +V1.05S_VCC_DMI 1D05V_S0
VCCIO20 R2301
AP23 AT20 2 1
42mA
VCCIO21 VCCDMI1
1

0R0402-PAD

1
DMI
C2310 C2311 C2321 C2320 C2301 AP24 C2319
VCCIO22

VCCIO
SC1U10V2KX-1GP
2

2
SC10U6D3V3MX-GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

AP26 AB36 VCCCLKDMI

2
VCCIO23 VCCCLKDMI 1D05V_S0

1
AT24 C2302 R2306
VCCIO24
1 2
20mA
SC1U10V2KX-1GP

2
AN33 0R0402-PAD
VCCIO25
20120112 PV-R
AN34 VCCIO26 VCCDFTERM1 AG16
3D3V_S0

SCD1U10V2KX-4GP
1
BH29 AG17 1D8V_S0
B VCC3_3_3 VCCDFTERM2 C2303 B

DFT / SPI
190mA
1

C2304

2
SCD1U10V2KX-4GP AJ16
1D05V_S0 VCCDFTERM3
2

+VCCAFDI_VRM AP16 VCCVRM2


VCCDFTERM4 AJ17

1 DY 20R3J-0-U-GP +V1.05S_VCCAPLL_FDI BG6


R2302 VCCAFDIPLL
R2303 3D3V_S5
2 1 +V1.05S_VCCDPLL_FDI AP17
0R0402-PAD VCCIO27
V1
20mA
FDI

+V1.05S_VCC_DMI VCCSPI

1
SC1U10V2KX-1GP
AU20 C2305
VCCDMI2

2
PANTHER-GP-NF

20120116PV-R +VCCAFDI_VRM

1D5V_S0 R2304 1 2 0R0603-PAD-1-GP

A <Core Design> A
1D8V_S0 1
R2305
DY 2
0R3J-0-U-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH(7/9) : PWR1
Size Document Number Rev
A3 -1
2012 S-Series Richie 13.3
Date: W ednesday, March 14, 2012 Sheet 23 of 103
5 4 3 2 1
A B C D E

1D05V_S0
PCH(8/9)
1
R2405
DY 2
0R3J-0-U-GP
2.925A
3D3V_S5
PCH1J POWER 10 OF 10 1D05V_S0
2mA +VCCACLK AD49 N26
VCCACLK VCCIO29
1 2

1
R2401 P26 C2402
0R0603-PAD-1-GP +VCCPDSW VCCIO30
T16 VCCDSW3_3 SC1U10V2KX-1GP
3D3V_S0 20120116PV-R P28
L2401

2
VCCIO31

1
4 C2403 4
1 2 +V3.3S_VCC_CLKF33 SCD1U10V2KX-4GP PCH_VCCDSW V12 T27
C2401 DCPSUSBYP VCCIO32

1
IND-10UH-238-GP SCD1U10V2KX-4GP T29
1D05V_S0 VCCIO33 3D3V_S5

SC10U6D3V3MX-GP

SC1U10V2KX-1GP