This article has been accepted for inclusion in a future issue of this journal.
Content is final as presented, with the exception of pagination.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Understanding the Potential and the Limits of
Germanium pMOSFETs for VLSI Circuits From
Experimental Measurements
P. Magnone, F. Crupi, M. Alioto, Senior Member, IEEE, B. Kaczer, and B. De Jaeger
Abstract—In this paper, potential and limits of Germanium
pMOSFETs for VLSI applications are investigated from a circuit
perspective for the first time in the literature. Since short-channel
Germanium devices have been developed only recently, no circuit
design tools are currently available, hence most of the results
available in the literature address process and device-level issues
(currently, down to the 65 nm node). However, the suitability of
Germanium MOSFETs for VLSI circuits should be assessed at
circuit level. To fill this gap, we introduce an innovative method-
ology that extracts the main circuit parameters of interest (e.g.,
speed, dynamic power, leakage) from measurements on exper-
imental devices. Appropriate figures of merit are adopted to
highlight the potential of Germanium MOSFETs under realistic
VLSI designs that fully exploit system-level schemes to minimize
leakage (e.g., body biasing, stack forcing, power gating). Mea-
surements and evaluations are performed on 125 nm Germanium
pMOSFETs with a high- /metal gate stack having an equivalent
oxide thickness of 1.3 nm. Comparison with Si pMOSFET pro-
totypes implemented with similar gate stack is also carried out
to comparatively understand the potential and the weaknesses
of Germanium transistors. The main experimental results are
justified through theoretical analysis as a function of the relevant
circuit and device parameters. Some system-level aspects are also
investigated, such as the energy efficiency and the wakeup time
of body-biasing schemes in Ge circuits and the impact of voltage
scaling.
Index Terms—Digital circuits, emerging technologies, germa-
nium, leakage-delay tradeoff, VLSI.
I. INTRODUCTION
ANO-SCALE Silicon-bulk CMOS technology is
N showing its limits more evidently at each new process
generation [1]. Due to the severe degradation of electrical prop-
erties of down-scaled Si-bulk CMOS transistors, the advantages
gained with each new process generation are continuously re-
ducing, thereby making design increasingly more critical.
In this scenario, a wide interest has grown in alternative de-
vices that scale better and are compatible with CMOS manu-
Manuscript received October 21, 2009; revised February 17, 2010, April 21,
2010; accepted May 23, 2010.
P. Magnone and F. Crupi are with the Dipartimento di Elettronica, Infor-
matica e Sistemistica (DEIS), Università della Calabria, 87036 Rende, Italy.
M. Alioto is with the Dipartimento di Ingegneria dell’Informazione (DII),
Università di Siena, 53100 Siena, Italy, and also with the Berkeley Wireless
Research Center—Electrical Engineering and Computer Science Department,
University of California, Berkeley, CA 94704-1302, USA (e-mail: malioto@dii.
unisi.it; alioto@eecs.berkeley.edu).
B. Kaczer and B. De Jaeger are with the Interuniversity Microelectronics
Center, 3001 Leuven, Belgium.
Digital Object Identifier 10.1109/TVLSI.2010.2053226
1063-8210/$26.00 © 2010 IEEE
1
facturing process [2]–[4]. Among these emerging technologies,
Germanium MOSFETs have been recently considered as an al-
ternative technology to improve the carrier mobility, and hence
to sustain the performance growth that is indicated by the ITRS
roadmap (to be added to strain as a further technology booster)
[1], [5]–[26]. Since the 90-nm technology node, Ge has been
introduced in commercial CMOS devices as a source to gen-
erate strain into the silicon channel rather than as a substitute
of the channel in itself. A 30% drive current increase in pMOS-
FETs devices has been obtained thanks to the uniaxial compres-
sive channel strain induced by the selective epitaxial growth of
Si Ge in recessed source/drain (S/D) regions. However Ger-
manium is not yet used to the best of its potential, as it can poten-
tially bring a bulk electron (hole) mobility that is approximately
twice (four times) higher than Si, (although the actual improve-
ment in real devices is limited by several scattering mecha-
nisms). This high mobility improvement allowed by Ge tech-
nology clearly makes the leakage-delay tradeoff more favorable
than Si devices, hence Ge devices can potentially be an excellent
replacement of Si devices from 22-nm technology node on. Re-
cently, various research groups have successfully demonstrated
high performance Ge pMOSFETs devices with channel length
down to 60 nm in a Si-compatible process flow [5]–[22]. Some
promising results have been reported also for Ge nMOSFETs
[23]–[26], but since the process is not mature yet, in this paper,
we will focus on Ge pMOSFETs only1.
As discussed above, the results on Ge transistors available
in the literature focus on the device, hence they do not pro-
vide enough information on the suitability for VLSI implemen-
tations. On the other hand, Ge technology needs to be assessed
by explicitly considering the issues and constraints that arise at
the circuit (and system) level of abstraction, such as the speed
potential, the leakage-delay tradeoff, the impact of static and dy-
namic voltage scaling. However, since Ge technology is still im-
mature, there are no adequate circuit design tools to support the
implementation of VLSI circuit prototypes (e.g., no design kit
is available). For this reason, in this paper we propose a novel
methodology that aims at filling the gap between device mea-
surements and circuit-level analysis. More specifically, appro-
priate figures of merit are introduced to express VLSI circuit-
and system-level features as a function of proper parameters,
1This does not limit the validity of the results on the potential of Ge tech-
nology, as long as the improvement over Si devices is approximately the same
for both pMOSFET and nMOSFET. Observe that this assumption is certainly
realistic for Ge devices, as the mobility enhancement of nMOSFETs over Si
2
counterparts is in the order of 1.5 [25], [26], which is consistent with the 2
improvement observed in our Ge pMOSFETs (as shown later).
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
which in turn are evaluated from experimental measurements.
This permits to perform an early assessment of the technology
that provides useful information well before having a complete
design kit. This measurement-based methodology permits to
gain a higher level of confidence in the results with respect to
the usual approach based on 2-D/3-D device simulations. Obvi-
ously, this approach is general, and can be applied to investigate
on various aspects of VLSI implementations in other emerging
technologies.
In this paper, for the first time in the literature, Ge transis-
tors are evaluated in terms of their suitability for VLSI imple-
mentation by explicitly dealing with circuit- and system-level
issues. In particular, the leakage-delay tradeoff is explored in
the context of realistic VLSI designs that fully exploit static/dy-
namic body biasing, stack forcing and power gating [28]–[32].
Other important VLSI issues are also investigated, such as the
energy efficiency and the wakeup time of body-biasing schemes
in Ge circuits, as well as the impact of voltage scaling. Within
the methodology framework above described, Ge transistors are
then compared with the traditional Si counterparts at the same
technology node. Theoretical justification is provided for the
most interesting experimental results.
The paper is structured as follows. Ge pMOSFETs are re-
viewed in Section II, where details on the fabrication of the
considered devices are provided. The proposed methodology
and figures of merit to evaluate the suitability of Ge transistors
for VLSI circuits are discussed in Section III. Sections IV and
V analyze the effectiveness of low-leakage techniques that are
widely employed in current VLSI circuits, i.e., body biasing and
stack forcing. The analysis of the speed potential of Ge transis-
tors is dealt with in Section VI, whereas the issues related to
the leakage-performance tradeoff and voltage scaling are then
discussed in Section VII. In all these sections, results obtained
with Ge transistors are compared with Si counterparts. Finally,
conclusions are drawn in Section VIII.
II. REVIEW OF GE TRANSISTORS AND FABRICATED DEVICES
Devices were fabricated at IMEC using 200 mm Ge-on-Si
wafers. A relaxed 1.6–2 m Ge layer was deposited epitaxi-
ally on top of the Si. First, an n-well was formed with P im-
plants of cm dose at 570 keV followed by
cm at 180 keV. The threshold voltage adjust implant was
cm at 90 keV with P. Isolation was achieved using
a deposited and patterned SiO layer. The Ge surface was passi-
vated with 6 monolayers of epi Si grown at 500 C using SiH as
a precursor, followed promptly by oxidation in slightly ozonated
water to get approximately 0.5 nm SiO . Immediately after, 4
nm HfO was deposited by atomic layer deposition (ALD). The
equivalent oxide thickness (EOT) of the gate stack was 1.3 nm
and the channel length was 125 nm. The gate metal consisted of
TiN/TaN. A P dose of at 60 keV was used for halo to
control the short channel performance. A detailed process flow
can be found elsewhere [6]. For comparison purposes, we char-
acterized a second set of devices on a Si substrate with the same
gate length and with similar gate stack consisting of 0.8 nm of
SiO , 2 nm of ALD HfO , and TiN metal gate. The EOT of the
gate stack was 1.2 nm, which is somewhat representative of the
65-nm technology node. The device measurements were done
TABLE I
DEVICE PARAMETERS OF GE AND SI PMOSFETS (FROM MEASUREMENTS)
Fig. 1. Cross section of a Ge-pMOSFET transistor.
at wafer-level using a Keithley 4200 semiconductor character-
ization system and an Agilent E4980A precision LCR meter.
The numerical value of the main device parameters is reported
in Table I.
For the typical investigated EOTs (1.2–1.3 nm), the ITRS
roadmap [1] indicates that the supply voltages are in the range
0.8–1.2 V based on the technology requirements (high-
performance or low-power). In this work, we choose as an in-
termediate value 1 V.
The basic structure of a Ge pMOSFET is shown in Fig. 1,
whose main difference with respect to the Si-bulk pMOSFETs
is the Germanium bulk. According to Table I, the latter permits
to improve the low-field peak mobility by a factor 2 compared to
the Si pMOSFET, where charge carrier mobility has been eval-
uated by using the split CV technique [10], [33]. This mobility
enhancement is lower than the factor 4 expected for bulk con-
duction, since in a MOSFET device the mobility is limited by
the surface conduction. The improved mobility permits to obtain
a higher on-current, as it is confirmed by the measured I-V char-
acteristics of a short-channel device (with 125 nm) in Fig. 2
(see solid line). From this figure, the on-current achieved for
1 V and 0.67 V
for the Si (Ge) device is 209 A/ m (310 A/ m), hence the
Ge device exhibits an improvement by a factor of 1.5. This im-
provement is lower than the factor of two expected from the
low-field mobility, since the short-channel device operates at
high longitudinal electric field, close to the saturation velocity.
This is confirmed by measurements, which reveal that the mea-
sured on-current in linear region (i.e., at low ) of Ge tran-
sistors is twice that of Si devices.
In Fig. 2 are reported the drain and source currents as a func-
tion of gate voltage measured in Si (a) and Ge (b) pMOSFETs.
By applying the maximum transconductance method [33] the
threshold voltage can be calculated in linear region from Fig. 2.
As reported in Table I, we found out that the Ge and Si de-
vices have different threshold voltages, 0.12 and 0.34 V, re-
spectively. In order to have a fair comparison, we shifted the
I-V curves in such a way to equalize the threshold voltages
0.33 V for both Ge and Si devices. The
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MAGNONE et al.: UNDERSTANDING THE POTENTIAL AND THE LIMITS OF GERMANIUM PMOSFETS FOR VLSI CIRCUITS
Fig. 2. Measured drain and source current versus V in Si (a) and Ge (b)
pMOSFETs. Since the source-to-bulk voltage is null, the source current (solid
line) does not include the junction leakage which instead corrupts the drain cur-
rent (dashed line).
choice of follows the historical trend for op-
timized MOSFET devices. It is worth noting that tuning and
equalizing the threshold voltage might be difficult in principle
when adjusting only the doping density, due to its limited range
of practical values.2 However, the threshold can be tuned also
by adjusting other knobs. For example, in any high-k/metal gate
stack (which is the case of Ge pMOSFETs under investigation),
it is possible to modulate the work function of the device by se-
lecting a proper metal or by inserting a cap layer between the
high-k dielectric and the metal gate [34].
In principle, the leakage current of the Ge and Si devices can
be evaluated from the value at 0 V (when the threshold
voltages are matched to 0.33 V). However,
some further considerations are required to achieve a fair com-
parison between the two devices, as discussed in the following.
As usual, the leakage current includes three components: the
subthreshold contribution, the gate current and the (drain-bulk)
junction current. The first is the usual contribution that arises in
the channel, and dominates over the other two in Si transistors
[35], [36]. The second is negligible thanks to the adoption of
high- gate dielectric. The third one is usually negligible in Si
devices, but in current Ge transistors it tends to be very large be-
cause of the lower bandgap and the higher defect density in the
space charge layer of the junction, as the Germanium process is
2Indeed, Ge has a lower bandgap than Si, hence a larger channel doping
would be required to obtain the same threshold voltage. However, doping den-
sity is partially constrained, since large shifts would lead to an excessive devia-
tion or degradation of other important device parameters (e.g., carrier mobility,
threshold voltage mismatch, subthreshold slope, junction leakage).
3
TABLE II
NUMERICAL VALUE OF BASIC PARAMETERS AND FIGURES OF MERIT
far less mature than the Si-bulk process [13]–[15]. This is clearly
shown in Fig. 2(b), where the I-V characteristics is plotted both
by accounting the third contribution (dashed line) or not (solid
line). This figure shows that for the junction current
dominates over the other two leakage components, and its value
for the Ge device is greater than the Si transistor by a factor of
about 5000. Since major Ge process improvements are expected
in the near future, the trap-assisted tunneling component of the
junction current is expected to significantly decrease. Moreover,
it was recently shown that it is possible to confine the high-mo-
bility material (SiGe) only in the channel region, thus strongly
suppressing the junction leakage [37]. For this reason, papers
on Ge transistors usually assume that it is already negligible,
in order to perform a fair comparison with other technologies
having much more mature process [6]. Accordingly, in the fol-
lowing the Ge junction current will be always subtracted from
the drain leakage.
Observe that, even neglecting the junction leakage, the
leakage current of a Ge device is significantly greater than
that of a Si transistor. More specifically, as reported in Table II,
for the Ge transistor is greater than that of the Si counterpart
of about two orders of magnitude. Although this seems to be
a major limit of Ge technology, many other issues must be
considered to perform a fair comparison with Si technology, as
will be discussed in Section III.
Another parameter that is often used to define the device be-
havior in the off state is the subthreshold swing , which is de-
fined as the reciprocal of the slope of the I-V characteristics in
subthreshold (see Fig. 2). The dependence of on is very
weak and, in particular, its value at 1 V is equal to 71
mV/dec (113 mV/dec) for the Si (Ge) device. In other words,
the Ge transistor has a much worse subthreshold swing in that
it requires a larger reduction to reduce its current by one
decade. This is mainly due to the much larger interface state
density, as Ge processes are still immature [16]–[19]. Hence,
near-future improvements in the Ge process are expected to
bring closer to its ideal value of 60 mV/dec, which is the same
as that of Si devices. In addition, in the next section it will be
shown that is not the only representative parameter of the be-
havior of VLSI digital circuits in the off state, hence a worse
does not necessarily lead to a worse leakage.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

where it was observed that is by definition

the subthreshold slope , and the coefficient is
the well-known coefficient that measures the sensitivity of the
threshold voltage on [4]. From its definition, low values
of indicate that a given technology can potentially exhibit
a low leakage in circuits adopting RBB.
The figure of merit permits to estimate the effectiveness
of static RBB, i.e., when is kept constant. However, some
other issues must be considered in the case of dynamic RBB is
Fig. 3. (a) Body biasing applied to pMOSFET. (b) Stacking applied to pMOS- adopted, where is dynamically varied according to the op-
FETs. (c) Joint body biasing and stacking applied to pMOSFETs. erating conditions [30]. One important issue regards the wakeup
time, i.e., the time required to switch from standby mode (with
) to active mode (with ). The wakeup
III. METHODOLOGY AND FIGURES OF MERIT TO time is set by the buffers that distribute the voltage to the
EVALUATE CIRCUIT-LEVEL POTENTIAL AND LIMITS FROM body capacitances of all transistors within the considered block
DEVICE MEASUREMENTS [4]. Hence, for a given available (dis)charge current (imposed
by the buffer sizing), the wakeup time is proportional to the
To assess an emerging technology for VLSI applications from overall capacitance (which is proportional to the body capaci-
single transistor measurements, some link between the device tance per unit width ), as well as to the required variation
and circuit (or system) level of abstraction must be provided. In of (which is clearly proportional to ; for example, to
the following, this link is built by introducing appropriate fig- reduce leakage by decades, the variation is exactly equal
ures of merit that permit to quantitatively evaluate and compare to ). Hence, a simple but powerful figure of merit for
the main parameters that are of interest in real VLSI circuits. the wakeup time of RBB schemes is the product [4].
In regard to the leakage in VLSI circuits, it is usually es- Again, this figure of merit depends only on device-level param-
timated through the and the subthreshold slope of a eters, but provides useful information at both the circuit and
single device [38]. However, it is well known that current system level of abstraction.
VLSI circuits widely employ various techniques to limit the Another important issue that arises in dynamic RBB schemes
leakage power consumption, since it has become dominant is the energy efficiency of the circuitry that generates . In-
in down-scaled technologies [36]. Hence, the actual leakage deed, every time is varied, the capacitance seen from the
that can be obtained in real circuits is mostly limited by the bulk of each transistor must be charged/discharged. This leads to
effectiveness of these techniques [39]. In other words, any a dynamic energy consumption that is proportional to the overall
figure of merit to estimate leakage in real circuit must explicitly capacitance seen from the bulk of all logic gates within the block
consider the impact of such low-leakage techniques [4]. Cur- (which is again proportional to ), as well as to the square of
rently, a few techniques are employed to reduce the leakage in the required variation with respect to (from the above
VLSI circuits: reverse body biasing (RBB), transistor stacking, discussion, it is proportional to ). Hence a powerful figure
and reverse gate biasing (RGB) [36], [39]. Actually, RGB can of merit that measures the energy efficiency of the RBB scheme
be applied to a very limited range of circuits (e.g., wordline is the product [4], which is again a simple function
decoders in memory arrays), hence it will not be considered in of device parameters but accounts for phenomena that are ob-
the following. The other two are discussed in Sections III-A served at the circuit and system level of abstraction.
and III-B, whereas considerations.
B. Considerations on Transistor Stacking
A. Considerations on Reverse Body Biasing
When two or more OFF transistors are stacked as in Fig. 3(b),
In RBB, leakage is reduced by setting the body voltage their leakage is lower than that of a single transistor by a factor
of the p-channel transistor above to increase the magnitude that is usually in the order of units, thanks to the well-
of the threshold voltage, as shown in Fig. 3(a). known stack effect [28], [29]. Parameter is a reasonable
Clearly, circuits under RBB can potentially exhibit low figure of merit to quantitatively evaluate the effectiveness of
leakage only if leakage has a strong dependence on , i.e., transistor stacking in reducing leakage.
values of slightly above are sufficient to achieve In general, depends on the number of stacked tran-
a considerable leakage reduction (similarly to the definition sistors , which is closely related to the fan-in of a given
of ). Hence, according to the detailed discussion in [4], the logic gate [29]. In particular, increases when increasing
effectiveness of RBB can be measured by the body bias voltage , although it usually tends to saturate to a constant value
variation needed to reduce the leakage current by one for [4]. The dependence on is of
decade, as defined in (1) [4] a certain interest in real designs, since it provides information
on the potential of a certain technology to reduce the leakage
(1a) in logic gates with a given fan-in. In turn, this gives guidelines
for the leakage-aware design of standard cells, as well as for the
composition of the cell library. As a further typical case where
(1b)
stack effect takes place, in this work we also evaluated
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

MAGNONE et al.: UNDERSTANDING THE POTENTIAL AND THE LIMITS OF GERMANIUM PMOSFETS FOR VLSI CIRCUITS 5

when sleep transistors are used to reduce the leakage of an in-
active block.
As an extension of the above discussed concepts, the tran-
sistor stacking and RBB can be applied jointly, as shown in
Fig. 3(c). In this case, the relevant figure of merit
for the total effect of RBB and stacking is
Finally, the impact of the number of stacked transistors
on the on-current is another parameter that provides information
on the speed degradation in high fan-in (i.e., high ) logic
gates. This also gives clear guidelines on the maximum reason-
able fan-in in a standard cell, and hence on the composition of
a cell library.

(2) IV. EFFECTIVENESS OF BODY BIASING SCHEMES IN GE

CIRCUITS AND COMPARISON WITH SI CIRCUITS REVIEW OF GE
TRANSISTORS AND FABRICATED DEVICES
which is analogous to in (1), with the only difference that
the leakage current in (2) pertains to the transistor stack instead A. Device Considerations
of the single transistor [4]. Figures of merit for the wakeup time
The impact of the body voltage on the leakage of Si and
and energy efficiency of schemes with joint usage of dynamic
Ge transistors can be qualitatively understood by analyzing the
RBB and stacking can be immediately obtained by extending
effect of the source-body voltage , which is
those presented in the previous section.
negative when RBB is applied.
C. Considerations on the Speed Potential By applying a value different from 0 V, the leakage
through the source-bulk junction is no more negligible (in spite
As is well known, the gate delay is propor- of what shown in Fig. 2 in solid line). In order to overcome this
tional to the device parasitic capacitances and inversely propor- issue, an appropriate procedure has been used to subtract the
tional to the on-current , for a given supply voltage [40]. junction leakage from I-V characteristics. Given a certain
Hence, when comparing two different technologies, the overall value, the curve at 0 V is taken as a reference.
speed improvement of one compared to the other depends on After that, we evaluate the threshold voltage shifts between the
the ratio of device capacitances and on-currents. curves at 0 V and the reference one in the sub-
In regard to the on-current , it is usually evaluated at the threshold region (where the effect of the junction leakage cur-
maximum supply voltage allowed by the technology, and pro- rent is not significant). Based on the measured shifts, the new
vides useful information on the maximum driving capability of - curves for 0 V are calculated as rigid horizontal
transistors. However, is not adequate to evaluate the per- shifting of the reference curve instead of taking the measured
formance of VLSI circuits that either employ low voltages or curves at 0 V. This procedure allows to achieve an op-
use aggressive dynamic voltage scaling schemes to reduce the timum agreement, above threshold voltage, between the mea-
power consumption [41]. In these cases, it is necessary to eval- sured data for 0 V and the data extrapolated as a shifting
uate the degradation of the driving capability (and hence per- of the reference curves. Moreover, the zero-bias (i.e., with
formance) associated with the voltage reduction. A reasonable ) was equalized for the Si and Ge devices to perform a
measure of this degradation is the Alpha-Power law coefficient fair comparison. This is because in the available prototypes
, i.e., the effective exponent of the I-V characteristics of a is not exactly the same in the two technologies, hence the I-V
transistor when the source-drain voltage is kept constant [42]. characteristics (i.e., the zero-bias ) were properly shifted to
Greater values of indicate that the driving capability is more achieve in linear region for for both
sensitive to voltage scaling, i.e., a greater speed penalty is paid technologies.
when reducing ). From Fig. 4(a) and (b), the impact of on the threshold
Another parameter that can affect is its dependence on voltage in Ge transistors is more pronounced than in Si tran-
, which is modeled as as usual, sistors. Positive values of referring to the case of forward
where is the device parameter that accounts for the drain- body bias (FBB) are also reported for the sake of completeness,
induced barrier lowering (DIBL) and the high-field effects [41]. although the significant higher junction current in Ge devices
Since the gate delay associated with the low-to-high transition makes the FBB less attractive. The stronger dependence of
is evaluated from the time where the output is high (i.e., on is a general property of Ge transistors. To justify this
) to the time where the output reaches its 50% (i.e., property, let us consider the parameter ,
), we will define the effective on-current as in (3) whose approximate expression under is
[38]

(3)
(4)
that is the average between the initial and final value of . where is the gate dielectric capacitance per unit area,
The right-hand side was derived by considering the above de- is the semiconductor relative permittivity (vacuum abso-
pendence on and assuming . From (3), an lute permittivity), is the thermal voltage, is the semi-
increase in leads to a linear degradation of the tran- conductor doping density and is the semiconductor intrinsic
sistor driving capability, compared to the ideal on-current ob- concentration. From (4), assuming the same and , the
tained with . ratio of in the Ge and Si technology results to
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 6. S versus V in Si and Ge pMOSFETs.

B. Circuit- and System-Level Considerations on the

Effectiveness of RBB in Reducing Leakage
From a circuit perspective, the effectiveness of RBB schemes
in reducing leakage can be evaluated through the figure of merit
Fig. 4. Threshold voltage versus body bias voltage V =V 0V in in (1a), which is plotted in Fig. 6 versus . From this
(a) Si and (b) Ge pMOSFETs. figure, the ratio between the value of in Ge and Si tech-
nology is approximately constant in the practical range of
between 0.5 and 0 V. Indeed, voltages lower than 0.5 V
are impractical, as they do not bring any further advantage in
terms of subthreshold leakage [4], [39].
Since the ratio between of Ge and Si transistor is
almost constant for practical values of , let us evaluate
its numerical value assuming 0.4 V as done before.
From the measured values of and in Tables I and
II, the predicted value of for the Si (Ge) technology is
970 mV/dec (710 mV/dec), which is close to the measured
value of 959 mV/dec (773 mV/dec), thereby confirming the
good accuracy of the approximate expression (1a). Accord-
ingly, Ge transistors exhibit a 21% reduction in compared
Fig. 5. Parameter  versus V .
with Si devices, which clearly shows that RBB is more effec-
tive in Ge technology than in Si. In other words, the voltage
required by Ge transistors for a targeted
leakage reduction is 21% less than that required by Si devices.
This is essentially due to the increased sensitivity of on
(5) (i.e., parameter ), as was discussed before. Moreover,
this advantage of Ge transistors is expected to be even stronger
in the near future, as more refined Ge processes will permit to
whose parameters have the following numerical value: significantly reduce to values comparable to Si devices, as
cm discussed in Section II. In the most optimistic case where the
cm . Since and , Ge devices always Ge process improvements permit to achieve the same as Si
have a larger . Observe that the improvement in Ge devices, the of Ge transistor is 55% less than that of the
transistors is only weakly dependent on and is roughly equal Si device.3
to 1.4 for typical doping levels. Observe that the improvement offered by the Ge tech-
The above results are consistent with measurements. In de- nology is particularly appealing in the context of nanometer
tail, the experimentally found ratio is plotted versus technologies. Indeed, this means that RBB can be still used as
in Fig. 5. From this figure, the ratio between of the Ge and a powerful approach to reduce leakage in Ge VLSI circuits, as
Si device under RBB (i.e., ) is approximately inde- opposite to Si circuits, for which RBB is less and less effective
pendent of . For example, at 0.4 V in the at each new technology generation [41].
Ge technology is greater than in the Si by a factor of 2.2 (see At the system level, the greater effectiveness of RBB in Ge
Table II), which is higher than that predicted by (4). This dif- circuits translates into the reduction of the required to
ference may be explained by slight differences in and 3In this work, the percentage difference between two generic parameters A
between Si and Ge devices. and B is defined as 100( 0 ) [( + ) 2]
A B= A B= .
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MAGNONE et al.: UNDERSTANDING THE POTENTIAL AND THE LIMITS OF GERMANIUM PMOSFETS FOR VLSI CIRCUITS
TABLE III
RATIO OF FIGURES OF MERIT FOR THE WAKEUP TIME AND ENERGY EFFICIENCY
achieve a targeted leakage reduction, which in turn simplifies
the design of the charge pumps that generate the reverse body
bias voltage, and also reduces the area/energy overhead associ-
ated with them [36], [39].
C. Wakeup Time and Energy Overhead in RBB Schemes
In regard to the wakeup time in dynamic RBB schemes, let
us evaluate to the figure of merit that was introduced
in Section III-A. As the measurement of the capacitance
is prone to error, let us resort to a qualitative analysis of its main
contributions. The capacitance seen from the bulk node of
a transistor consists of the sum of the gate contribution (between
bulk and gate) and the junction contribution (associated with the
source-bulk and drain-bulk junction capacitances). The former
contribution is basically the same for both Ge and Si devices,
as they have the same gate stack. The junction contribution is
different, and is proportional to (being the relative per-
mittivity of the bulk) for an assigned doping density and pro-
file. Hence, the ratio of the capacitance contribution of the Ge
and Si transistor is equal to . As a conse-
quence, of the Ge transistor is greater than the Si device
by a factor of 1.16 if is dominated by the junction contri-
bution (worst case in Table III), whereas it is the same as the Si
device if is dominated by the gate contribution (best case
in Table III). In practical cases, of the Ge transistor lies
between these two extreme (but close) values. Hence, from data
in Table III, Ge transistors have in the best (worst) case a 21%
(6.2%) lower , compared to Si devices, which trans-
lates into the same percentage reduction in the wakeup time for a
given driving capability of the buffer driving the body terminal.
Hence, Ge technology is expected to permit to implement dy-
namic body biasing schemes that are able to switch more rapidly
from standby to active mode, or vice versa. This is clearly bene-
ficial, as it permits to use more aggressive power-down policies
that turn blocks off as soon they are not used, so that a larger
leakage reduction can be achieved [4], [36].
Regarding the energy efficiency of RBB schemes, the rele-
vant figure of merit for the Ge technology is easily
found to be 42% (29%) lower than that of Si technology in the
best (worst) case. This translates into the same percentage re-
duction in the energy overhead associated with the circuit imple-
mentation of the RBB scheme. This remarkable energy savings
is a nice feature of Ge circuits, and permits to adopt more ag-
gressive power-down policies that turn unused blocks off more
frequently to standby mode, thereby achieving a larger leakage
reduction [4], [36].
7
V. EFFECTIVENESS OF TRANSISTOR STACKING IN GE CIRCUITS
AND COMPARISON WITH SI CIRCUITS
The effectiveness of transistor stacking is evaluated through
the stacking factor introduced in Section III-B. From its
definition, this parameter should be directly measured from ad
hoc structures with stacked transistors in off state. However,
in practical cases (like our prototypes) where only single-de-
vice structures are available for measurements, some appro-
priate strategy must be adopted to evaluate the stack current
and hence the stacking factor . To this aim, in this
work we performed appropriate measurements on a single de-
vice and applied a suitable strategy to evaluate the current in
stacked transistors. The procedure consists in finding the op-
erating point of the stacked transistors that allows to force the
same current through the series transistors.
By applying the above procedure to the case of two and three
stacked transistors (i.e., ), we evalu-
ated the effectiveness of the joint adoption of RBB and stacking.
The leakage of a single transistor, as well as two and three
stacked transistors, is plotted in Fig. 7 versus .
The resulting stacking factors for the Si and Ge technology
are reported in Table IV in the case of . From
this table, the stacking of two or three transistors permits in
the Ge technology a 1.5 greater leakage reduction compared
with Si pMOSFETs. Again, this confirms the better ability of
Ge technology to reduce leakage through standard circuit tech-
niques. This experimental result can be justified by referring to
the well-known approximate expression of the stacking factor
in (6) under [28]
(6)
From (6) it is possible to observe that the greater ability of Ge
technology to reduce leakage through stacking is due to the
higher coefficient , although it is limited by the higher value
of in the denominator of (6). However, as was previously dis-
cussed, the expected process improvements will reduce of Ge
transistors to values closer to those in Si technology. Conse-
quently, an even larger leakage reduction in stacked Ge pMOS-
FETs is expected.
The figure of merit in (2) is plotted versus
in Fig. 8 for the Si and Ge technology. As expected,
these figures show that , which agrees
with the intuition, since the effectiveness of joint RBB and
stacking (evaluated by ) is better than RBB only
(evaluated by ). For example, in two stacked transistors
with 0.4 V, results to 853 mV/dec (631
mV/dec) in the case of Si (Ge) technology (similar results were
obtained for three stacked transistors). Hence, Ge transistors
exhibit a 30% reduction in , with respect to Si
devices, thereby confirming that Ge technology is also more ef-
fective in reducing leakage when using both RBB and stacking.
It is worth noting in Fig. 8 that, in both Si and Ge technolo-
gies, the implementation of two or three stacked transistors leads
to the same , meaning that RBB is equally effec-
tive regardless of the number of stacked transistors. Neverthe-
less, this does not imply the same leakage reduction in two or
three stacked transistors, as confirmed by Fig. 7, where leakage
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 7. Leakage current of (a) Si and (b) Ge device versus V

Fig. 8. S of (a) Si and (b) Ge device versus V
for a single
for two and three
transistor, two stacked transistors, and three stacked transistors. stacked transistors.

TABLE IV
STACKING FACTOR VERSUS NUMBER OF STACKED TRANSISTORS
(V V = V 0 0.4 V) =0
significantly depends on the number of stacked transistors. (this
difference is due to the stack effect).
Observe that the ratio of in Fig. 8 for the Ge and
Si technology (and hence the above results) is almost indepen-
dent of , thus confirming the generality of the numerical re-
sult. As already observed in the previous subsection, the above
discussed advantages of Ge technology is expected to signifi-
cantly increase in the near future, thanks to the improvements
in Ge processes.
The analysis of the impact of joint effect of RBB and tran-
sistor stacking on wakeup time and energy overhead is similar
to the one reported in Section IV-C. From data in Table III, Ge
transistors have in the best (worst) case a 30% (15%) lower
, compared to Si devices, which translates
into the same percentage reduction in the wakeup time for
a given driving capability of the buffer driving the body ter-
minal. Regarding the energy efficiency, the figure of merit
for the Ge technology is easily found to be
58% (45%) lower than that of Si technology in the best (worst)
case. This translates into the same percentage reduction in the
energy overhead associated with the circuit implementation of
the RBB scheme.
By comparing these results with the ones reported in
Section IV-C, it is evident that the joint effect of RBB and
transistor stacking allows to further improve the wakeup time
and energy overhead advantages of Ge devices compared to the
case of RBB only.
Let us now analyze the stacking effect in power-gated circuits
where a sleep transistor is used to reduce leakage of an inactive
block. To this purpose, we made the following assumptions.
— The intrinsic leakage of the sleep transistor is lower than
that of transistors within logic gates by a decade (i.e., the
threshold voltage of the sleep transistor is increased by
the subthreshold slope, as compared to transistors in logic
gates).
— The width of the sleep transistor was sized to keep
its maximum voltage drop (which degrades the effective
supply voltage seen by logic gates) to 5% of . Clearly,
the maximum voltage drop depends on the current that is
drawn by the logic gates, which is in turn set by the max-
imum number of logic gates that switch simultaneously.
To derive numerical examples, we assumed for simplicity that
a sleep transistor is connected to 100 minimum-sized inverters
(with width ). Then, we repeated the sleep transistor sizing
and leakage calculations by assuming that the number of logic
gates that switch simultaneously varies from 5 to 30. On
one hand, we found that in order to keep the voltage drop on the
Ge sleep transistor below the 5% of must be 4.97
times larger than . On the other hand, in case of Si
sleep transistor, the required must be 6.89 times larger
than . Under this conditions we evaluated in Fig. 9
the factors as a function of . In this figure we can
see that Ge devices allow a larger leakage reduction (by a factor
2) with respect to Si devices, since the required size of the Ge
sleep transistor is smaller.
As opposite to the case of dynamic body biasing, the wakeup
time associated with power gating is not an issue. Indeed, it
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

MAGNONE et al.: UNDERSTANDING THE POTENTIAL AND THE LIMITS OF GERMANIUM PMOSFETS FOR VLSI CIRCUITS 9

Fig. 9. Leakage reduction X in power-gated circuits where sleep transis-

tors are used to drive 100 inactive pMOSFETs, as a function of the number of
simultaneously active gatesN .

is well known to be much smaller than that associated with

dynamic (adaptive) body biasing in practical cases (see, e.g.,
[36]). This is easily explained by considering that, during
the standby-to-active mode transition, the capacitance that is
switched in the case of power gating to turn on the considered
block is much smaller than that in the case of body biasing. As Fig. 10. Plot of I versus V for the (a) Si and (b) Ge pMOSFETs.
an example, in [43] it was shown that the wakeup time under
power gating can be even a small fraction (1/5) of a clock cycle,
Now, let us evaluate the effective current that is actu-
as opposite to body biasing that has a wakeup time of multiple
ally available for the (dis)charge of the load capacitance of a
clock cycles.
generic logic gate in (3). From (3), is influenced by
VI. ANALYSIS OF THE SPEED POTENTIAL AND COMPARISON through coefficient , whose value for the considered tech-
WITH SI CIRCUITS nologies is reported in Table II. From this table, in the Si
(Ge) technology is equal to 25 mV/V (62 mV/V). Although the
The performance of VLSI systems is limited by the intercon- larger value of in Ge technology was found to be benefi-
nect and gate delay [41]. The interconnect delay mainly depends cial in terms of leakage reduction through stacking in Section V,
on the physical and geometrical features of the interconnect hi- from (3) it also determines a higher degradation of the on-cur-
erarchy (i.e., the back-end), which is not directly related to the rent compared to the ideal value that would be obtained in
front-end process optimization, and hence on the adopted tech- a single pMOSFET at . More specifically, the term
nology. For this reason, the Ge technology will be compara- in (3) results to 0.995 (0.989) for the Si (Ge)
tively evaluated by explicitly referring only to the gate delay. technology for 0 V. Similar results are obtained when
In the following, a detailed analysis of the parameters that af- RBB is adopted, as is shown in the plot of versus in
fect the gate delay is presented. Fig. 11. For example, results to 0.994 (0.985) for the Si
From experimental measurements in Fig. 2, the on-current (Ge) technology for 0.4 V. Accordingly, the on-cur-
evaluated at the maximum supply voltage of 1 V results rent degradation due to term in (3) is in the order of a
to 310 A/ m (209 A/ m) for a single Ge (Si) device, as few percentage points, and slightly more in the specific case of
reported in Table II. Apparently, the Ge technology permits a Ge transistors. Anyway, the small degradation is negligible
remarkable 1.5 improvement in , which can potentially compared with the above shown advantage of Ge technology in
bring a similar speed advantage for comparable transistor capac- terms of , hence the above results still hold. In other words,
itances. Observe that this advantage of Ge technology slightly the worse (i.e., DIBL and high-field effects) of Ge transis-
reduces when applying RBB, as is shown in the plot of tors is not an issue.
versus in Fig. 10. For example, the advantage of Observe that the above discussed increase in Ge tech-
the Ge transistor is reduced to a factor 1.37 under RBB with nology can be easily justified by considering the approximate
0.4 V, which is still considerable. This reduc- expression of DIBL effect (7) derived from the voltage-doping
tion in the speed advantage under strong RBB is easily explained transformation model [44]
by considering that the threshold voltage (and hence ) in Ge
transistors is more sensitive to compared to Si devices, as (7)
discussed in Section IV-A. This improvement in terms of
(and speed) is lower than the 2 low-field mobility improve- where is the bulk permittivity, is the oxide permittivity,
ment offered by Ge transistors, since the is evaluated at high is the electrical effective channel length, is the gate oxide
longitudinal field (high voltages) close to the saturation ve- thickness, is the source and drain junction depth, and
locity. is the depth of the depletion region underneath the gate. EI is
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

from a 15% lower4 degradation with respect to the single de-

vice, compared to Si technology. In turn, this is because stacked
transistors experience a lower (and hence a lower longitu-
dinal field), thus the higher Ge low-field mobility determines a
more effective drive current increase.
Summarizing, Ge circuits are expected to have a significant
(1.5 ) speed advantage compared to Si circuit under the same
capacitance, and this advantage is even greater (by a further
15%) in complex gates with a greater number of stacked tran-
sistors (i.e., fan-in).
Now, we can combine the analysis of the on-current and
the load capacitance associated with gate and drain ter-
minals of transistors. In practical cases where one to three tran-
Fig. 11.  parameter versus V for the Si and Ge pMOSFETs.
sistors are stacked, the on-current was shown to be im-
proved by a factor of 1.5 –1.8 when Ge transistors are em-
TABLE V ployed instead of Si devices. On the other hand, in Ge tran-
ON-CURRENT UNDER STACKED TRANSISTORS sistors is slightly higher than in Si transistors, by at
most a factor 1.16 (see Section IV-C). Comprehensively, the gate
delay in Ge technology turns out to be at
least 1.29 –1.55 lower than that in Si technology at the same
voltage, and even 1.5 –1.8 if the load capacitance is domi-
nated by gate or interconnect capacitances. Results on the gate
delay comparison are reported in Table VI.
TABLE VI
GATE DELAY IMPROVEMENT VERSUS NUMBER OF STACKED TRANSISTORS
(V V = V 0 0.4 V) =0 VII. ANALYSIS OF LEAKAGE-PERFORMANCE TRADEOFF AND
STATIC/DYNAMIC VOLTAGE SCALING
In this section, the leakage-performance tradeoff and
the impact of voltage scaling are respectively discussed in
Section VII-A and VII-B.

A. Analysis of Leakage-Performance Tradeoff

Fig. 12. I-V characteristics of Ge and Si transistor prototypes, as well as of Si
transistor with V tuned to get the same speed as Ge.
called “Electrostatic Integrity” factor and depends on the device
geometry. Since Ge has a higher permittivity, by assuming the
same EI, a larger value is obtained in Ge devices.
Finally, it is interesting to evaluate the degradation of the
on-current due to the transistor stacking. By following a pro-
cedure similar to that in Section V, the resulting in a stack
of two and three transistors is reported in Table V. From this
table, it is apparent that Ge circuits with stacked transistors have
a 1.8 advantage compared to Si circuits, which is even
greater than that of a single device (1.5 , as previously dis-
cussed). This is explained by the fact that Ge transistors suffer
In the previous sections, leakage and performance were ana-
lyzed adopting a Ge and a Si technology with similar features
(e.g., gate stack, ). Analysis showed that Ge circuits are sig-
nificantly faster than Si circuits, permit a greater leakage reduc-
tion when resorting to standard circuit techniques, but have a
higher intrinsic device leakage.
Now, let us analyze all these aspects in a consistent manner,
i.e., by comparing Ge and Si technologies in terms of leakage
under the same performance. To this aim, the threshold voltage
of the Si technology must be reduced to achieve the same gate
delay (or equivalently ) as the Ge counterpart. The resulting
of the Si transistor is 118 mV, and the resulting I-V charac-
teristics is shown in Fig. 12 along with that of the Si and Ge tran-
sistor prototypes. Analysis of this figure reveals that the leakage
current in Ge technology is actually lower than Si technology by
a factor of 6.4, at same speed, which is a remarkable result. Ob-
serve that this advantage of Ge technology is expected to further
improve in the near future, thanks to the process improvements
that will permit to reduce the subthreshold swing .
Under the above discussed scenario, the leakage reduction
permitted by the Ge technology under RBB and stacking tech-
niques is reported in Table VII, assuming that of Ge tech-
nology is that of the fabricated prototypes. Inspection of this
4More specifically, I in a stack of N Si (Ge) transistors is easily found
to decrease by a factor equal to N (0:85 1 N ), compared with the single
device.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

MAGNONE et al.: UNDERSTANDING THE POTENTIAL AND THE LIMITS OF GERMANIUM PMOSFETS FOR VLSI CIRCUITS 11

TABLE VII
LEAKAGE REDUCTION PERMITTED BY GE TECHNOLOGY AT SAME SPEED

Fig. 14. I versus V (left axis) and I of Ge normalized to Si technology

versus V (right axis).

Fig. 13. I 0I tradeoff for Si and Ge pMOSFET.

table reveals that the Ge technology permits a leakage reduc- Fig. 15. I versus V (left axis) and I of Ge normalized to Si technology
tion that ranges from 6.4 to 14.6, if the Si process is tuned to versus V (right axis).
achieve the same speed as Ge technology. This is a very inter-
esting result, and demonstrates that the mobility improvement
of Ge transistors can be suitably traded off to significantly re- the higher in Ge devices which affects less the leakage at
duce the power consumption of VLSI circuits. Moreover, even lower .
better results are expected in the near future, thanks to the Ge From the plot of versus in Fig. 15, the advantage
process improvements. of the Ge technology in terms of on-current tends to further
In Fig. 13 we evaluated the tradeoff when applying increase when is reduced. This result is in contrast with
different RBB to a single pMOSFET or to stacked transistors. the higher in Ge devices, which should reduce not only
From this figure we can draw two important conclusions. The the off-current ratio but also the on-current
first one is that RBB is more effective when applied to Ge cir- ratio . The observed opposite trend can be ex-
cuits, as compared to Si circuits, and the resulting leakage re- plained by referring to the dependence of the mobility on both
duction factor is improved. This is obtained thanks to a higher the drain and gate voltage. In regard to the first dependence, it
, which at the same time also leads to a stronger reduc- is clear that a reduced tends to reduce the high longitu-
tion. The second one it that, when applying RBB to two or three dinal fields (high voltages), and hence the ratio of the Ge
stacked transistors, the observed reduction is smaller than and Si currents is closer to the ratio of the low-field mobilities
the one observed when applying RBB to a single transistors, for (which is 2, according to Table I). Regarding the dependence of
both Ge and Si pMOSFETs. gate voltage, a reduced tends to reduce the high transversal
fields (high voltages), and again the ratio of the Ge and Si
B. Impact of Static/Dynamic Voltage Scaling currents is closer to the ratio of the low-field mobilities. As a
confirmation of the higher mobility degradation in Ge devices
Now, let us evaluate the impact of the voltage scaling on per- at high voltages, it was found that the Alpha-Power law co-
formance and leakage, as discussed in Section III-C. To this aim, efficient of the Ge (1.34) is lower than in Si (1.52). Summa-
the fabricated prototypes were measured under the wide range rizing, the increased (and speed) advantage of Ge transistors
of supply voltages from 0.7 to 1.2 V. for decreased is explained by the mobility enhancement
From the plot of versus in Fig. 14, the disadvantage due to the reduction of both longitudinal fields (lower ) and
of the Ge technology with respect to Si technology in terms of transversal fields (lower ).
off-current is reduced by one decade when is decreased As a result, the advantages of Ge technology in terms of
from 1.2 to 0.7 V. This trend can be explained by referring to on-current and off-current with voltage scaling are particularly
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
12
appealing in low-voltage applications, as well as in systems that
take full advantage of ultra-dynamic voltage scaling.
VIII. CONCLUSION
In this paper, Ge pMOSFETs have been analyzed to under-
stand their potential and limits in the context of VLSI circuits.
The analysis is based on an innovative methodology that derives
circuit- and system-level parameters from experimental mea-
surements of device prototypes. Appropriate figures of merit are
discussed to fill the gap between these levels of abstraction, re-
alistically considering the adoption of system-level schemes to
reduce leakage.
The comparative leakage analysis has been focused only on
the channel leakage component while the contribution of the
junction leakage, which is significantly higher in Ge circuits,
has been neglected, since it is expected to significantly decrease
with major Ge process improvements in the near future.
Measurements showed that the leakage reduction obtained
with RBB in Ge circuits is improved by 21%, compared to Si
circuits. This is due to the improved sensitivity of Ge threshold
voltage on body bias voltage, which was justified by the higher
Ge permittivity and intrinsic concentration. Moreover, the Ge
process improvements expected in the near future may increase
this advantage to up 55%. In dynamic RBB schemes, it has also
been shown that the wakeup time (energy overhead) associated
with the circuit implementation of the RBB scheme in Ge tech-
nology is reduced by up to 21% (42%), compared with Si cir-
cuits. A 2 improvement in the effectiveness of power gating
was also observed, compared with Si devices.
Analogously, the leakage reduction obtained with transistor
stacking in Ge technology is improved by 1.5 , compared with
Si technology. This has been shown to be due to the greater
DIBL coefficient (which only marginally affects speed).
Regarding the performance, Ge transistors have been shown
to exhibit a 2 mobility improvement, but the resulting on-cur-
rent improvement is about 1.5 due to high-field effects. A
slight device capacitance increase (by up to 16%) has also been
estimated in Ge transistors. The net speed advantage of Ge tech-
nology turns out to range from 1.29 to 1.5 , compared with
Si technology.
To understand the leakage-delay tradeoff, the Ge and Si cir-
cuits have been compared at the same speed by decreasing the
Si threshold voltage to match the drive current of Ge circuits. As
a result, Ge circuits exhibit a leakage reduction that ranges from
6.4 to 14.6, depending on the adopted low-leakage scheme. Ex-
pected Ge process improvements will even increase this advan-
tage. This makes Ge technology extremely interesting for VLSI
implementations in future technology nodes.
Regarding the impact of dynamic voltage scaling on the cir-
cuit performance, results showed that Ge circuits suffer from a
reduced speed degradation when the supply voltage is reduced.
This translates into a remarkable advantage of Ge technology,
in the context of real VLSI circuits that fully exploit dynamic
voltage scaling.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ACKNOWLEDGMENT
The authors would like to thank IMEC P-line and IMEC Core
Partners for their support and G. Eneman, J. Mitard, E. Simoen,
M. Meuris, and S. Kubicek for useful input and discussions.
REFERENCES
[1] “International technology roadmap for semiconductors,” 2003–2007.
[Online]. Available: http://public.itrs.net
[2] H.-S. P. Wong, “Beyond the conventional transistor,” IBM J. Res. De-
velop., vol. 46, no. 2/3, pp. 133–168, 2002.
[3] Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S.-H.
Lo, G. A. Sai-Halasz, R. G. Viswanathan, H.-J. C. Wann, S. J. Wind,
and H.-S.P. Wong, “CMOS scaling into the nanometer regime,” Proc.
IEEE, vol. 85, no. 4, pp. 486–504, Apr. 1997.
[4] M. Agostinelli, M. Alioto, D. Esseni, and L. Selmi, “Leakage-delay
tradeoff in FinFET logic circuits: A comparative analysis with bulk
technology,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.
16, no. 2, pp. 232–245, Feb. 2010.
[5] T. Yamamoto, Y. Yamashita, M. Harada, N. Taoka, K. Ikeda, K.
Suzuki, O. Kiso, N. Sugiyama, and S.-I. Takagi, “High performance
60 nm gate length Germanium p-MOSFETs with Ni germanide metal
source/drain,” in IEDM Tech. Dig., 2007, pp. 1041–1043.
[6] G. Nicholas, B. D. Jaeger, D. P. Brunco, P. Zimmerman, G. Eneman,
K. Martens, M. Meuris, and M. Heyns, “High-performance deep sub-
micron Ge pMOSFETs with halo implants,” IEEE Trans. Electron De-
vices, vol. 54, no. 9, pp. 2503–2511, Sep. 2007.
[7] C. Le Royer, L. Clavelier, C. Tabone, C. Deguet, L. Sanchez, J.-M.
Hartmann, M.-C. Roure, H. Grampeix, and S. Deleonibus, “0.12 m
p-MOSFETs with high- and metal gate fabricated in a Si process line
on 200 mm GeOI wafers,” in Proc. 37th ESSDERC, 2007, pp. 458–461.
[8] K. Romanjek, L. Hutin, C. Le Royer, A. Pouydebasque, M.-A. Jaud,
C. Tabone, E. Augendre, L. Sanchez, J.-M. Hartmann, H. Grampeix,
V. Mazzochi, S. Soliveres, R. Truche, L. Clavelier, and P. Scheiblin,
“High performance 70 nm gate length Germanium-on-insulator
pMOSFET with high- metal gate,” in Proc. 38th ESSDERC, 2008,
pp. 75–78.
[9] G. Hellings, J. Mitard, G. Eneman, B. De Jaeger, D. P. Brunco, D.
Shamiryan, T. Vandeweyer, M. Meuris, M. M. Heyns, and K. De
Meyer, “High performance 70-nm Germanium pMOSFETs with
Boron LDD implants,” IEEE Electron Device Lett., vol. 30, no. 1, pp.
88–90, Jan. 2009.
[10] D. Maji, F. Crupi, E. Amat, E. Simoen, B. De Jaeger, D. P. Brunco, C.
R. Manoj, V. R. Rao, P. Magnone, G. Giusi, C. Pace, L. Pantisano, J.
Mitard, R. Rodriguez, and M. Nafrìa, “Understanding and optimization
of hot carrier reliability in Germanium-on-silicon pMOSFETs,” IEEE
Trans. Electron Devices, vol. 56, no. 5, pp. 1063–1069, May 2009.
[11] J. Mitard, C. Shea, B. De Jaeger, A. Pristera, G. Wang, M. Houssa, G.
Eneman, G. Hellings, W. E. Wang, J. C. Lin, F. E. Leys, R. Loo, G.
Winderickx, E. Vrancken, A. Stesmans, K. DeMeyer, M. Caymax, L.
Pantisano, M. Meuris, and M. Heyns, “Impact of EOT scaling down
to 0.85 nm on 70 nm Ge-pFETs technology with STI,” in Proc. Symp.
VLSI Technol., 2009, pp. 82–83.
[12] P. Zimmerman, G. Nicholas, B. De Jaeger, B. Kaczer, A. Stesmans,
L.-A. Ragnarsson, D. P. Brunco, F. E. Leys, M. Caymax, G. Winder-
ickx, K. Opsomer, M. Meuris, and M. M. Heyns, “High performance
Ge pMOS devices using a Si-compatible process flow,” presented at the
IEDM Tech. Dig., San Francisco, CA, 2006.
[13] E. Simoen, F. De Stefano, G. Eneman, B. De Jaeger, C. Claeys, and
F. Crupi, “On the temperature and field dependence of trap-assisted-
tunneling current in Ge p n junctions,” IEEE Electron Device Lett.,
vol. 30, no. 5, pp. 562–564, May 2009.
[14] G. Eneman, O. Sicart i Casain, E. Simoen, D. P. Brunco, B. De Jaeger,
A. Satta, G. Nicholas, C. Claeys, M. Meuris, and M. M. Heyns, D.
Schmitt-Landsiedel and R. Thewes, Eds., “Analysis of junction leakage
in advanced Germanium p /n junctions,” in Proc. ESSDERC, Munich,
Germany, 2007, pp. 454–457.
[15] G. Eneman, M. Wiot, A. Brugere, O. S. I. Casain, O. S. I. S. Sonde, D.
P. Brunco, B. De Jaeger, A. Satta, G. Hellings, K. De Meyer, C. Claeys,
M. Meuris, M. M. Heyns, and E. Simoen, “Impact of donor concentra-
tion, electric field, and temperature effects on the leakage current in
Germanium p /n junctions,” IEEE Trans. Electron Devices, vol. 55,
no. 9, pp. 2287–2296, Sep. 2007.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MAGNONE et al.: UNDERSTANDING THE POTENTIAL AND THE LIMITS OF GERMANIUM PMOSFETS FOR VLSI CIRCUITS
[16] K. Martens, B. De Jaeger, M. Meuris, G. Groeseneken, and H. E. Maes,
“Interface characterization of Si-passivated HfO Germanium capaci-
tors using DLTS measurements,” Mater. Sci. Semicond. Process., vol.
9, pp. 742–749, 2006.
[17] J. Mitard, B. De Jaeger, F. E. Leys, G. Hellings, K. Martens, G. En-
eman, D. P. Brunco, R. Loo, J. C. Lin, D. Shamiryan, T. Vandeweyer,
G. Winderickx, E. Vrancken, C. H. Yu, K. De Meyer, M. Caymax, L.
Pantisano, M. Meuris, and M. Heyns, “Record I =I performance
for 65 nm Ge pMOSFET and novel Si passivation scheme for improved
EOT scalability,” in IEDM Tech. Dig., 2008, pp. 1–4.
[18] K. Martens, J. Mitard, B. De Jaeger, M. Meuris, H. Maes, F. Minucci,
F. Crupi, and G. Groeseneken, “Impact of Si-thickness on interface
and device properties for Si-passivated Ge pMOSFETs,” in Proc. Eur.
Solid-State Device Res. Conf., 2008, pp. 138–141.
[19] P. Magnone, F. Crupi, G. Giusi, C. Pace, E. Simoen, C. Claeys, L.
Pantisano, D. Maji, V. R. Rao, and P. Srinivasan, “1/f noise in drain
and gate current of MOSFETs with high-k gate stacks,” IEEE Trans.
Device Mater. Reliab., vol. 9, no. 2, pp. 180–189, Sep. 2009.
[20] E. Batail, S. Monfray, C. Tabone, O. Kermarrec, J. F. Damlencourt, P.
Gautier, G. Rabille, C. Arvet, N. Loubet, Y. Campidelli, J. M. Hart-
mann, A. Pouydebasque, V. Delaye, C. Le Royer, G. Ghibaudo, T.
Skotnicki, and S. Deleonibus, “Localized ultra-thin GeOI: An innova-
tive approach to germanium channel MOSFETs on bulk Si substrates,”
presented at the IEDM Tech. Dig., San Francisco, CA, 2008.
[21] R. Xie, T. H. Phung, W. He, Z. Sun, M. Yu, Z. Cheng, and C. Zhu,
“High mobility high-/Ge pMOSFETs with 1 nm EOT-new concept
on interface engineering and interface characterization,” presented at
the IEDM Tech. Dig., San Francisco, CA, 2008.
[22] M. Caymax, G. Eneman, F. Bellenger, C. Merckling, A. Delabie,
G. Wang, R. Loo, E. Simoen, J. Mitard, B. De Jaeger, G. Hellings,
K. De Meyer, M. Meuris, and M. Heyns, “Germanium for advanced
CMOS anno 2009: A SWOT analysis,” in IEDM Tech. Dig., 2009, pp.
461–464.
[23] M. Kobayashi, T. Irisawa, B. M. Kope, Y. Sun, K. Saraswat, H. S.-P.
Wong, P. Pianetta, and Y. Nishi, “High quality GeO2/Ge interface
formed by SPA radical oxidation and uniaxial stress engineering for
high performance Ge NMOSFETs,” in Proc. Symp. VLSI Technol.,
2009, pp. 76–77.
[24] F. Bellenger, M. Houssa, A. Delabie, V. Afanasiev, T. Conard, M.
Caymax, M. Meuris, K. De Meyer, and M. M. Heyns, “Passivation of
Ge(100)/GeO2/high- gate stacks using thermal Oxide treatments,” J.
Electrochem. Soc., vol. 155, no. 2, pp. 33–38, 2008.
[25] C. Lee, T. Nishimura, N. Saido, K. Nagashio, K. Kita, and A. Toriumi,
“Record-high electron mobility in Ge n-MOSFETs exceeding Si uni-
versality,” in IEDM Tech. Dig., 2009, pp. 457–460.
[26] D. Kuzum, T. Krishnamohan, A. Nainani, Y. Sun, P. A. Pianetta, H.
S.-P. Wong, and K. C. Saraswat, “Experimental demonstration of high
mobility Ge NMOS,” in IEDM Tech. Dig., 2009, pp. 453–456.
[27] B. Razavi, “Prospect of CMOS technology for high-speed optical com-
munication circuits,” IEEE J. Solid-State Circuits, vol. 37, no. 9, pp.
1135–1145, Sep. 2002.
[28] S. Narendra, V. De, S. Borkar, D. Antoniadis, and A. Chandrakasan,
“Full-chip subthreshold leakage power prediction and reduction tech-
niques for sub-0.18-m CMOS,” IEEE J. Solid-State Circuits, vol. 39,
no. 3, pp. 501–510, Mar. 2004.
[29] M. Johnson, D. Somasekhar, L.-Y. Chiou, and K. Roy, “Leakage con-
trol with efficient use of transistor stacks in single threshold CMOS,”
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, pp.
1–5, Feb. 2002.
[30] J. Tschanz, S. Narendra, Y. Ye, B. Bloechel, S. Borkar, and V. De, “Dy-
namic sleep transistor and body bias for active leakage power control
of microprocessors,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp.
1838–1845, Nov. 2003.
[31] M.-H. Chiang, K. Kim, C.-T. Chuang, and C. Tretz, “High-density re-
duced-stack logic circuit techniques using independent-gate controlled
double-gate devices,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp.
2370–2377, Sep. 2006.
[32] W. Zhang, J. Fossum, L. Mathew, and Y. Du, “Physical insights re-
garding design and performance of independent-gate FinFETs,” IEEE
Trans. Electron Devices, vol. 52, no. 10, pp. 2198–2206, Oct. 2005.
[33] D. K. Schroder, Semiconductor Material and Device Characteriza-
tion. New York: Wiley, 1998.
13
[34] H.-J. Cho, H. Yu Yu, V. S. Chang, A. Akheyar, S. Jakschik, T. Conard,
T. Hantschel, A. Delabie, C. Adelmann, S. Van Elshocht, L.-Å. Rag-
narsson, T. Schram, P. Absil, and S. Biesemans, “The impact of stacked
cap layers on effective work function with HfSiON and SiON gate di-
electrics,” IEEE Electron Device Lett., vol. 29, no. 7, pp. 743–745, Jul.
2008.
[35] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High- gate di-
electrics: Current status and materials properties considerations,” J.
Appl. Phys., vol. 89, no. 10, pp. 5243–5275, May 2001.
[36] S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS
Technologies. New York: Springer, 2006.
[37] J. Franco, B. Kaczer, A. Stesmans, V. V. Afanas’ev, K. Martens, M.
Aoulaiche, T. Grasser, J. Mitard, and G. Groeseneken, “Impact of
Si-passivation thickness and processing on NBTI reliability of Ge and
SiGe pMOSFETs,” presented at the 40th SISC, Arlington, VA, 2009.
[38] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices.
Cambridge, MA: Cambridge University Press, 1998.
[39] K. Itoh, M. Horiguchi, and H. Tanaka, Ultra-Low Voltage Nano-Scale
Memories. New York: Springer, 2007.
[40] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits
(A Design Perspective). Englewood Cliffs, NJ: Prentice-Hall, 2003.
[41] A. Chandrakasan, W. Bowhill, and F. E. Fox, Design of High-Perfor-
mance Microprocessor Circuits. Piscataway, NJ: IEEE Press, 2001.
[42] T. Sakurai and A. R. Newton, “Alpha-power law MOSFET model and
its applications to CMOS inverter delay and other formulas,” IEEE J.
Solid-State Circuits, vol. 25, no. 2, pp. 584–594, Apr. 1990.
[43] T. Miyazaki, T. Q. Canh, H. Kawaguchi, and T. Sakurai, “Observation
of one-fifth-of-a-clock wake-up time of power-gated circuit,” in Proc.
CICC, 2005, pp. 87–90.
[44] T. Skotnicki, “Heading for decananometer CMOS—Is navigation
among icebergs still a viable strategy?,” in Proc. 30th ESSDERC,
2000, pp. 19–33.
Paolo Magnone received the B.S. and M.S. degrees
in electronic engineering from the University of Cal-
abria, Rende, Italy, in 2003 and 2005, respectively,
and the Ph.D. degree in electronic engineering from
the University of Reggio Calabria, Rende, Italy, in
2009.
During 2006–2007 and 2007–2008, he joined the
Interuniversity MicroElectronics Center (IMEC),
Leuven, Belgium, within the APROTHIN project
(Marie Curie Actions), where he worked on param-
eters extraction and matching analysis of FinFET
devices. From 2009, he has been a Postdoctoral Researcher with the University
of Calabria. His research interests include the electrical characterization and
the modeling of semiconductor devices with particular emphasis on the study
of low frequency noise and of variability.
Felice Crupi received the M.S. degree in elec-
tronic engineering from the University of Messina,
Messina, Italy, in 1997 and the Ph.D. degree from
the University of Firenze, Firenze, Italy, in 2001.
Since 2002, he has been with the Dipartimento
di Elettronica, Informatica e Sistemistica, Univer-
sità della Calabria, Rende, Italy, as an Associate
Professor of electronics. Since 1998, he has been
a repeat Visiting Scientist with the Interuniversity
Micro-Electronics Center (IMEC), Leuven, Bel-
gium. In 2000, he was a Visiting Scientist with the
IBM Thomas J. Watson Research Center, Yorktown Heights, NY. In 2006,
he was a Visiting Scientist with the Universitat Autonoma de Barcelona,
Barcelona, Spain. His main research interests include reliability of VLSI
CMOS devices, modeling and simulation of VLSI CMOS devices, electrical
characterization techniques for solid state electronic devices and the design of
ultra-low noise electronic instrumentation. He has authored and coauthored
over 60 publications in peer-reviewed journals and over 40 publications in
international conference proceedings. His journals have been cited over 500
times and his h-index is equal to 12. He serves as a reviewer for leading journals
and conferences in the field of electronic devices. He has been the Coordinator
of research projects at National and International level.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
14
Massimo Alioto (M’01–SM’07) was born in
Brescia, Italy, in 1972. He received the laurea degree
in electronics engineering and the Ph.D. degree in
electrical engineering from the University of Catania,
Reggio, Italy, in 1997 and 2001, respectively.
In 2002, he joined the Dipartimento di Ingegneria
dell’Informazione (DII) of the University of Siena
as a Research Associate and in the same year as an
Assistant Professor. In 2005 he was appointed As-
sociate Professor of Electronics, and was engaged in
the same faculty in 2006. In the summer of 2007, he
was a Visiting Professor at EPFL—Lausanne, Switzerland. In 2009–2010, he
is Visiting Professor at BWRC—UCBerkeley, investigating on ultra-low power
circuits and wireless sensor nodes. Since 2001 he has been teaching undergrad-
uate and graduate courses on advanced VLSI digital design, microelectronics
and basic electronics. He has authored or coauthored about 150 publications
on journals (over 50, mostly IEEE Transactions) and conference proceedings.
Two of them are among the 25 most downloaded TVLSI papers in 2007 (re-
spectively, 10th and 13th). He is coauthor of the book Model and Design of
Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits
(Springer, 2005). His primary research interests include the modeling and the
optimized design of CMOS high-performance, low-power and ultra low-power
digital circuits, arithmetic and cryptographic circuits, interconnect modeling,
design/modeling for variability-tolerant and low-leakage VLSI circuits, circuit
techniques for emerging technologies. He is the director of the Electronics Lab
at University of Siena (site of Arezzo).
Prof. Alioto is a member of the HiPEAC Network of Excellence. He is the
Chair of the “VLSI Systems and Applications” Technical Committee of the
IEEE Circuits and Systems Society, for which he is also Distinguished Lecturer.
He is regularly invited to give talks and tutorials to academic institutions,
conferences and companies throughout the world. He has served as a member
of various conference technical program committees (ISCAS, PATMOS, ICM,
ICCD, CSIE) and Track Chair (ICECS, ISCAS, ICM, ICCD). He serves
as Associate Editor of the IEEE TRANSACTIONS ON VERY LARGE SCALE
INTEGRATION (VLSI) SYSTEMS, as well as of the Microelectronics Journal,
the Integration—The VLSI journal, and the Journal of Circuits, Systems, and
Computers. He is Guest Editor of the Special Issue “Advances in Oscillator
Analysis and Design” of the Journal of Circuits, Systems, and Computers
(2009), and Technical Program Chair for the ICM 2010 Conference.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Ben Kaczer received the M.S. degree in physical
electronics from Charles University, Prague, Czech
Republic, in 1992 and the M.S. and Ph.D. degrees in
physics from The Ohio State University, Columbus,
in 1996 and 1998, respectively.
In 1998, he joined the Reliability Group of the
Inter-university MicroElectronics Centre (IMEC),
Leuven, Belgium, where his activities have included
research on the degradation phenomena and re-
liability assessment of SiO , SiON, high-k, and
ferroelectric films; planar and multiple-gate FETs
and circuits; and characterization of Ge/III-V and MIM devices. He has au-
thored or coauthored more than 200 journal and conference proceeding papers,
and presented eight invited presentations and three International Reliability
Physics Symposium (IRPS) tutorials.
Dr. Kaczer has served or is serving in various functions at the IEEE Inter-
national Electron Device Meeting, IRPS, International Integrated Reliability
Workshop, IEEE Semiconductor Interface Specialists Conference, and Insu-
lating Films on Semiconductor conference. He received the OSU Presidential
Fellowship and support from Texas Instruments, Inc., Dallas, for his Ph.D. re-
search on the ballistic-electron emission microscopy of SiO and SiC films. He
was a recipient of the Best and the Outstanding Paper Awards at IRPS and the
Best Paper Award at the International Symposium on the Physical and Failure
Analysis of Integrated Circuits.
Brice De Jaeger received the B.S. and M.S. degrees
in electrical engineering from the Universiteit Gent,
Belgium, in 1994 and 1997.
Since 1997, he has been a Researcher with the
CMOS Device Research Department, Interuniversity
Microelectronics Center (IMEC), Leuven, Belgium.
His current research interests include the technology,
device integration and characterization of germa-
nium and III/V transistors.