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High-to-Low Propagation Delay tPHL Hand Calculation of tPHL

■ VIN switches instantly from low to high. Driver transistor (n-channel) ■ The output voltage decreases linearly over 0 < t < tPHL if we assume that the
immediately switches from cutoff to saturation; the p-channel pull-up switches MOSFET remains saturated:
from triode to cutoff.
■ Circuit during high-to-low transition: vOUT (t)

(p-channel MOSFET is cutoff)


IDn VOH
vOUT (t) slope = dvOUT / dt
+
CL = CG + CP VOH / 2
VIN (t > 0) = VOH
_

0 tPHL t

■ The high-to-low propagation delay is given by:


■ The voltage on the load capacitor at t = 0- was VOH; since n-channel MOSFET is
saturated initially and the input voltage is a constant, the drain current is initially
IDn(sat) for VGS = V+. dv OUT ( V OH ⁄ 2 ) – V OH – I Dn ( sat )
■ The high-to-low propagation delay tPHL is (by definition) the time required for ----------------- = ----------------------------------------- = -----------------------
dt t PHL CG + CP
VOUT to reach VOH / 2:

dvOUT d  QL  – I Dn ( sat ) Solving for the delay:


----------------- = -----  --------------------- = -----------------------
dt dt  C G + C P CG + C P
( C G + C P ) ( V OH ⁄ 2 )
t PHL = ---------------------------------------------------------------------------
2
µ n C ox ( W ⁄ 2L ) n ( V OH – V Tn )

EECS 105 Fall 1998 EECS 105 Fall 1998


Lecture 17 Lecture 17
Graphical Interpretation Low-to-High Propagation Delay tPLH

■ The n-channel driver remains saturated throughout the first half of the transition ■ For the low-to-high transition, the n-channel device is cutoff and the p-channel
from high-to-low... MOSFET is initially saturated and supplying - IDp(sat) to charge up the gate and
parasitic capacitances.
ID VOUT
VDD
t = tPHL t = 0+
VIN = VOH
VOH
VSGp +
_

t = 0−
VOH
VIN = 0V
2
- IDp
0 0 VIN = 0 V
0 VOUT 0 tPHL t
VOH VOH
2
(a) (b)

note that the characteristics above are not for a square-law MOSFET, which
would enter the triode region for VOUT < VOH - VTn; the error is not large enough ■ Therefore,
to matter for hand calculations in any case

( C G + C P ) ( V OH ⁄ 2 )
t PLH = ---------------------------------------------------------------------------
2
µ p C ox ( W ⁄ 2L ) p ( V OH + V Tp )

In order to have identical propagation delays, the width-to-length ratio of the p-


channel pull-up must be twice that of the n-channel driver, in order to compensate
for the lower hole mobility in the channel.

EECS 105 Fall 1998 EECS 105 Fall 1998


Lecture 17 Lecture 17
Power Dissipation Power (cont.)

■ Energy from power supply needed to charge up the capacitor: ■ Practical numbers: CL = 50 fF, f = 200 MHz, V+ = 3 V, Ngates = 5 x 105
+ 2
∫V
+ + P = 45 W ! (note that the real average depends on the average number switching
E charge = i(t)dt = V Q = ( V ) ( C G + C P )
per clock cycle)

Comparing Technologies -- the power-delay product


■ Energy stored in the capacitor:
+ 2
* Logic families are often compared by considering the product of the dynamic
E store =  --- ( C G + C P ) ( V )
1
 2 power dissipation and the propagation delay:

 + 
 + 2  ( C L + C p ) ( V ⁄ 2 ) 
■ Energy lost in p-channel MOSFET during charging: PDP = Pt P ≅  ( C L + C p ) ( V ) f  -------------------------------------------- 
2
  1 --- k ( V – V Tn ) 
+
+ 2  2 N 
E diss = E charge + E store =  --- ( C G + C P ) ( V )
1
2
where V+ has been substituted for VOH to achieve a more universal result.
During discharge, the n-channel MOSFET driver dissipates an identical amount * For V+ >> VTn,
of energy. If the charge/discharge cycle is repeated f times/second, where f is the 2 +
( CL + Cp ) V f
clock frequency, the dynamic power dissipation is: PDP ≅ -------------------------------------
kN

+ 2
P = ( 2E diss ) ⋅ f = ( C G + C P ) ( V ) f

In practice, many gates don’t change state every clock cycle, which lowers the
power dissipation
■ Additional source of dissipation: power flow from V+ to ground when both
transistors are saturated. Can be significant, but hard to estimate by hand.
Typical number: 25% of dynamic power dissipation.

EECS 105 Fall 1998 EECS 105 Fall 1998


Lecture 17 Lecture 17
CMOS Static Logic Gates CMOS NAND Gate

■ “Static” -- logic levels remain valid so long as power is supplied ■ Qualitative description
■ NOR and NAND gates Find transfer curve for case where VA = VB and both transition from 0 to 5 V

VDD ■ Transistors M1 and M2 are in series and have the same current; however, they do
not have the same gate-source bias
M4

A
B M3 VDD

+
VM M3 M4 ID
A M1 B M2 VOUT
_ VM

VM M2 VGS1 = VM
(a)
+
VDD VGS2 = VM − VDS1
M1 VDS1 ID1 = ID2

A M3 M4 VDS
(a) (b)
A
+
B
B M2 VOUT
_

M1

(b)

EECS 105 Fall 1998 EECS 105 Fall 1998


Lecture 17 Lecture 17
MOSFETs in Series MOSFETs in Series (Cont.)

■ Transistors M1 and M2 are “in series” with the same gate voltage, for the case ■ At VA = VB = VM, the cross section through M1 - M2 is:

,,,,,,
where the inputs are tied together (A = B)
VM
VOUT VM

,, ,,
gate gate

,,,,
,, ,,
M1 M2
source drain
n+
L1 L2
(a)
VM

M1 VM

,, ,,
gate gate
M1 M2
source drain

L1 L2
(b)
VA = VB

■ Transistor M1 is in triode and M2 is saturated. From the cross section, the drain
M2 of M1/ source of M2 can be eliminated without affecting anything --> the two
MOSFETs can be merged into a composite transistor with L1 + L2 = 2 Ln
■ Solving for VM for the case where VA = VB (note that the two p-channel devices
are in parallel and have an effective width of W3 + W4 = 2 Wp

ground 2k p kp
V Tn + ------------ ( V DD + V Tp ) V Tn + 2 ----- ( V DD + V Tp )
kn ⁄ 2 kn
V M = ----------------------------------------------------------------- = --------------------------------------------------------------
drain current is the same through each device ... what is the effective value of 2k p kp
1 + ------------ 1 + 2 -----
kP? kn ⁄ 2 kn

where kn = µnCox (Wn/Ln) and kp = µpCox (Wp/Lp)

We could optimize VM = VDD/2, but there is another switching condition to consider

EECS 105 Fall 1998 EECS 105 Fall 1998


Lecture 17 Lecture 17