2892
11, NOVEMBER 2010
Modeling and Simulation of Charge-Pumping
Characteristics for LDD-MOSFET
Devices With LOCOS Isolation
Hakim Tahi, Boualem Djezzar, and Bacharia Nadji
Abstract—We propose a model for the so-called constant-
amplitude charge-pumping (CP) characteristics, giving the Elliot
Gaussian-like CP current curve (ICP –VL ) of lightly doped drain
(LDD) MOSFET with local oxidation of silicon (LOCOS). This
method is based on modulation of the contributing active-channel
area (AG ) to the ICP –VL curve, depending on the position of
the high and low levels of the gate signal voltage. In addition, it
allows to separate and clarify the contribution of all MOSFET
regions (such as the effective channel, LDD, LOCOS, and LDD
subdiffusion under the LOCOS) to the amount of ICP –VL curves.
We have simulated this model and compared with experimental
CP data. The model shows a very good correlation with exper-
imental ICP –VL curves, particularly for transistors with short
channel gate lengths (LG ≤ 1 µm). However, as the channel gate
length increases, the model matches only for rising and falling
ICP –VL curve edges, corresponding to the contribution of LDD
and LOCOS regions, respectively. Moreover, we have demon-
strated that the deviation, which was observed between the CP
model and experimental data at the maximum plateau of ICP –VL
characteristics, depends on the gate pulse fall time and vanishes
for large fall time. This difference has been found to behave like a
geometric component, since it depends on gate length and fall time
and disappears for both short gate lengths and long fall times.
Index Terms—Charge pumping (CP), lightly doped drain
(LDD), local oxidation of silicon (LOCOS).
I. I NTRODUCTION
D UE TO its accuracy and sensitivity, the charge-pumping
(CP) technique [1] is extensively used to characterize
the MOSFET Si/SiO2 interface. Different CP variants have
been proposed in the literature to extract interface-, oxide-,
and border-trap densities and their energy distributions [2]–[5].
In fact, the CP technique has been used to study many MOSFET
reliability issues, such as radiation [6], [7], hot carrier [8], [9],
Manuscript received April 18, 2010; revised June 28, 2010; accepted
August 2, 2010. Date of publication September 20, 2010; date of current version
November 5, 2010. This work was supported by the High School Educational
and Scientific Research Ministry of Algeria under the National Funding of
Research. The review of this paper was arranged by Editor H. S. Momose.
H. Tahi and B. Djezzar are with the Microelectronics and Nanotech-
nology Division, Centre de Développement des Technologies Avancées
(CDTA), Algiers 16303, Algeria (e-mail: htahi@cdta.dz; hakimtahi@yahoo.fr;
bdjezzar@cdta.dz; b_djezzar@yahoo.fr).
B. Nadji is with the Microelectroncs et microsystems Laboratory, Dé-
partement d’Automatisation et Electrification Laboratoire d’Electrification
des Entreprises Industrielles, Université M’hamed Bougara de Boumerdès,
Boumerdès 35000, Algeria (e-mail: b_nadji@yahoo.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2010.2068300
0018-9383/$26.00 © 2010 IEEE
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO.
and bias temperature instability (BTI) [10], [11]. These in-
vestigations generally assume that the trap densities, which
are given by CP and its variants from maximum CP current
(ICPmax ), are uniform in the whole active channel area of the
transistor. Unfortunately, this assumption is not experimentally
valid, particularly for a small lightly doped drain (LDD) device
with field oxide isolation, where edge effects become signif-
icant [12]–[14]. Recently, it has been shown that LDD and
local oxidation of silicon (LOCOS) regions pollute the ICPmax
of the main effective channel [15]–[17]. These papers clearly
demonstrate the contribution of different active channel regions
in the ICP –VL characteristics. They propose an experimental
methodology to separate the main effective channel CP current
from the remainder CP current region for radiation-induced
traps in MOSFET. However, these methods need at least three
transistors and do not give CP components of LDD and LOCOS
regions, separately. In addition, the unknown contribution of
each region leads to unambiguous understanding of radiation
and BTI effects and subsequently conducts to unreliable mod-
els. Therefore, care has to be taken to distinguish between
the LDD-CP, LOCOS-CP, and geometric-CP components to
develop a reliable model for radiation and BTI effects. There-
fore, it is important to determine the amount of CP curve by
modeling the individual contribution of each MOSFET part.
In this paper, we deeply investigate the different regions of
LDD-MOSFET with LOCOS isolation. An empirical model
for LOCOS-CP, LDD-CP, and effective channel CP is devel-
oped and simulated to obtain the whole experimental ICP –VL
characteristic. Basically, the model employs the modulation
of the contributing active-channel area, which depends on the
position of the high and low level of the gate signal. The
approach used for this model is explicit and accurate, giving
a good correlation between simulated model and experimental
results mostly for short channel length. However, as the channel
increases, the geometric component starts to play an important
role. Because of limitation on the paper’s length, this point will
be investigated in another paper.
This paper is outlined as follows. Section II describes sim-
ulation and experiment tools. Model derivation is the subject
of Section III. In Section IV, we analyze the simulation results
of the Elliot Gaussian-like ICP –VL curve of LDD MOSFET
with LOCOS isolation and the individual CP curve associated
with different regions. The simulated results are compared
and discussed regarding the experimental data in Section V.
Conclusions are drawn in Section VI.
TAHI et al.: MODELING AND SIMULATION OF CP CHARACTERISTICS FOR LDD-MOSFET 2893

II. E XPERIMENT AND S IMULATION D ESCRIPTIONS

This work has been carried out using both simulation and
experiment tools. We simulated MOS transistors using 1-μm
LDD-CMOS process flow with LOCOS isolation developed
at the Institute for Silicon Technology, Fraunhofer, Germany,
by means of Athena of SILVACO TCAD software [18]. The
process is a dual-layer metal LDD-CMOS twin-well technol-
ogy on a P-type 12-μm epilayer on silicon-100-substrate with
a 20-nm-thick gate-oxide layer grown in dry O2 . The gate
capacitance per unit area Cox is about 2.23 × 10−7 F cm−2 . The
devices are isolated by LOCOS with a field oxide of 850 nm.
To extract threshold voltage (Vth ) and flatband voltage (Vfb )
distributions of the different MOSFET regions, we performed
electrical simulation of the MOSFET structure using Atlas
software [19]. The CP curve of the different channel regions
is modeled using Vth and Vfb distributions along the X- and
Y -directions. Altogether, the transistor CP current is the in-
tegral of all participating channel areas. These regions are
subdivided using 3D-TONYPLOT software [20].
The experiment CP data are obtained from LDD NMOSFET.
The transistors used in our experiments are nonpackaged and
have different gate lengths and widths. The standard Elliot
Fig. 1. Schematic illustration of the different channel regions. Channel-
ICP –VL curves were extracted using a trapezoidal signal with Eff is the effective channel area region. LDD-Sub is the LDD subdiffusion
an amplitude ΔVG of 4 V, varied rise (tr ) and fall (tf ) times beneath the polysilicon gate region. LOCOS-Eff is the LOCOS located near
from 4 to 500 ns, and frequency of 1 MHz. The low voltage the effective channel area region. LOCOS-LDD is the LDD subdiffusion under
the LOCOS region.
of the gate pulse VL was varied from −6 to 2 V. The measure-
ments were performed at 25 ◦ C using a fully automated bench
including a sensitive Keithley 617 electrometer, Keithley 3940 additional regions for CP, the rising VL ejects area from CP.
multifunction synthesizer, and Karl Suss PA300 micromanipu- Consequently, the constant-amplitude CP technique probes a
lator probe station. fraction of the channel area AG , which depends on the position
of the high and low level of the gate signal. For a given gate
amplitude ΔVG , the total area that contributes to CP current
III. M ODEL D ERIVATION can be expressed as
First, let us analyze the threshold voltage in MOSFET. The
classical Vth is defined as the necessary gate voltage that AG (VL , VH ) = W (VL , VH ) • L(VL , VH ) (2)
guarantees the inversion of the whole channel area of the
device. However, Vth in CP measurement is solely dependent where AG is the gate area, W (VL , VH ) is the active-CP gate
on the local carrier concentration. The latter can change along width, and L(VL , VH ) is the active-CP gate length. It is obvi-
the channel due to nonuniform doping in the transistor, which ously clear that the CP area is dependent on the position of VL
creates local variations of Vth and Vfb . In fact, the CP − Vth in and VH .
n-channel devices is defined as the gate–source and gate–drain Using SILVACO TCAD simulation, Tahi et al. [16] have
voltage that induces sufficient surface minority carrier concen- demonstrated that there are four regions in the channel that
tration (Cs ) to fill traps during tH . An analogous definition can contribute to CP current. Fig. 1 schematically shows the
can be introduced for CP − Vfb . Therefore, the surface carrier different channel regions of the simulated structure. Region one
concentration is given by is the effective channel area (Channel-Eff), region two is the
LDD subdiffusion beneath the poly-silicon gate (LDD-Sub), re-
 −1 gion three is the LOCOS located near the effective channel area
Cs = vth σn(p) tH(L) (1) (LOCOS-Eff), and region four is the LDD subdiffusion under
LOCOS (LOCOS-LDD). The latter is estimated by simulation
where σn(p) is the capture cross section for electrons (holes), of about 0.1 × 0.1 μm2 .
and vth is the thermal carrier velocity. (tH(L) ) is the gate In addition, the proposed CP model is limited to the traps
top (bottom) level. More details on Vth and Vfb distributions located at the interface. We assume that traps located in the
along the LDD-MOSFET channel length regions, obtained by silicon dioxide do not participate in CP because the frequency
SILVACO TCAD simulation, are given in [16] and [17]. signal measurement is 1 MHz. Therefore, there is no CP process
In a constant-amplitude CP technique, both Vth and Vfb in the Z-direction. According to the preceding analysis, the
voltages are probed at the same measurement; consequently, general CP current equation can be written as (3) shown at the
the contributing area changes. While the rising VH opens up bottom of the next page.
2894 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 11, NOVEMBER 2010

Considering that the interface traps and the filling factor of

the traps ΔF are distributed uniformly in energy and nonuni-
formly in space, we can write
En
Nit (x, y) = Dit (x, y, E)dE. (4)
Ep

Thus, (3), shown at the bottom of the page, becomes

 
ICP = q.f ΔF (x, y)Nit (x, y, )dxdy (5)
W (VL ,VH ) L(VL ,VH )

where q(C) is the electron charge, and Dit (in per square
centimeters per electronvolt) and Nit (in per square centime-
ters) are the trap densities. The Ep and Ee are the lower Fig. 2. Illustration of the Vth and Vfb CP distribution in the X- and
and upper boundaries of the active-CP energy interval. They Y -directions in the channel.
are equal to the nonsteady-state emission levels for holes and
According to the simulated LDD-NMOSFET structure given
electrons, respectively [2]. ΔF gives the probability that the
in [16] and illustrated in Fig. 1, (5) can be expressed as
trap at (x, y, E) contributes to CP current [21], [22]. From the  
Shockley–Read–Hall statistics and by neglecting the emission ICP = qf ΔF C (x, y)NitC dxdy
of carriers, the evolution with time and space of the filling factor
WG LEFF (VL ,VH )
ΔF of an interface trap situated at an energy E in the silicon  
bandgap during one cycle can be expressed as a function of + 2qf ΔF LDD (x, y)NitLDD dxdy
channel position by WG ΔL(VL ,VH )
 
ΔF (x, y) + 2qf ΔF LOCOS (x, y)
(1−exp(−cp (x, y)Tacc (x, y))(1−exp(−cn (x, y)Tinv (x, y)) ΔW (VL ,VH ) LEFF (VL ,VH )
=
1−exp−cn (x, y)Tinv (x, y)−(cp (x, y)Tacc (x, y) × LOCOS
Nit dxdy 
(6) + 4qf ΔF LOCOS−LDD (x, y)
ΔW (VL ,VH ) ΔL(VL ,VH )
where cp (x, y) and cn (x, y) are the capture rate of hole and
electron as a function of channel position (x, y). Tinv (x, y) and × NitLOCOS−LDD dxdy (9)
Tacc (x, y) are the inversion and accumulation times, respec- where LEFF (VL , VH ) is the effective channel length, WG is
tively. Contrary to ΔF given by Bouza et al. [21], in our model, the gate width, ΔL(VL , VH ) is the LDD subdiffusion length
both cp(n) (x, y) and Tacc(inv) (x, y) are varied as a function of under the poly-silicon gate, and ΔW (VL , VH ) is the width of
position (x, y) in the channel due to the nonuniform doping the LOCOS edge. NitC , NitLDD , NitLOCOS , and NitLDD−LOCOS
in the channel. Consequently, we can express Tinv (x, y) and are the interface trap densities in the Channel-Eff, LDD-sub,
Tacc (x, y) as a function of the local Vth and Vfb , respectively, LOCOS-Eff, and LOCOS-LDD regions, respectively.
as (see Fig. 2) In the constant-amplitude CP technique, the CP current is
[(VL + ΔVG − Vth (x, y)] probed from different regions at the same time, depending
Tinv (VL , x, y) = TH + (tr + tf ) on Vth (x, y) and Vfb (x, y) distributions. Therefore, (9) can be
ΔVG
(7) expressed as
[(Vfb (x, y) − VL ] ICP = qf NitC WG LEFF (VL , VH )ΔF C (VL , VH )
Tacc (VL , x, y) = TL + (tr + tf ) (8)
ΔVG + 2qf NitLDD WG ΔL(VL , VH )ΔF LDD (VL , VH )
where TH , TL , tr , and tf are the time high level, time low level, + 2qf NitLOCOS ΔW (VL , VH )LEFF (VL , VH )
rise time, and fall time gate pulse, respectively. Vth (x, y) and × ΔF LOCOS (VL , VH )
Vfb (x, y) are the threshold and flatband voltage distributions in + 4qf NitLOCOS−LDD ΔW (VL , VH )ΔL(VL , VH )
the channel. × ΔF LOCOS−LDD (VL , VH ). (10)

⎡ ⎤
  En
⎢ ⎥
ICP = q.f ⎣ ΔF (x, y, E)Dit (x, y, E)dE ⎦ dxdy (3)
active width active length Ep
TAHI et al.: MODELING AND SIMULATION OF CP CHARACTERISTICS FOR LDD-MOSFET
C , N LDD , and N LOCOS .
Fig. 3. Illustration of interface trap densities Nit
it
Extraction from experimental CP curve.
To compute the CP current versus VL , first, we extracted
Vth (x, y) and Vfb (x, y) distributions by SILVACO simulation
to define the CP active area for each region and to calculate
the trap filling factor ΔF . Then, we estimated the interface
trap densities for each region from experimental CP curves.
After that, we calculated the CP current for each region. Finally,
the total CP current of LDD-MOSFET with LOCOS isolation
is computed by adding all region CP currents. We note here
that the SILVACO tool has not been used to directly simulate
the ICP –VL curve, but it is only used to extract the Vth (x, y)
and Vfb (x, y) distributions along the gate area to identify the
CP active area and calculate ΔF . ICP –VL can be calculated
using any other programming tool (for example, in our case,
MATLAB tool).
IV. S IMULATION OF LDD-NMOSFET W ITH LOCOS
I SOLATION ICP –VL C HARACTERISTICS
In the first step of this paper, we have simulated the ICP –VL
characteristics of LDD N-MOSFET with WG /LG = 10/1 us-
ing the model described in Section III. Both detailed process
and experimental CP measurements are given in previous pa-
pers [15]–[17].
A. NitC , NitLDD , NitLOCOS , and NitLDD−LOCOS Extraction
To compute the CP characteristics of each region, we have
extracted NitC , NitLDD , and NitLOCOS densities from experi-
mental CP using three CP current values taken from regions
(A), (C), and (E), as shown in Fig. 3. More details on these
regions are given in earlier papers [16], [17]. The CP current
component of the LDD-LOCOS region is negligible because
⎧
⎪
⎪ Region(A) → ICP
LDD
= 2qf NitLDD WG ΔL(VL , VH )ΔF LDD (VL , VH )
⎨
Region(C) → ICP = qf NitC WG LEFF (VL , VH )ΔF c (VL , VH ) + 2qf NitLDD WG ΔL(VL , VH )ΔF LDD (VL , VH )
C
⎪
⎪ +2qf NitLOCOS ΔW (VL , VH )LEFF (VL , VH )ΔF LOCOS (VL , VH )
⎩
Region(E) → ICP
LOCOS
= 2qf NitLOCOS LEFF (VL , VH )ΔW (VL , VH )ΔF LOCOS (VL , VH )
2895
it is less than the experimental leakage current (10−12 A). Its
area ΔW (VL , VH )ΔL(VL , VH ), is very small and found by
simulation to be equal to 0.01 μm2 [16]. We can consider
the trap density of this region NitLDD−LOCOS to be the same
as that of the LOCOS region NitLOCOS . Then, we can write
(11), shown at the bottom of the page. Solving (11) gives
1010 (cm−2 ), 1.02 × 1010 (cm−2 ), and 1.03 × 1011 (cm−2 )
for NitC , NitLDD , and NitLOCOS , respectively. The relatively
high density of the LOCOS region, as compared with the
other regions, is due to the LOCOS oxidation process that
generates a large number of point defects in the interfacial
area, which produces a Si/SiO2 interface of poor quality
[12], [23].
1) ICP –VL Curve Simulation in LOCOS-Eff Region: We
remind that Vth , which satisfies (1), is defined as the gate
it
voltage that accumulates electrons at the surface. The same
definition holds for Vfb . In our case, we have found a density
of 5.5 1014 (cm−3 ) for both electrons and holes.
To obtain Vth (x, y) and Vfb (x, y) spatial distribution in
the LOCOS edge region, we have divided this region (1 ×
0.1 μm2 ) into small area transistors of 1 × 0.01 μm2 (to result
in ten transistors, T1 to T10 ). All those transistors have the
same gate length and width but different oxide thickness Tox .
In the LOCOS region, the oxide thickness varies from 25 to
200 nm. Fig. 4 depicts the determination of Vth (x, y) and
Vfb (x, y) spatial distribution in the LOCOS region. Fig. 4(a)
shows an example of a polarized 3-D N-MOSFET structure,
simulated using Atlas; the dash dot line in the LOCOS re-
gion shows the position of the cut plan used to divide this
region using TONYPLOT 3-D software [20]. Fig. 4(b) and
(c) shows the electron spatial distribution of two transistors
T1 and T10 having gate oxide Tox of 25 and 200 nm, re-
spectively. The Vth (x, y) and Vfb (x, y) of these two transistors
are given in Fig. 4(d). Vth (x, y) is shifted downwards by
ΔVG = 4 V. Consequently, for a specified VL , the interface
area between Vth (x, y) and Vfb (x, y) curves determines the
region of the total capture of both electrons and holes. In
this region, the local variations of Vth (x, y) and Vfb (x, y)
are caused by nonuniform doping and nonuniform oxide
thickness.
The numerical computed CP characteristics of all LOCOS
region transistors (from T1 to T10 ) are given in logarithmic
scale in Fig. 5. The sum of these ICP –VL curves gives us the
LOCOS region ICP –VL curve. The tails observed on the rising
edge ICP –VL characteristics are due to the nonuniformity of
Vth and Vfb in the proximity of the LOCOS-LDD region, where
the doping profile changes dramatically at the vicinity of LDD
metallurgic junction in the LOCOS region. Fig. 6 gives the
simulated CP characteristic at LOCOS-Eff and in the LOCOS-
LDD regions.
(11)
2896 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 11, NOVEMBER 2010

Fig. 4. Determination of Vth (x, y) and Vfb (x, y) spatial distribution. (a) Cut plan in the LOCOS region. (b) and (c) Electron spatial distribution contour at cut
plan position. (d) Vth (x, y) and Vth (x, y) spatial distribution for two transistors. In (a), (b), and (c), the polarization conditions are gate voltage Vg = 0.4 V,
drain bulk, and source bulk voltage Vr = 0.1 V.

Fig. 6. Simulated ICP –VL characteristic of LOCOS edge and LDD-

Fig. 5. Calculated ICP –VL characteristic of the LOCOS region in logarith- subdiffusion under the LOCOS region. ΔVG = 4 V, and f = 1 MHz.
mic scale. T1 to T10 present the transistors in the divided LOCOS region.

on CP of LDD devices and explained by the LDD-Source and

B. ICP –VL Curve Simulation in LDD-Sub Region
Fig. 7(a) shows the simulated LDD-Sub region ICP –VL
curves, and Fig. 7(b) illustrates the doping spatial distribution in
this region. The LDD-Sub ICP –VL characteristic presents two
shape tails on the rising edge. Similar tails have been observed
LDD-Drain boundary regions and the LDD subdiffusion [24].
The CP in the LDD-Sub region shapes the rising side of the
total ICP –VL characteristic. The LOCOS region contribution
determines the falling side shape. This point is highlighted in
Section V.
TAHI et al.: MODELING AND SIMULATION OF CP CHARACTERISTICS FOR LDD-MOSFET
Fig. 7. (a) Simulated ICP –VL characteristic of LDD subdiffusion. (b) LDD
subdiffusion region doping contour. ΔVG = 4 V, and f = 1 MHz.
Fig. 8. Simulated ICP –VL characteristic of the effective channel. ΔVG =
4 V, and f = 1 MHz.
C. ICP –VL Curve Simulation in Channel-Eff Region
The simulated ICP –VL curve of the Channel-Eff region
is shown in Fig. 8. The shape of the rising side seems to
correspond to the LDD-Sub region. It is due to the Vth (x, y)
and Vfb (x, y) variations nearby the LDD-Sub region, as shown
in Fig. 2.
2897
V. C OMPARISON B ETWEEN C ALCULATED M ODEL AND
E XPERIMENTAL M EASUREMENTS , AND D ISCUSSION
In this section, we compare the calculated ICP –VL curve
of LDD-MOSFET with LOCOS isolation to the measured
ICP –VL curve data. Experimental CP curve extraction details
can be found in [16] and [17]. We assume that LDD and
LOCOS structures are the same in all transistors, since they are
produced simultaneously by the same process on the same chip
in the same production line. As a consequence, ΔL(VL , VH )
and ΔW (VL , VH ) are also similar for all transistors. The
same assumption can also be made concerning NitC , NitLDD ,
NitLOCOS , and NitLDD−LOCOS .
Before comparison between the calculated and measured
ICP –VL curves using the SILVACO software TCAD tool, we
verified and calibrated the electrical parameters (such as Vth ,
Cox , Idsat , etc.) as well as for the device and process parameters
(such as junction depth, lateral diffusion, etc.) to match sim-
ulation and measurement within tolerated standard deviation
process specifications given by the founder.
For all transistors, the simulated ICP –VL curves based on
the above-discussed model exhibit a good correlation in the
rising and falling edges of the experimental ICP –VL curve.
This is due to the fact that the LDD and LOCOS structures
are the same in all transistors. On the other hand, perfect
matching is found between measurements and model for tran-
sistor with WG /LG = 10/1. Fig. 9 gives the total simulated
ICP –VL with its model-based components and experimental CP
curve performed on LDD-NMOSFET with WG /LG = 10/1.
The curves are plotted in linear and logarithmic scale to indicate
the correlation. There is obviously a great similarity between
the simulated total CP curve and the experiment data for all
shaped parts. In addition, the contribution of different regions to
the total ICP –VL characteristic is illustrated on the same figure.
We can easily distinguish the participation of each region as
follows:
(A) −6 V < VL < −5.1 V Only the LDD-Sub region is
activated in the CP current.
(B) −5.1 V < VL < −4.55 V The LDD-Sub and LOCOS-
LDD regions contribute to the CP current.
(C) −4.55 V < VL < −4.15 V The Channel-Eff, LDD-
Sub, and LOCOS-LDD regions participate with the CP
current.
(D) −4.15 V < VL < −1.82 V The Channel-Eff, LDD-Sub,
LDD-LOCOS, and LOCOS-Eff regions are activated in
the CP current.
(E) −1.82 V < VL < −0.38 V The Channel-Eff and
LOCOS-Eff regions participate with the CP current.
(F) −0.38 V < VL < 0.6 V Only the LOCOS-Eff region
contributes to the CP current.
(G) VL > 0.6 V Leakage current.
It is worth to mention that this model allows us to compute
ICP –VL of the LOCOS-LDD region, where ICPmax is about
3 × 10−13 A. However, experimental measurement could not
capture this region in the ICP –VL amount because of the
leakage current (∼10-12 A).
2898
Fig. 9. Comparison between experimental and calculated ICP –VL characteristics of LDD-NMOSFET with WG /LG = 10/1. (a) Current in logarithmic scale.
(b) Current in linear scale. The CP conditions are: Vr = 0.1 V, ΔVG = 4 V, f = 1 MHz, tr = tf = 10 ns.
The rising edge of both experimental and total simulated
ICP –VL characteristics presents two tails. The first tail is just
under Vth of the effective channel and located in regions (B)
and (C) [see Fig. 9(a)]. The second tail is located in region
(A) and extends from the end of the first tail deeply toward the
negative bias. The same behavior has been reported by Habas
[24]. They are mainly caused by nonuniformity of doping
distribution across Channel-Eff/LDD-Sub and LDD regions,
respectively. The first tail only occurs in ICP –VL of the LDD
devices and has no equivalent in ICP –VL of the conventional
devices, and the second tail looks like the tail of the con-
ventional devices [24]. Indeed, Heremans et al. [25] reported
that the conventional device ICP –VL presents one current tail
for VL smaller than Vth − ΔVG . This tail was theoretically
calculated and compared with experiments [24], [25]. They
obviously found a very good correlation between calculated
and measured data. However, they did not include the LOCOS
edge effect in their calculations to evaluate the slope of the
falling side of the ICP –VL curves. Some authors [21], [22] have
found a similar ICP –VL calculation and experiment agreement
regarding the ICPmax at the interface and inside the oxide but
different ICP –VL rising and falling edges.
In this paper, not only the rising edge of the ICP –VL curve is
calculated, but also the falling edge by including the LOCOS
effect. This last part of ICP –VL presents a good correlation
with the experimental ICP –VL characteristics for all transistors.
It is influenced by doping nonuniformity and the variation
of oxide thickness in the LOCOS region (bird-beak oxide).
Nevertheless, our calculation model does not take into account
the CP at low frequencies to probe traps in the oxide. It would
be valuable to consider this point in a future work.
In contrast, Fig. 10 shows that ICPmax of the calculated
ICP –VL curves diverges from experiment data when the gate
length is increased. Fig. 10(a)–(d) shows plots for transistors
with WG /LG = 10/5 and WG /LG = 10/10 in log scale to
show that the tails (LOCOS side and LDD side) remain un-
changed and in linear scale to illustrate the vertical deviation
dependence on the gate length. The longer the gate length, the
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 11, NOVEMBER 2010
higher the difference. This divergence for gate length greater
than 1 μm is mainly caused by the CP of the Channel-Eff
region, since only this region varies with channel length. The
other regions are still unchanged since all transistors are fab-
ricated by the same process on the same chip in the same
production line.
To deeply investigate the origin of this discrepancy, we have
calculated and measured ICP –VL curves for transistors with
different gate sizes at different tf and tr . All ICP –VL curves
exhibit the same behavior with WG /LG and tf (tr ). In addition,
the ICP –VL curve edges are also the same for transistors with
10/0.75, 10/0.65, 10/0.55, 1/10, 5/10, and 2/10 (ICP –VL curves
not shown here). We plot in Fig. 11 the differences between
experimental and simulated ICPmax normalized with respect
to the gate area as a function of gate length and width. This
difference is equal to the leakage current for LG ≤ 1 μm but
exhibits a linear behavior in logarithmic scale for LG > 1 μm.
Moreover, Fig. 11 plainly shows that this difference does not
depend on the gate width. To better understand the origin of
this deviation, a thorough analysis on its time dependence has
been carried out. Fig. 12 shows the current differences as a
function of pulse fall time for different gate lengths and widths.
All time-dependent deviations reveal the same feature and are
identical with gate width but different with gate length. In
addition, this difference is independent of the pulse fall time for
1-μm gate-length transistor and equal to the leakage current.
In other terms, the calculated and simulated CP curves are
the same. All transistor curves tend to converge to the same
value as tf increases. They coincide at 500 ns, where the
deviation is about leakage current (∼10−12 A). This means
that the difference disappears and the calculated model matches
well the experiment for all transistors. According to the above
analysis, the deviation seems to have the same characteristics
as the geometric component regarding gate length and fall time
dependences [1], [2]. This is why we believe that the geometric
current is the origin of the model and measurement mismatch.
Care has to be taken for this component not to pollute the CP
current and cause overestimation when it is used to evaluate
TAHI et al.: MODELING AND SIMULATION OF CP CHARACTERISTICS FOR LDD-MOSFET 2899

Fig. 10. Comparison between experimental and calculated ICP –VL characteristics of LDD-NMOSFET. (a) and (b) LDD-NMOSFET with WG /LG = 10/5.
(c) and (d) LDD-NMOSFET with WG /LG = 10/10. The CP conditions are the same as in Fig. 9.

Fig. 12. Difference between experimental and calculated ICPmax as a func-

tion of fall time for different gate lengths (empty symbols) and widths (filled
Fig. 11. Difference between experimental and calculated ICPmax as a func- symbols).
tion of gate length (triangular symbol) and gate width (square symbol).

device reliability such as BTI and radiation effect. Because
of paper length, this issue will be separately analyzed and
addressed in next paper.
By computing each region CP current separately, the method
presented in this paper can help to deeply analyze the transistor
reliability, particularly the radiation- or BTI-induced traps in
different regions of the channel. This approach could be able to
provide more correct evaluation of BTI and radiation stresses,
subconsequently enabling to develop accurate models for de-
vice life time prediction.
In the future work, it would be beneficial to carry out analysis
on geometric current. We will complete this model by adding
this component and also show how it should be integrated with
different CP current regions.
2900 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 11, NOVEMBER 2010
VI. C ONCLUSION
In this paper, a modeling approach has been proposed to
analyze a CP characteristic of LDD-MOSFET with LOCOS
isolation. This approach is based on modulation of the con-
tributing active channel area (AG ) to the CP curve. Using this
model, we have found that the rising and falling edges of the CP
characteristic are due to the contribution of LDD subdiffusion
and LOCOS regions, respectively. The ICPmax is a result of the
contribution of the CP current of the effective channel, LDD
subdiffusion, and LOCOS regions.
This model has been implemented and compared against
experimental CP data. It is in perfect agreement with measure-
ments for transistors having short gate length (LG ≤ 1 μm).
For gate length greater than 1 μm, it only fits the rising and
falling CP curve edges but does not match data at maximum
plateau of the CP curve. Moreover, we have shown that this
deviation is strongly dependent on gate length and voltage
signal fall time. Indeed, the present model does not account
for the geometric current. This is why there are discrepancies
between the calculated model and measurements for transistors
with long gate length.
It should be noticed that this model presents a diagnostic tool
offering detailed information about interface trap distributions
with more comprehension of experimental CP data. For this
reason, this modeling approach has a significant application
and is appropriate for radiation and BTI estimation, where
interface trap density extraction of the actual channel needs
more attention for separating the effect of parasitic regions from
pure effective channel. For a more complete model, it should be
worthy to investigate the geometric component.
ACKNOWLEDGMENT
The authors would like to thank R. Serhane and F. H. Larbi
from DMN Division, CDTA, for their assistance with SILVACO
simulation.
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Hakim Tahi was born in Tizi Ouzou, Algeria,
on February 02, 1977. He received the Engineer
degree in electronics and the Master’s degree in
microelectronics from the University of Mouloud
Mammeri Tizi ouzou, Tizi Ouzou, in 2001 and 2005,
respectively.
Since 2007, he has been with the Microelectronics
and Nanotechnology Division, Centre de Développe-
ment des Technologies Avancées, Algiers, Algeria,
where he is currently a Researcher on the charac-
terization of interface and oxide trap induced by γ
radiation on the MOS devices using C–Vg , C-P, I–V , DTCP, DTBT, and OTCP
methods.
TAHI et al.: MODELING AND SIMULATION OF CP CHARACTERISTICS FOR LDD-MOSFET
Boualem Djezzar was born in Algiers, Algeria, on
December 3, 1965. He received the Diplôme des
Etudes Supérieures (DES) degree in solid-state phys-
ics from the University of Constantine, Constantine,
Algeria, the Diplome des Etudes Approfondies
(DEA) degree in microelectronics from the Univer-
sity of Grenoble, Grenoble, France, in 1991, and the
Master’s degree in thin film from the University of
Algiers, Algiers, in 2000.
From 1990 to 1992, he worked on thin-film depo-
sition under ultrahigh vacuum of rare earth (Erbium)
Silicide on Si (111) with the LEPES Laboratory, CNRS, Grenoble. Since
1992, he has been with the Microelectronics and Nanotechnology Division,
Centre de Développement des Technologies Avancées, Algiers. He worked on
the technological process simulation and modeling of CMOS, BiCMOS, and
CBiCMOS. In 1997, he started working with the Caracterisation des Dispositifs
à Semiconducteurs (CDS) Group on MOS device reliability and electrical
characterization of radiation-induced traps in silicon dioxide SiO2 and interface
Si/SiO2 in MOS devices. He is the author or coauthor of more than 40
papers published in refereed journal and refereed conference proceedings on
modeling/simulation devices and radiation effect on MOS devices. His current
research interests include CMOS technology reliability, particularly electrical
characterization and modeling of radiation and NBTI effects.
2901
Bacharia Nadji was born in Béchar, Algeria, in
1961. She received the “Ingénieur” degree in elec-
tronics from the University of Sidi Bel Abbes, Sidi
Bel Abbes, Algeria, in 1985 and the Ph.D. degree for
her work on anodic silicon oxide thin films from the
University Joseph Fourier de Grenoble, Grenoble,
France, in 1990.
From 1990 to 1992, she was a physics Teacher
with the University of Savoie Chambéry, Chambéry,
France. Since 1992, she has been teaching with
the University of M’Hamad Bougara, Boumerdes,
Algeria. In 2007, she became “maitre de conférences A” and has been the Head
of the Microelectronic and Microsystems Laboratory. She is also responsible
for the infotronic postgraduate. Her current research focuses on material and
device reliability.