Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap
Daubechies Filters
Tze-Yun Sung, Yaw-Shih Shieh and
Chun-Wang Yu
Department of Microelectronics Engineering
Chung Hua University
Hsinchu, Taiwan 30012
E-mail: bobsung@chu.edu.tw
Abstract
This paper proposes two architectures of 2 - 0
discrete wavelet transform (DWT) and inverse DWT
(ID WT). The first high-eficiency architecture
comprises a transform module, an address sequencer,
and a RAM module. The transform module has uniform
and regular structure, simple control jtow, and local
communication. The significant advantages of the
single transform module are full hardware-utilization
and low-power. The second architecture features
parallel and pipelined computation and high
throughput. Both architectures are very suitable for
VLSI implementation of new-generation image
coding/decoding systems, such as JPEG-2000. In the
realization of 2-D DWT/IDWT, we focus on a FPGA
and VLSI implementation using - t a p Daubechies
filters, which savespower and reduces chip area.
Ktywords: D WT/IDWT, low-power, image coding/
decoding system, JPEG-2000, 4-tap Daubechiesjlters,
multiplierless.
1. Introduction
In the field of digital image processing, the
JPEG-2000 standard uses the scalar wavelet transform
for image compression [I]; hence, the two-dimensional
(2-D) discrete wavelet transform (DWT)/inverse DWT
(IDWT) has recently been used as a powerful tool for
image codingldecoding systems. Two-dimensional
DWTIIDWT demands massive computations, hence, it
requires a parallel and pipelined architecture to
perform real-time or on-line video and image coding
and decoding, and to implement high-efficiency
application-specific integrated circuits (ASIC) or field
programmable gate array (FPGA). At the heart of the
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Parallel and Distributed Computing,Applications and Technologies (PDCAT'06)
0-7695-2736-1/06 $20.00 © 2006
Hsi-Chin Hsin
Department of Computer Science and
Information Engineering
National Formosa University
Hu- Wei, Taiwan 63208
E-mail: hsin@nfu.edu.tw
analysis stage of the system is the DWT. In the
synthesis stage, the inverse DWT recovers the original
image from the coefficients of DWT.
Cohen, Daubechies and Feauveau proposed
using Ctap Daubechies coefficients for lossy analysis
[I]. The symmetry of 4-tap Daubechies filters and the
fact that they are almost orthogonal [2] make them
good candidates for image analysis application. The
coefficients of the filter are quantized before hardware
implementation; hence, the multiplier can be replaced
by limited quantity of shift registers and adders. Thus,
the system hardware is saved, and the system
throughput is improved significantly.
In this paper, we proposed two high-efficiency
architectures for the even and odd parts of 1-D
decimated convolution. The advantages of the
proposed architectures are 100% hardware-utilization,
multiplierless, regular structure, simple control flow
and high scalability.
The remainder of the paper is organized as
follows. Section 2 presents the 2-D discrete wavelet
transform algorithm, and derives new mathematical
formulas. In Section 3, the high-efficiency architecture
for the 2-D DWT is proposed. In Section 4, the
high-efficiency and low-power architecture for the 2-D
IDWT is proposed. Section 5 applies the two proposed
2-D DWTIIDWT architectures to the coefficient
quantization scheme for FPGA and VLSI
implementation, and analyzes their performance.
Finally, comparison of performance between the
proposed architectures and previous works is made
with conclusions given in Section 6.
2. 2-D Discrete Wavelet Transform
Algorithm
 The 2-D DWT is a multilevel decomposition
technique. The mathematical formulas of 2-D DWT
are defined as follows:
K-I K-1
LLj(m,n) = y x l ( i ) - l ( k ) .LLiil (2m - i,2n - k ) (I)
i=O k=O
[K/2 1
LHLi (n)= d ( Q h ( 2 k ) -L a . (2n-2k)

K-l K-l
HL' (m,n ) = h(i) .l(i)- LL'-' (2m - i,2n - k ) (3)
i=O k=O

where 0 < n, m < N j , LL0 (m,n) is the input image,

K denotes the length of filter, [ ( i ) denote the impulse
responses of the low-pass filter, and h(k) denote the
impulse responses of the high-pass filter, which is
developed from ( K x K ) -tap filters, and
LLJ(m,n) , LHJ(m,n) , HL'(m,n) , and
HHJ(m,n) denote respectively the coefficients of
low-low, low-high, high-low and high-high subbands
produced at the decomposition levelj (also represented
by LL' , L H ~, HLJ , and H H ~). N j x N j denotes
samples of LLJ .
According to the mathematical formulas (I), (2),
(3) and (4), the decomposition is produced by four 2-D
convolutions followed by the decimation both in the
row and in the column dimension for each level. In the
three-level analysis for 2-D DWT, the data set LLJ-'
having N,-, x Nj-l samples is decomposed into four
subbands LLj ,LH j ,HLj , and HH' each having
N j x N j (equals to (Nj,/2)x(Nj,/2)) samples.
Let LLL(2n) , l(i)1(2k) , l(i)h(2k) , h(i)l(2k)
and h(i)h(2k) be I-D DWT consisting of the
even-numbered samples, and 0ln lN, ; is ( N l 2 )x ( N l 2 ) . At the second level, the input is the
0<k < K 12 .Moreover, let L L (2n ~ + 1) ,
l(i)1(2k+1) , l(i)h(2k+l) , h(i)1(2k+l) and
h(i)h(2k+l) be 1-D DWT consisting of the
odd-numbered samples, and 0 < n < N, ;0 < k K 12 .
~ L i , ~ (,nL) ~ i , ~ (,nH)L ; , ~ ( ~,and
) H H ; , ~ ( ~can
) be
expressed as follows:
[KIZFI
Hlf'. (n)= ch(i)h(2k) -L a . (21
-2k)
k=O
The above equations imply that LLLj ( n ) ,L H ~( n, )~,
HLAj(n) and H H j~( n ) can be computed as the sum
of two 1 -D convolutions performed independently on
the even part LL!&(2n -2k) and the odd part
3. The Proposed 2-DDWT Architecture
The proposed architecture performs parallel and
pipelined processing. Each analysis level involves two
stages: stage 1 performs row filtering, and stage 2
performs column filtering. In a one-level filter bank for
2-D DWT computation. At the first level, the size of
the input image is N x N , and the size of the output of
each of the three subbands LH, HL and HH
LL subband whose size is ( N / 2) x ( N / 2 ) , and the size
of the output of each of the three subbands LLLH,
LLHL and LLHH is ( N / 4 ) x ( N / 4). At the third level,
the input is the LLLL subband whose size
is ( N 14) x ( N / 4 ) , and the size of the output of each of
the four subbands LLLLLL, LLLLLH, LLLLHL and
LLLLHH is (N / 8) x ( N / 8) .
The coefficients of the low-pass filter and the
high-pass filter have been derived in the biorthogonal
917 wavelet [3].The coefficients are quantized before

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 hardware implementation. We assume that the
low-pass filter has four tapes: a, ,a,, a, and a,, and the
high-pass filter also has four tapes: bo ,bl ,b, and b, .
The vertical filter and the horizontal filter for 1-D
DWT are shown in Figure 1 and Figure 2, respectively.
According to Eqs. (5), (6), (7) and (8), each 1-D
decimated convolution can be computed as the
point-wise sum of two 1-D convolutions performed
independently. Figure 3 illustrates the transform
module for 2-D DWT, the splitter arranges the data of
the even and odd parts using processing element (PE). f
represents the input frequency, fl2 denotes that the
output frequency of L and H is a half of the input
frequency, andfl4 denotes that the output frequency of
LL, LH, HL and HH is a quarter of the input frequency.
The single transform module can perform 2-D DWT.
The single transform module comprises a ( N / 2 x N I 2 )
RAM, a transform module, a multiplex, a splitter and
an address sequencer. It requires 42 clock cycles to
perform the 2-D DWT transform. Clock cycles 0 to 31
perform the level-1 analysis, clock cycles 32 to 40
perform the level-2 analysis, and clock cycles 40 to 41
perform the level-3 analysis. Three transform modules
can be cascaded to perform parallel and pipelined
processing.
4. The Proposed 2-D IDWT Architecture
In the proposed architecture of three-level synthesis
for 2-1) DWT, each synthesis level involves two stages:
stage 1 performs column filtering, and stage 2 performs
row filtering. The horizontal filter and the vertical
filter for 1-D IDWT are shown in Figure 4 and Figure
5, respectively. Figure 6 illustrates the transform
module for 2-D IDWT. f denotes that the input
frequency of L and H i s a double of the input frequency,
and 4f denotes that the output frequency is four times
that of the input frequency of LL, LH, HL, and HH.
The single transform module comprises an inverse
transform module, a RAM module (N 12x N 12) and
a multiplexer. At the first-level composition, the
inverse transform module comprises the
(LL)~-,LL subband selected from the (LL)'-I LL
subband by the multiplexer, as well as the
(LL)~-'LH, (LL)~-IHL, and (LL)~-'HH
subbands obtained by the entropy decoder. The
(LL)~-'LL subband is stored in the RAM module. At
the second-level composition, the inverse transform
module comprises the (LL)jw3LL subband selected
from (LL)~-,LL subband by the multiplexer of the
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RAM module, as well as the (LL)'-* LH,
(LL)~-,HL, and (LL)~-,HH subbands obtained by the
entropy decoder. At the last-level composition, the
inverse transform module comprises the original image
selected from the LL subband by the multiplexer, as
well as the LH ,HL , and HH subbands obtained by the
entropy decoder. It requires 22 clock cycles to perform
the 2-D IDWT transform. Clock cycles 0 to 1 perform
the level-1 synthesis, clock cycles 2 to 9 perform the
level-2 synthesis, and clock cycles 10 to 41 perform
the level3 synthesis.
5. Hardware Implementation and
Performance Analysis of the Proposed 2-D
DWTDDWT Architectures
Filter coefficients of 4-tap Daubechies low-pass
filter are quantized before implementation in the
high-speed computation hardware [17]-[18]. In the
proposed architectures, all multiplications are
performed using shifts and additions after
approximating the coefficients as a booth binary
recoded format. The multiplier is replaced by a
carry-save-adder (CSA), an adder and three hardwire
shifters in processing element (PE).
The hardware codes were written in
Verilog-hardware description Language (HDL) [5]
evaluated under ModelSim simulation tool [6]. The
architectures were synthesized by Xilinx FPGA
express tools [7] and evaluated on the Xilinx
XC2V4000 FPGA platform [8]. They were designed to
evaluate the hardware and to provide an embedded
core for digital image data analysis and synthesis [9].
The decimation filter for 1-D DWT requires
eight adders, thirteen shiflers and three registers for
each PE, while that for the 1-D IDWT requires seven
adders, thirty shifters and three registers for each PE.
Both hardwares are very cost-effective. They require
three and two additions to perform each PE
computation in DWT and IDWT, respectively. The two
architectures reduce power dissipation by m compared
with conventional architectures in m-bit operand
(low-power utilization).
Two proposed DWT and IDWT architectures
have regular structure, local communication and simple
control flow, so they are very suitable for VLSI
implementation and scalable filter length. In both of
the single transform modules, the hardware utilization
are loo%, so the systems consumes ultra-low power.
The total data processing time of 2-D DWT can be
calculated as follows:

I
where j = log2 N .
In the single transform module of 2-D IDWT, the
total data processing time is the same as that of 2-D
DWT.
Two architectures with fixed point operation
applying on 3-level image compression and
decompression by periodic extension methods [17], the
peak-signal-to-noise ratios (PSNR) of the reconstructed
image is 255.5dB. The 3-level compressed image using
periodic extension method is shown in Figure 7. The
original image and reconstructed image are shown in
Figure 8. Hence, the performances of the proposed 2-D
DWTIIDWT architectures are suited for PEG-2000
and motion-JPEG-2000.
6. Discussion and Conclusion
In this paper, two high-speed and ultra low-power
architectures for 2-D DWT and IDWT with single
transform modules have been proposed. Both
architectures perform analysis in 2 . (1 - 2-2i). N~ I 3
processing time and synthesis in 2 . (1 - 2-2i). N~ I 3 .
They are significantly faster than conventional
architectures proposed by Wu and Chen [lo]-[l I], and
Marino [12]. Table 1 depicts the comparison with
previous works. In this table, AT^ represents the
system performance [Ill-[15], where A denotes area
and T denotes time or latency (clock cycles). As can be
seen, the system performances of the two proposed
architectures are significantly better than that of
previous works.
Filter coefficients are quantized before
implementation using 4-tap Daubechies filters. Both
hardwares are cost-effective and the systems have
high-speed. The architectures reduce power dissipation
by m compared with conventional architectures in
m-bit operand (low-power utilization).
The proposed architectures have been verified by
Verilog-HDL and implemented on FPGA. The
advantages of the proposed architectures are 100%
hardware utilization and ultra low-power. The
architectures have regular structure, simple control
flow, high throughput and high scalability. Thus, they
are very suitable for new-generation image
codingldecoding systems, such as PEG-2000.
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L-Line delay register

Figure 2. The Horizontal filter for 1-D DWT

1
input -
Figure 1. The vertical filter for I-D DWT

Figure 4. The Horizontal filter for 1-D IDWT

Figure 7. The 3-level compressed image

Figure 5. The vertical filter for 1-D IDWT

(a) Ib)
Figure 8. (a) Original image and @)
Reconstructed image

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 Figure 6 . The transform module for 1-D IDWT

Figure 3. The transform module for 1-D DWT

Table 1. Comparison with the previous works ( j = log, N )

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