A NINE-LEVEL INVERTER USING ONE VOLTAGE SOURCE AND
REDUCED COMPONENTS USING CAPACITOR BALANCING
TECHNIQUE
Mr.S.Balamurugan
Assistant professor
Dept of Electrical and Electronics Engineering
Alagappa Chettiar Government College of
Engineering and Technology
Karaikudi
ABSTRACT
In this project, a new method of
nine-level inverter is proposed. The
inverter employs only one input source and
reduced number of switches. Instead of
using many voltage sources, four
capacitors is used. Lower total harmonic
distortion can be obtained with sinusoidal
pulse width modulation methods. In this
method capacitors are naturally balanced
by its arrangement. In previous years Multi
level inverters using more than one voltage
source and power devices and also the size
of the device is also large. The voltage
stress on power devices is relatively
reduced, which increases its range of
applications also. Self voltage balancing
ability of the capacitors is used in this nine
level inverter is the main advantage of this
project. By using this proposed
methodology nine levels in the output is
obtained. The theoretical analysis,
comparison with the existing methods and
simulation results of the proposed nine-
level inverter is also done.
INTRODUCTION
Basically Inverter is a device that
converts DC power to AC power at desired
output voltage because of other advantages
such as high power quality, lower order
harmonics, lower switching losses, and
N.Gautham Sharma
PG Student
Power Electronics and drives
Alagappa Chettiar Government College of
Engineering and Technology
Karaikudi
better electromagnetic interference, and
frequency. Demerits of inverters are less
efficiency, high cost, and high switching
losses. To overcome these demerits, were
going to the multilevel inverter topologies.
Multilevel inverter output voltage produce
a staircase output waveform, this
waveform look like a sinusoidal
waveform. The multilevel inverter output
voltage having less number of harmonics
compare to the conventional bipolar
inverter output voltage. If the multilevel
inverter output increase to N level, the
harmonics reduced to the output voltage
value to zero. The multilevel inverters are
mainly classified as Diode clamped Flying
capacitor inverter and cascaded multi level
inverter. The most attractive features of
multilevel inverters are as follows.
 They can generate output voltages
with extremely low distortion and
lower order harmonics.
 They draw input current with very
low distortion.
 They can operate with a less
switching frequency.
Multilevel inverter output voltage produce
a staircase output waveform, this
waveform look like a sinusoidal
waveform. The multilevel inverter output
voltage having less number of harmonics
compare to the conventional bipolar
inverter output voltage. If the multilevel
inverter output increase to N level, the
harmonics reduced to the output voltage
value to zero.
Cascaded H-bridge topology has
simple circuit and easy to understand. A
multilevel inverter has four main
advantages over the conventional bipolar
inverter. First, the voltage stress on each
switch is decreased due to series
connection of the switches. Therefore, the
rated voltage and consequently the total
power of the inverter could be safely
increased. Second, the rate of change of
voltage (dv/dt) is decreased due to the
lower voltage swing of each switching
cycle. Third, harmonic distortion is
reduced due to more output levels.
Fourth, lower acoustic noise and
electromagnetic interference (EMI) is
obtained.
The features of multilevel cascade is given
by
 It is much more suitable to high-
voltage, high-power applications
than the conventional inverters.
 It switches each device only once
per line cycle and generates a
multistep staircase voltage
waveform approaching a pure
sinusoidal output voltage by
increasing the number of levels.
MODULATION TECHNIQUES FOR
MULTILEVEL INVERTER
Mainly the power electronic
converters are operated in the “switched
mode”. This means the switches within the
converter are always in either one of the
two states - turned off or turned on. Any
operation in the linear region, other than
for the unavoidable transition from
conducting to non -conducting, makes an
undesirable loss of efficiency and an
unbearable rise in switching power
dissipation. To control the flow of power
in the converter, the switches alternate
between these two states. This happens
rapidly enough that the inductors and
capacitors at the input and output
nodes of the converter average or filter
the switched signal. The switched
component is attenuated and the desired dc
or low frequency ac component is retained.
This process is called Pulse Width
Modulation, since the desired average
value is controlled by modulating the
width of the pulses.
The fundamental methods of pulse-
width modulation are divided into the
traditional voltage-source and current-
regulated methods. Voltage-source
methods more easily lend themselves to
digital signal processor or programmable
logic device implementation.
CLASSIFICATION OF MULTILEVEL
INVERTER CONTROL SCHEMES
Fig.1.Modulation Methods
PROPOSED NINE-LEVEL INVERTER
TOPOLOGY
Fig.2.Block Diagram of proposed system
The nine-level inverter employing
one voltage source and two capacitors is
implemented. The number of switches used
is also reduced. Capacitor balancing
technique is involved instead of using two or
more voltage sources. In this proposed
system capacitor natural balancing technique
is used. Lower THD of output voltage is
obtained and the voltage stress on the power
switches in the back-stage is relatively
relieved. It makes full use of the conversion
of series and parallel connections of one
voltage source and two capacitors to realize
nine output levels.
CIRCUIT TOPOLOGY
Fig.3.Proposed Single-Phase Nine-Level
Inverter
It comprises a single-phase
conventional H-bridge inverter, three
bidirectional switches, and a capacitor
voltage divider formed by C1, C2,C3 and
C4,as shown in figure. The modified H-
bridge topology is significantly
advantageous over other topologies, i.e.,
less power switch, power diodes, and less
capacitor for inverters of the same number
of levels. The power generated by the
inverter can be used for any usage.
Proper switching of the inverter can
produce nine output-voltage-levels (Vdc,
3Vdc/4, Vdc/2, Vdc/4, 0,,Vdc/4, Vdc/2, -
3Vdc/4,- Vdc) from the dc supply voltage.
The proposed inverter’s operation can be
divided into nine switching states. The
required nine levels of output voltage were
generated as follows:
OPERATION OF NINE LEVELS
Maximum positive output (Vdc): S1 is
ON, connecting theload positive terminal to
Vdc, and S4 is ON, connecting the load
negative terminal to ground. All other
controlled switches are OFF; the voltage
applied to the load terminals is Vdc.
Three-fourth positive output (3Vdc/4):
The bi-directional switch S5 is ON,
connecting the load positive terminal, and
S4 is ON, connecting the load negative
terminal to ground. All other controlled
switches are OFF; the voltage applied to the
load terminals is 3Vdc/4.
Half of the positive output (Vdc/2): The
bidirectional switch S6 is ON, connecting
the load positive terminal, and S4 is ON,
connecting the load negative terminal to
round. All other controlled switches are
OFF; the voltage applied to the load
terminals is Vdc/2.
One-fourth of the positive output
(Vdc/4): The bidirectional switch S7 is ON,
connecting the load positive terminal, and Table shows the switching combinations
S4 is ON, connecting the load negative that generated the nine output-voltage
terminal to ground. All other controlled levels are (Vdc, 3Vdc/4, Vdc/2, Vdc/4,0,
switches are OFF; the voltage applied to the Vdc/4, Vdc/2, -3Vdc/4,-Vdc)
load terminals is Vdc/4.
V0 S1 S2 S3 S4 S5 S6 S7
Zero output: This level can be produced Vdc ON OFF OFF ON OFF OFF OFF
by two switching combinations; switches 3Vdc/4 OFF OFF OFF ON ON OFF OFF
S3 and S4 are ON, or S1 andS2are ON, and Vdc/2 OFF OFF OFF ON OFF ON OFF
all other controlled switches are OFF; Vdc/4 OFF OFF OFF ON OFF OFF ON
terminal ab is a short circuit, and the 0 ON ON OFF OFF OFF OFF OFF
voltage applied to theload terminals is zero. -Vdc/4 OFF ON OFF OFF ON OFF OFF
One-fourth negative output (−Vdc/4): -Vdc/2 OFF ON OFF OFF OFF ON OFF
The bidirectional switch S5 is ON, -3Vdc/4 OFF ON OFF OFF OFF OFF ON
connecting the load positive terminal, and -Vdc OFF ON ON OFF OFF OFF OFF
S2 is ON, connecting the load negative
terminal toVdc. All other controlled Table.1.Switching Sequence For The
switches are OFF; the voltageapplied to the Output Voltage
load terminals is −Vdc/4.
Forward current path at level Vdc/2
Half of the negative output (−Vdc/2): The
bidirectional switch S6 is ON, connecting
the load positive terminal, and S2 is ON,
connecting the load negative terminal to
ground. All other controlled switches are
OFF; the voltage applied to the load
terminals is −Vdc/2.

Three-fourth negative output (−3Vdc/4):

The bidirectional switch S7 is ON,
connecting the load positive terminal, and
S2 is ON, connecting the load negative
terminal to ground. All other controlled
switches are OFF; the voltage applied to the
Fig.4.Forward current path at level Vdc/2
load terminals is −3Vdc/4.
SIMULATION AND EXPERIMENTAL
Maximum negative output (−Vdc): S2 is
RESULTS
ON, connecting the load negative terminal
to Vdc, and S3 is ON, connecting the load Analysis of proposed system
positive terminal to ground. All other
controlled switches are OFF; the voltage In order to improve the performance of the
applied to the load terminals is −Vdc. inverter, the nine level inverter with
reduced switch count is proposed which
comprises a single-phase conventional H-
bridge inverter, three bidirectional switches,
and a capacitor voltage divider formed by
C1, C2,C3 and C4.The modified H-bridge
topology is significantly advantageous over
other topologies, i.e., less power switch,
power diodes, and less capacitor for
inverters of same number of levels.
Fig.5.Simulation diagram of proposed nine-
level inverter
SWITCHING PATTERNS FOR PWM
GENERATION
Fig.6.Simulation waveforms of driving
signals for PWM generation
SIMULATION RESULTS OF THE
FOUR CAPACITORS VOLTAGES
OUTPUT VOLTAGE AND CURRENT
WAVEFORMS:
Fig.7.Output of nine level voltage
aveform. Y axis denoted as Voltage and
the X axis denoted as Time.
Fig.8.Output of nine level current
waveform. Y axis denoted as current and
the X axis denoted as Time.
Fig.9.Total harmonic distortion of nine
level output voltage. The THD of the output
voltage is 11.19%
Power Vs efficiency waveform:
Efficiency of the proposed
system is calculated and compared
with existing system.
 higher than the existing system. All
Efficiency the merits and the feasibility of
100 proposed topology are evaluated by a
Efficiency(%)

simulation model.
90
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80
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