FPGA Design

Problem Statement: To design a pipelined 10 bit microprocessor with

a minimum of three pipeline stages on a FPGA using Verilog/VHDL.

You have to design a pipelined 10 bit microprocessor with the under defined instruction set with at
least three pipeline stages. The pipeline should be made in an efficient way so that the different
stages have similar complexity with respect to time. The pipeline should be stalled when dealing
with data hazards and ensure correct execution. Any other way of tackling data hazards would also
be acceptable as long as the program execution is correct and the benefits of pipelining are not
severely reduced.

The instruction set is a 10 bit one, with 4 bits for op-code. The rest of the bits have varying use
depending on the instruction.

Op-code Operation Data Handled

0 INC Register
1 DCR Register
2 MOV 2 operand registers
3 MVI Immediate data and Accumulator
4 ADD 2 operand registers
5 ADI Immediate data and Accumulator
6 ADD 3 registers
7 SUB 2 operand registers
8 SBI Immediate data and Accumulator
9 SUB 3 registers
10 MOVFA Destination Register and Accumulator
11 MOVTA Source Register and Accumulator
12 POD 3 registers
13 POE 3 registers
14 HLT None
15 NOP None

Register File: R0, R1, R2, R3, flag register and Accumulator 8bits each.

Where: INC is the increment Register by 1. DCR is decrement the register by 1.

ADD if defined as a 2 operand instruction will write into the first operand after adding the result of
the two operands. If is also defined as a 3 operand instruction, it adds the last two operands and
writes the result into the first operands.

ADI is an add with immediate operands. The immediate operand is a 6 bit data.

MOV is a move instruction that moves the data from the second register to the first register.
MVI is a move instruction that moves immediate data to the accumulator.

SUB reads and writes from operands just like ADD and it is used for subtracting the last operand
from the second and to store the result in the first operand.

SBI is subtract immediate value from the accumulator.

POD performs a seven bit add on the last two operands and then converts the seven bit result into a
odd parity number with the most significant digit as the parity digit. For the whole operation the last
two operands are considered to be 7 bit operands and the their sum is also 7bits. If the addition
overflows, the program counted must be saved in an error queue of length 4. If the queue is full
after 4 errors the execution must be stopped.

POE is similar to POD but converts the sum of the last two operands into a even parity number.

MOVFA and MOVTA are move from and to accumulator respectively. MOVFA moves data from
accumulator to a given register and MOVTA moves from a register to accumulator.

HLT stops the execution till the device is restarted.

NOP is just an instruction that doesn’t do anything. It goes through all the stages of the processor
without changing anything.

The registers and accumulators are 8 bit and the immediate data is only 6 bit. While performing
the immediate instructions zero padding must be done. Data dependencies between data must be
taken care of to ensure correct execution of the program.

Instruction Format:

One operand immediate instructions have 4bit op-code + 6bit immediate data.

One operand INC instructions have 4bit op-code + 2bit for register selection +4 don’t care bits.

Two operand move instructions have 4bit op-code + 4bits for registers selection (2bits for one
register) + 2 don’t care bits.

Two operand add instructions have 4bit op-code +2 register selection bits + 2 don’t care bits + 2
register selection bits.
 Detailed Format is explained in the table below:-
Instruction B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Immediate
Data Type Op-code Immediate data
instructions
Single Op-code Operand Don’t Care
Operand
Instruction
INC,DCR,
MOVFA,MOVT
A
MOV type Op-code First Operand Second Operand Don’t Care
instructions
2 operand First Operand Don’t Care Second Operand
ADD Op-code
instructions
3 operand
ADD, SUB, First Operand Second Operand Third Operand
POD and POE Op-code
instructions

All instructions other than MOV are to set flags. The flag register has

Carry flag Zero flag Auxiliary Sign flag Parity Don’t care Don’t care Don’t care
carry flag Odd flag
B7 B0
When all the instructions are executed you must show that Microprocessor is in halt state by making
a Led glow on FPGA.

Note- You can use board memory (EEPROM) or you can make memory where instructions will be
stored.

BONUS (NOT COMPULSARY)

Before the execution of instructions you will have to show the values of all registers R 0-R3, Flag
Register and Accumulator on LCD. Again show the values of all registers on LCD after the execution
of all instructions.
You can add as much features as you want.

Judging Method:-
A sequence of some instructions (instructions may be repeated) complete in all respect will be given.
Instructions will be written in memory. Microprocessor should work according to instructions and
change the values of registers. Any no. of extra features may be added, keeping in mind that these
extra features are indeed user-friendly.

Judging Criteria:-
1. Completeness of the solution for the basic problem statement given.
2. No. of logic elements used (eg. no. of LUTs, flip flops).
3. Latency of Pipeline.
 4. Amount of memory implemented or external memory used to perform instructions.
5. Maximum frequency achieved without using external crystals.
6. Power Consumption.
7. No. of extra features added.
Note:-The output interface is a secondary criterion for Judging. So your primary focus should be to
build the microprocessor architecture in an efficient manner.

Software to be used:-
You can use Xilinx ISE Design Suit or Modelsim to simulate your design on your PCs. You can
download it here for free. You need to register first at Xilinx Website:-
http://www.xilinx.com/tools/webpack.htm
The final code will be programmed into the FPGA Kits using Xilinx ISE Version 9 at the VLSI Lab of
MNNIT Allahabad.

You may use any of the languages Verilog/VHDL to create your design.

Participation Rules:-
1. A team can have a maximum of 4 members. Students from different educational institutes
may form a team.
2. The decision made by the coordinators is final.
3. Rules and Regulations, if changed will be informed to the participants via email.
4. The students must be present with valid identity cards at the time of event.
5. You need to register yourself for the event at avishkar site.

Contacts:-

Nirmal Prasad Supreeth P. Rohit Kumar

nirmalfalling@gmail.com venkatsupreeth@gmail.com rkmnnit5021@gmail.com
+91-9889-751-353 +919889908826

Ashish Sethi Ashish Srivastav

simplymeashish@gmail.com ashishsri28@gmail.com
+91-9616827905 +919336138168

For any query regarding Electromania you can contact

Shobhit Singhal
shobhitsinghal123@gmail.com
+919005321924