◆ SPECIFICATION
◆ TROUBLE SHOOTING
◆ ENGINEERING SPECIFICATION
◆ BLOCK DIAGRAM
◆ CIRCUIT
◆ BOM
- NP-42S5****** BOM
- NP-42H5****** BOM
- NP-50H5****** BOM
◆ EXPLODED VIEW
- NP-42S5****** Exploded View
- NP-42H5****** Exploded View
- NP-50H5****** Exploded View
◆ INSPECTION METHODS
Main Features
● High Contrast Ratio & High Brightness
● Built in Tuner
● Built in Speakers (Option)
● HDMI Port Support Up to 1920 x 1080i
● Multi-Scanning RGB(PC) Monitor Support Up to 1024 x 768 / 60Hz
1360 x 768 / 60Hz (nVidia Only)
● Multi-Digital Signal Compatibility : SDTV , HDTV
● Multi-Video System Supported : NTSC/PAL
● Multi-TV System Supported : NTSC/PAL - M/ N
● Multi-TV Sound System Supported : A2 , BTSC
● Multi-PiP Support (Normal , PiP , PBP)
● Variable Image Aspect Ratios (Wide, 4 : 3 , 16:9, Panorama, Zoom)
● Variable Picture Mode (Sandard , Movie , Mild , Dynamic , Custom)
● Variable Sound Mode (Normal , Music , Movie , Speech , Custom)
● Variable TV Stereo Mode (Stereo , Dual , Mono) & Auto Volume
● Variable Color Temp (Warm1, Warm2 , Normal , Cool1, Cool2)
● 3D Comb-filter
● Digital Image Enhancement (DLTI / DCTI)
● Digital Noise Reduction
● Digital Still
● Sleep Timer
● TV Channel Auto Serching
● Close Caption & V-Chip Supported
● Quiet Fanless Operation
● Ultra slim & light design
PDP TV
Specifications
Item
42" SD 42" HD 50" HD
Screen Size(Active Area) 42" (920.1(H) x 518.4(V)±5mm) 50" (1106.5(H) x 622.1(V)±5mm)
Aspect ratio 16:9
Number of Pixels 852 (H) x 480 (V) 1024 (H) x 768 (V) 1366 (H) x 768 (V)
Pixel Pitch 1.080(H) x 1.080(V) [mm] 0.900(H) x 0.676(V) [mm] 0.810(H) x 0.810(V) [mm]
Display Displayable Colors 16.7 Million Colors
Brightness 1500 cd/㎡ 1200 cd/㎡ 1000 cd/㎡
10000:1 8000:1 8000:1
Viewing Angle Over 160 degrees
Internal Speaker 10W(L) + 10W(R) [RMS] / 8 Ω
Speaker
Output External 10W(L) + 10W(R) [RMS] / 8 Ω
Speaker 2 Way 3 Speaker System
RS-232C 3.5mm Jack TXD/RXD
Digital RGB : TMDS
HDMI HDMI Jack MAX : 1920 x 1080i
Input
RCA-pin x 1 Audio : 0.5V[rms] (L+R)
RGB:0.7V[p-p](75Ω), H/CS/V:TTL (2.2 kΩ), SOG:1V[p-p](75Ω)
RGB D-Sub 15-pin x1 MAX : 1024 X 768 / 60 Hz (XGA)[42"] , 1360 X 768 / 60 Hz (nVidia
Input Only)[50"]
Operational 0 ~ 40 ℃
Temperatur
Storage -20 ~ 60 ℃
Environment Humidity Operational 20 ~ 80% RH (No condensation)
Condition Storage 10 ~ 90% RH (NO condensation)
Operational 800 ~ 1100 hPa (Altitude : 0 ~ 2,000 m)
Pressure
Storage 700 ~ 1100 hPa (Altitude : 0 ~ 3,000 m)
* The specifications are subject to change without notice
External Speaker (Optional)
Specifications
Item
42" (A) 42" (B) 50"
Dimensions (W mm x H mm x D 113 x 626.6 x 82.2 90 x 625 x 68 90 mm x 721 mm x 68 mm
Weight 5 Kg ( L + R ) 2.9 Kg (L+R) 3 Kg ( L + R )
Type 2 Way 3 Speaker System
Input 10 W ( RMS)
Impedence 8Ω
Output Sound Pressure 87 dB/W/M
Item Specifications
Type 1 Way 1 Speaker System
Input 10 W ( RMS)
Impedence 8Ω
Output Sound Pressure 88 dB/W/M
Frequency Response 140 Hz ~ 10 KHz
Accessories
Owner's Instruction , Remote Controller/AAA Batteries , Antenna Cabl
Standard
Power Cord , Speaker Cable
Foot Stand , Table-Top stand , Wall-Mount Bracket , Ceiling-Mount Brac
Internal Speaker System , External Speaker System ,
Optional HDMI Cable , VGA(D-SUB) Cable , Audio Cable , Component Cable ,
RCA Video/Audio Cable , S-Video Cable
Abnormal TV Signal
NO
NO
Replace YES
Main Board Replace Main Board
/ Check
NO
Replace HDMI,
YES Replace Cable
RGB, RCA Cable
/ Check
NO
Replace
YES
Main Board Replace Main Board
/ Check
NO
YES
Replace
RCA Cable (HDMI)
3.5mm Cable(PC), Replace Cable
RCA Cable (ComponentI)
/ Check
NO
NO
Replace YES
Sub Board Replace Sub Board
/ Check
NO
Replace YES
Main Board Replace Main Board
/ Check
NO
Replace
YES Replace Cable
RCA Cable
/ Check
NO
Replace YES
Sub Board Replace Sub Board
/ Check
NO
Replace YES
Main Board Replace Main Board
/ Check
NO
NO
Replace
Connector Ass'y YE Replace Connector Ass'y
/ Check
NO
Replace YES
Control Board Replace Control Board
/ Check
NO
Replace YES
Power Board Replace Power Board
/ Check
NO
Replace
YES
Main Board Replace Main Board
/ Check
NO
Replace YES
Sub Board Replace Sub Board
/ Check
NO
Replace
YES Replace Cable
Connector Ass'y
/ Check
NO
Replace
YES
Control Board Replace Control Board
/ Check
NO
PDP – TELEVISION
TABLE OF CONTENTS
1. SCOPE
1.1 Introduction.
1.2 Product Definition.
1.3 Mass Production Release.
1.4 Change Control.
1.5 Service.
2. GENERAL SPECIFICATION
2.1 General Spec.
2.2 Input / Output Terminal.
4. POWER
4.1 Power Supply.
8. MECHANICAL
8.1 Fan.
8.2 Dimension.(without stand)
8.3 Weight.
9. ENVIRONMENTAL
9.1 42”SD Environmental Conditions.
9.2 42”HD Environmental Conditions.
9.3 50”HD Environmental Conditions.
10. PACKAGING
10.1 Packaging Specifications.
10.2 Vibration.
10.3 Drop.
1.1 Introduction
1.5 Service
Native Resolution & Frequency 852 X 480 @ 60Hz 1024 X 768 @ 60Hz 1366x768 @ 60Hz
HDMI Jack x1
HDMI Input (Type A)
RCA Jack(L+R) × 1
RCA(YPbPr/YCbCr) Jack × 2
Component Input
RCA(L+R) Jack × 2
D-Sub 15-Pin Cable Connector Pin out Pin 1 Red analog Signal
Pin 4 GND
Pin 5 GND
Pin 9 NC
Pin 10 GND
Pin 11 GND
Pin 14 V-Sync
☞1) Non-Ignition Dot(Dark Defect) is defined as “A cell of which more than 50% area is not ignited”
☞2) Unstable Dot (Flickering) is defined as “A cell which repeats On and Off”
☞3) Uncontrollable Dot is defined as “A cell which is distinctly brighter or darker than other cells around it” and/or
“A cell of which color is distinctly different from that of other cells around it”
☞4) Non-Extinguishing Dot (brightness defect) is defined as “A cell of which more than 50% area is always ON”
☞5) Stain is defined as “A blob due to local color contamination in white or simple color pattern”
7.2 42” HD Cell Defect Specifications
☞1) Non-Ignition Dot(Dark Defect) is defined as “A cell of which more than 50% area is not ignited”
☞2) Unstable Dot (Flickering) is defined as “A cell which repeats On and Off”
☞3) Uncontrollable Dot is defined as “A cell which is distinctly brighter or darker than other cells around it” and/or
“A cell of which color is distinctly different from that of other cells around it”
☞4) Non-Extinguishing Dot (brightness defect) is defined as “A cell of which more than 50% area is always ON”
☞5) Stain is defined as “A blob due to local color contamination in white or simple color pattern”
7.3 50” HD Cell Defect Specifications
☞1) Non-Ignition Dot(Dark Defect) is defined as “A cell of which more than 50% area is not ignited”
☞2) Unstable Dot (Flickering) is defined as “A cell which repeats On and Off”
☞3) Uncontrollable Dot is defined as “A cell which is distinctly brighter or darker than other cells around it” and/or
“A cell of which color is distinctly different from that of other cells around it”
☞4) Non-Extinguishing Dot (brightness defect) is defined as “A cell of which more than 50% area is always ON”
☞5) Stain is defined as “A blob due to local color contamination in white or simple color pattern”
8. MECHANICAL
8.1 Fan
107.4mm[B-type] 114.3mm[D-type]
9. ENVIRONMENTAL
10. PACKAGING
Ver.01 INPU
2006.03.16 MENU - VOL + - CH +
T
RXD
E2PROM DDR Flash ROM
RS-232C TXD
EEPROM(DDC)
I2S HDMI AUDIO
A LVDS1
HDMI HDMI Input HDMI IN CON
TUNER
TV
SIF
TUNER
POWER
L R
HDMI V
AUDIO
PROCESSOR AUDIO AMP
L R MAX10W*2 CON Rint
COMPONENT 1 MICRONAS MSP4440K R
AUDIO OR TDA7262
MICRONAS MSP4410K Internal
L R Speaker
Lint Output
L
COMPONENT 2 AUDIO
L R
AV1/S-VIDEO AUDIO
AUDIO
L R
AV2
AUDIO
I2S HDMI AUDIO
L R A
AUDIO OUT
AUDIO
AUDIO PART
5 4 3 2 1
l
tia
C C
en
id
nf
B B
Co
A A
Date
CONFIDENTIAL Friday, February 10, 2006
Title Sheet 1 of 10
Size Rev Document Number
A3 A1 <Doc>
01 Cover story Note
Designer LAB 3
Address
5 4 3 2 1
5 4 3 2 1
Stby_5V
DVI_5V
Stby_5V DVI_5V DVI_5V DVI_5V
D1
R319 R320
10K 10K R342 R343
PC2_5V R322 B S B S 10K 10K Signal
100 U41 DVI_5V B B
BAV70L D6 D11 D12 B S S S DETECT
T S BAV99 BAV99 BAV99 6 8
3 DVI_DDC_SCL SCL VCC GND
B S B S T S 5 D23 D24
3 DVI_DDC_SDA SDA BAV99 BAV99
R323 1 7 C466 B B
JACK1 R308 100 A0 WP 100nF NS NS
2 A1
1K Q1 B S 3 4 B S High Active
PC2_5V S T MMBT3904 A2 GND
+5V 18 DTV1_DET 7
D HPD 19 HPD T S ESD Circuit in MUX D
15 DVI_DDC_SCL R318 AT24C04 JACK5
DDC SCL DTV2_DET 7
3
DVI_DDC_SDA 4.7K B S SHRCA-623-G.B.R
10
DDC SDA 16 DVI_DDC_SCL 3
4
13 1 T S HB-1M2012-121
CEC HPD0 7
14 C457 C456 C461 DVI_DDC_SDA 3 T 3 9 FB32 B S
NC Stby_5V Y Y DTV2_Y 3
15pF 15pF 15pF S
2
20 B B T D10 D9 D2 D3 D4 D5 D7 D8 HB-1M2012-121
20 NS NS NS BAV99 BAV99 BAV99 BAV99 BAV99 BAV99 BAV99 BAV99 FB33 B S
21 21CEC/DDC GND 17 2 8 DTV2_Pb 3
22 B S B S B S B S B S B S B S B S Pb Pb
22 HB-1M2012-121
23 23 Dat2 shield 2
5 1 7 FB34 B S
Dat1 shield High Active Pr Pr DTV2_Pr 3
Dat0 shield 8
11 PC2_5V C483 C484 C485
CHK_DVI 7
6
11
clk shield Bottom TOP 15pF 15pF 15pF R344 R345 R346 C486 C487 C488
R309 R644 C460 B B B 75 75 75 68pF 18pF 18pF
2k 3.3k 100nF NS NS NS B B B B S B S B S
T S T S T S NS NS NS
l
HDMI Type A CON FB35 HB-1M2012-121 B S
T S
tia
DTV1_Y 3
FB36 HB-1M2012-121 B S
C465 C464 C454 C455 C458 C459 C462 C463
DTV1_Pb 3
15pF 15pF 15pF 15pF 15pF 15pF 15pF 15pF
T T T T T T T T FB37 HB-1M2012-121 B S
NS NS NS NS NS NS NS NS
DTV1_Pr 3
C C
en
2
R328 1K T S
2 DVI_R_IN 6
D29 D30 D31 D28
R
2
1
T S T S B S
DTV2_L_IN 6
FB39
1K_OHM_200MA R348 1K B S
1
3 4 B S
W R DTV2_R_IN 6
FB40
1K_OHM_200MA R349 1K B S
1 2 B S
id DSUB_5V W R FB41
1K_OHM_200MA R350 1K B S
DTV1_R_IN 6
6
B S
DTV1_L_IN 6
Stby_5V DSUB_5V
D20 R331 R332 R333 R335 R334
10K 10K 10K 10K 10K
B B B B B
PC_5V S S S S S C495 C496 C498 C497
nf
330pF 330pF 330pF 330pF
BAV70L D15 D16 D17 D18 D19 B B B B
T BAV99 BAV99 BAV99 BAV99 BAV99 S S S S
B B
S B B B B B
17
NS NS NS NS NS
6 FB27
JACK3 1 PC_R
DSUB_R 3
DSUB 15P 11 0 B S
T S 7 FB28
2 PC_G
DSUB_G 3
12 DDC1_DAT 0 B S VADC3.3V
8 FB29
Co
3 PC_B
DSUB_B 3
13 PC_HYNC 0 B S
PC_5V U43B
14
14
9
4 T S
14 PC_VSYNC
10 DET_PC PC_HYNC 1 2 3 4
DET_PC 7 ADC_HS 3
5
15 DDC1_CLK C479
Low Active 33pF U43A
7
U42 DSUB_5V B S SN74LVC14APWR
16
T S
6 SCL VCC 8
5 VADC3.3V
SDA
1 7 C477 C478
A0 WP 100nF VADC3.3V 100nF VADC3.3V
2 A1
C469 C470 C471 C472 C473 C474 C475 C476 3 4 B S T
15pF 15pF 15pF 15pF 15pF 15pF 15pF 15pF A2 GND S
B NS B NS B NS B NS B NS B NS B NS B NS
AT24C02N U43C U43E U43F
14
14
14
14
B S SN74LVC14APWR T S T S
T S
PC_VSYNC 5 6 9 8 11 10 13 12
ADC_VS 3
FB30 R338 C480 U43D
JACK8 1K_OHM_200MA 1K 33pF T S
7
7
B B S B S B S
b
c C PC_R_IN 6
A
e E A
f F
d D PC_L_IN 6
2
Title Sheet 2 of 10
Size Rev Document Number
D21 D22 C A1 <Doc>
MMBZ5V6ALT1 MMBZ5V6ALT1 02 Graphic Input
B NS B NS Note
Designer LAB 3
Address
5 4 3 2 1
5 4 3 2 1
119
113
126
102
123
106
C500 220pF T S
29
32
39
53
65
73
86
88
90
67
75
92
4
R359 10K T S
AVDD_DVI1
AVDD_DVI2
AVDD_ADC1
AVDD_ADC2
AVDD_ADC3
VDDP1
VDDP2
VDDP3
VDDP4
VDDP5
VDDP6
VDDP7
VDDP8
AVDD_PLL
VDDC1
VDDC2
VDDC3
VDDC4
AVDD_MPLL
2 HSYNC0
5Vcc R360 33 B S C501 47nF B S
2 DSUB_B
FB43 3
D VSYNC0 GBE[9:2] 7 D
FB_50_600mA R362 C503
R361 C502 T NS 75 18pF 80 GBE5
470K 470pF B B DATA3 GBE4
DATA2 81
B B S S 82 GBE3
NS NS R363 68 B S C504 47nF B S DATA1 GBE2
DATA0 83
R370 R371 C506 + C505 6 76 GBE9
68K 2K 10nF 47uF/16V BIN0P DATA7 GBE8
DATA6 77
T T T T R364 390 B S C507 1nF B S 7 78 GBE7
C508 B NS U45 NS NS NS NS BIN0N DATA5 GBE6
DATA4 79
10nF R365 68 B S C509 47nF B S 8
2 DSUB_G SOGIN0
C510 T NS 1 24
2 DTV2_Pr 47uF/16V RED1_in HD1_in R366 C512
+
9 GIN0P GGE[9:2] 7
C511 B NS 2 23 75 18pF
10nF HD_Sync HD2_in B B GGE5
10 GIN0N DATA11 59
C513 T NS 3 22 S S 60 GGE4
2 DTV2_Y 47uF/16V GREEN1_in HD_out DATA10
R367 33 B S C514 47nF B S GGE3
+
11 RIN0P DATA9 61
C515 B NS 4 21 DTV_SEL_Pr 62 GGE2
10nF GND1 RED_out DATA8 GGE9
12 RIN0N DATA15 55
C516 T NS 5 20 R368 33 B S C517 47nF B S 56 GGE8
2 DTV2_Pb 47uF/16V BLU1_in Vcc 2 DSUB_R DATA14 GGE7
+
DATA13 57
C518 T NS 6 19 DTV_SEL_Y R369 C520 58 GGE6
10nF GND2 GREEN_out 75 18pF DATA12
C519 T NS 7 18 B B
10 DTV3_Pr 47uF/16V RED2_in VIDEO_in S S
+
GRE[9:2] 7
C521 T NS 8 17 R372 68 B S C522 47nF B S
10nF GND3 SYNC_out GRE5
DATA19 47
C523 T NS 9 16 10 ID2mstar 48 GRE4
10 DTV3_Y GREEN2_in CTL DTV_2_3_SEL 7 DATA18
l
47uF/16V GRE3
+
DATA17 49
C525 T NS 10 15 DTV_SEL_Pb R373 33 T S C524 47nF T S 50 GRE2
10nF GND4 BLUE_out 2 DTV1_Pb DATA16
43 GRE9
C526 T NS R374 C527 DATA23 GRE8
11 14 13 44
tia
10 DTV3_Pb 47uF/16V BLU2_in VD_out HSYNC1 DATA22
75 18pF GRE7
+
DATA21 45
12 13 T T 14 46 GRE6
VD1_in VD2_in S S R375 68 T S C528 47nF T S VSYNC1 DATA20
DTV3 = DTV Module Input 15 BIN1P
BA7657-SOP24
B R376 390 T S C529 1nF T S 16
NS BIN1N R379 22 T S
C
DATACK 68 IN0CLK 7 C
R377 33 T S C530 47nF T S 17 69 R380 47 T S
2 DTV1_Y SOGIN1 SOGOUT IN0SOG 7
70 R382 47 T S
HSOUT IN0HS 7
R398 R378 C531 18 71 R383 47 T S
GIN1P VSOUT IN0VS 7
0 B S 75 18pF 72 TP102
DTV2_Y DTV_SEL_Y T T FIELD/GPO T POINT R B S
19 GIN1N
S S
R381 68 T S C532 47nF T S 20
R390 RIN1P
96 HDMI_DAT 6
en
0 B S AUSD
21 RIN1N AUSCK 97 HDMI_CLK 6
DTV2_Pb DTV_SEL_Pb R384 33 T S C533 47nF T S 98
2 DTV1_Pr AUWS HDMI_WS 6
99 TP103
R385 C534 AUMUTE
MCLKO 100 R648 47 T POINT R T S
R401 75 18pF B NS
0 B S T T 101 TP104 T S
DTV2_Pr DTV_SEL_Pr S S SPDIF T POINT R
PAL change points
R386 68 T S C535 47nF T S
VDVI3.3V
Md
Sd
Te
3s
3s
8
8=
-
19
1C
0h
DTV_SEL_Pb R389 33 B S C536 47nF B S
120 R387 390 1% B S
I
2
C
A
r
(
P
o
r
t
1
)
R391 C540 REXT
75 18pF 22 C537
id DTV_SEL_Y
B
S
R399
75
B
S
C544
18pF
R393
R395
R396
68 B S
390 B S
33 B S
C541
C542
C543
47nF
1nF
47nF
B S
B S
B S
23
24
25
26
27
BIN2P
BIN2N
SOGIN2
GIN2P
GIN2N
RIN2P
VREFP
VREFN
A0
128
1 B
36
C538
100nF
S
If A0 = high,
Then Address : 9E
100nF
B S
C539
100nF
B S
nf
B B 28
S S RIN2N
R400 68 B S C545 47nF B S
B B
C546
33 22pF
DTV_SEL_Pr R402 33 B S C547 47nF B S XOUT T S
108 Y4
2 RX0M RX0N
R404 C548 109 14.318MHz
2 RX0P RX0P
75 18pF 111 T S
2 RX1M RX1N
B B 112 34 C549
2 RX1P RX1P XIN
S S 114 22pF
2 RX2M RX2N
R405 68 B S C550 47nF B S 115 T S
Co
2 RX2P RX2P
117 41 DVI_HDCP_SCL
2 RXCM RXCKN MCL
2 RXCP 118 RXCKP
VADC3.3V R406 100 B S 124 42 DVI_HDCP_SDA
2 DVI_DDC_SCL DDCSCL MDA
R407 100 B S 125
2 DVI_DDC_SDA DDCSDA
R408
10K 40 121
7 ADC_INT INT NC17
B R409 100 B S 37 95
7,8,10 SCL1 SCL NC10
S R410 100 B S 38 94
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
7,8,10 SDA1 SDA NC9
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
35
NC1
NC2
NC3
NC4
NC6
NC7
NC8
HWRESET
Active HIGH
3
Q2
5
30
31
54
66
74
87
89
91
103
104
105
107
110
116
122
127
51
52
63
64
84
85
93
1 MMBT3904 MST3388-110
4,5,6,7 RESET_DEVICE
B T S
R411 S
2
1K
B
S 5Vcc
w
/
H
D
C
P
K
e
y
R617 R618
10K 10K
B B U72 5Vcc
S S
DVI_HDCP_SCL 6 8
DVI_HDCP_SDA SCL VCC
5 SDA
A C820 A
1 7 100nF
A0 WP B
2 A1
3 4 S
A2 GND
VDDP3.3V VADC3.3V VDVI3.3V VPLL3.3V VMPLL3.3V VDDC2.5
AT24C04?
B
S
+ C551 C557 C558 C559 C560 C561 C562 C563 + C552 C564 C565 C566 + C553 C567 C568 + C554 C569 + C555 C570 + C556 C571 C572 C573 C574
10uF/16V 100nF 100nF 100nF 100nF 100nF 100nF 100nF 10uF/16V 100nF 100nF 100nF 10uF/16V 100nF 100nF 10uF/16V 100nF 10uF/16V 100nF 10uF/16V 100nF 100nF 100nF 100nF Date
T B T B T B B T T T B T T B B T T T T T T B B CONFIDENTIAL Friday, February 10, 2006
S S S S S S S S S S S S S S S S B S S S S S S S Title Sheet 3 of 10
S Tango Size Rev Document Number
C A1 <Doc>
03 Graphic_ADC Note
Designer LAB 3
Address
5 4 3 2 1
5 4 3 2 1
U48
TAD0 21 2 TDQ0
TAD1 A0 DQ0 TDQ1
22 A1 DQ1 3
TAD2 23 5 TDQ2
Tuner_CVBS_TW C596 100nF B S TAD3 A2 DQ2 TDQ3
24 A3 DQ3 6
TAD4 27 8 TDQ4
AV1_CVBS_IN_TW C597 100nF B S TAD5 A4 DQ4 TDQ5
28 A5 DQ5 9
TAD6 29 11 TDQ6
Tuner_CVBS_TW AV2_CVBS_IN_TW C598 100nF B S TAD7 A6 DQ6 TDQ7
10 TUNER_CVBS 30 A7 DQ7 12
TAD8 31 39 TDQ8
C821 L6 C822 R625 HS/AV3_CVBS_TW C599 100nF B S TAD9 A8 DQ8 TDQ9
32 A9 DQ9 40
330pF 3.3uH/b 330pF 75 TAD10 20 42 TDQ10
B B B B LU1_IN_TW C600 100nF B S TBA0 A10/AP DQ10 TDQ11
19 BA DQ11 43
S S S S 45 TDQ12
FS_CVBS/LU2_TW C601 100nF B S U49 DQ12 TDQ13
DQ13 46
59 24 TDQ15 48 TDQ14
D MUX0 DRAM_DQ15 TDQ14 TUDM DQ14 TDQ15 D
58 MUX1 DRAM_DQ14 25 36 UDQM DQ15 49
AV1_CVBS_IN_TW 57 28 TDQ13 V-MEM_3.3V TLDM 14
10 AV1_CVBS_IN MUX2 DRAM_DQ13 LDQM
CH1_IN_TW C602 100nF B S 56 29 TDQ12 /TRAS 17 1 V-MEM_3.3V
C823 L7 C824 R626 MUX3 DRAM_DQ12 TDQ11 /TCAS RAS VDD
55 MUX4 DRAM_DQ11 30 16 CAS VDD 25
330pF 3.3uH/b 330pF 75 CH2_IN_TW C603 100nF B S 54 31 TDQ10 /TWE 15 7
B B B B MUX5 DRAM_DQ10 TDQ9 R38 /TCS WE VDDQ
60 YGND DRAM_DQ9 32 18 CS VDDQ 13
S S S S 62 33 TDQ8 4.7K 44
R431 0 T S CGND DRAM_DQ8 TDQ7 B CKE VDDQ
10 SCART_FB DRAM_DQ7 13 34 CKE VDDQ 38
YBFOUT 53 14 TDQ6 S TCLK 35
YBOUT DRAM_DQ6 TDQ5 CLK
DRAM_DQ5 18 VSS 50
AV2_CVBS_IN_TW FB95 1K_OHM_200MA T S C604 100nF T S 63 19 TDQ4 CKE 33 26
10 AV2_CVBS_IN 10 SCART_R CIN0 DRAM_DQ4 N.C VSS
64 20 TDQ3 37 4
C825 L8 C826 R627 CIN1 DRAM_DQ3 TDQ2 N.C/RFU VSSQ
DRAM_DQ2 21 VSSQ 10
330pF 3.3uH/b 330pF 75 FB96 1K_OHM_200MA T S C605 100nF T S 50 22 TDQ1 47
10 SCART_G FB0 DRAM_DQ1 VSSQ
B B B B 5 TTX_FB TTX_FB 51 23 TDQ0 41
S S S S FB1 DRAM_DQ0 VSSQ
FB97 1K_OHM_200MA T S C606 100nF T S 47 120 TAD11 K4S161622
10 SCART_B RIN0 DRAM_AD11
43 4 TAD10 B NS
GIN0 DRAM_AD10
TTX_R
41 BIN0 DRAM_AD9 121 TAD9
TAD8
1Mx16 DRAM
R628 R629 R630 5 TTX_R C607 100nF B S 122
75 75 75 DRAM_AD8 TAD7
46 RIN1 DRAM_AD7 123
HS/AV3_CVBS_TW T T T 5 TTX_G TTX_G C608 100nF B S 44 124 TAD6
10 HS/AV3_CVBS GIN1 DRAM_AD6 U73
S S S 40 126 TAD5
C827 L9 C828 R631 TTX_B C611 100nF B S BIN1 DRAM_AD5 TAD4 TAD0 TDQ0
5 TTX_B DRAM_AD4 127 23 A0 DQ0 2
330pF 3.3uH/b 330pF 75 R434 100 B S 75 128 TAD3 TAD1 24 4 TDQ1
5,7,10 SCL3 SCLK DRAM_AD3 A1 DQ1
B B B B R435 100 B S 76 1 TAD2 TAD2 25 5 TDQ2
S S S S 5,7,10 SDA3 SDAT DRAM_AD2 TAD1 TAD3 A2 DQ2 TDQ3
PAL change points 74 SIAD0 DRAM_AD1 2 26 A3 DQ3 7
l
3 TAD0 TAD4 29 8 TDQ4
DRAM_AD0 TAD5 A4 DQ4 TDQ5
3,5,6,7 RESET_DEVICE 77 RST 30 A5 DQ5 10
73 7 TBA0 TAD6 31 11 TDQ6
LU1_IN_TW TP105 PDN DRAM_BA0 TBA1 TAD7 A6 DQ6 TDQ7
78 5 32 13
tia
10 LU1_IN INTREQ DRAM_BA1 A7 DQ7
T POINT R 36 TAD8 33 42 TDQ8
C829 L10 C830 R632 B S TMODE TLDM TAD9 A8 DQ8 TDQ9
DRAM_LDM 12 34 A9 DQ9 44
330pF 3.3uH/b 330pF 75 80 117 TUDM TAD10 22 45 TDQ10
B B B B XTI DRAM_UDM /TWE TAD11 A10/AP DQ10 TDQ11
DRAM_WE 11 35 A11 DQ11 47
S S S S 1 2 79 10 /TCAS TBA0 20 48 TDQ12
XTO DRAM_CAS /TRAS TBA1 BA0 DQ12 TDQ13
DRAM_RAS 9 21 BA1 DQ13 50
C C612 Y5 27Mhz C613 6 8 /TCS RP74 51 TDQ14 C
22pF T S 22pF VDDE DRAM_CS 22 TCLK TUDM DQ14 TDQ15
27 VDDE DRAM_CLK 118 R649 33R 39 UDQM DQ15 53
FS_CVBS/LU2_TW T T VDDE_3.3V 82 T S T S TLDM 15 V-MEM_3.3V
10 FS_CVBS/LU2 VDDE Y6 VG[9:0] LDQM
S S 102 93 5 4 VG6 /TRAS 18 1
C831 L11 C832 R633 R438 VDDE VD16 Y7 VG7 /TCAS RAS VDD
116 VDDE VD17 92 6 3 7 17 CAS VDD 14
330pF 3.3uH/b 330pF 75 1M 89 Y8 7 2 VG8 /TWE 16 27
B
S
B
S
B
S
B
S
T
S
IO Pad Power 17 VSSE
TW9919 VD18
VD19 88 Y9
Y2
8 1 VG9
VG2
/TCS 19
WE
CS
VDD
VDDQ 3
26 VSSE#26 VD12 97 5 4 VDDQ 9
81 96 Y3 6 3 VG3 CKE 37 43
en
VSSE#81 VD13 Y4 VG4 TCLK CKE VDDQ
101 VSSE#101 VD14 95 7 2 38 CLK VDDQ 49
CC_5V 115 94 Y5 8 1 VG5
VSSE#115 VD15 Y1
125 VSSE#125 VD11 98 36 N.C
99 Y0 RP75 40 6
CH1_IN_TW VD10 33R N.C/RFU VSSQ
10 CH1_IN 15 VDD VD9 104 28 VSS VSSQ 12
C620 R439 VDD_2.5V 34 105 T S 41 46
C833 L12 C834 R634 100nF 20K VDD VD8 R651 33 T NSVG1 VSS VSSQ
90 VDD VD7 106 54 VSS VSSQ 52
330pF 3.3uH/b 330pF 75 T 110 107 R650 33 T NSVG0
VDD VD6
B B B B S Digital Power VD5 108 K4S641632
3
S S S S Q5 T 16 109 B S
VSS VD4
MMBT3904 S1 YBFOUT 35 VSS#35 VD3 111 4Mx16 DRAM
T 68 112
+
S C621 VSS#68 VD2
91 113
2
CC_5V
R446
22K
T
S
S
AVDP_3.3V
Analog Power
AVD_2.5V
39
45
52
65
42
48
49
61
37
AVD
AVD
AVD
AVD
AVS
AVS
AVS
AVS#61
VCLK1
VCLK2
FIELD
HSYNC
VSYNC
DVALID
MPOUT
AMCLK
100
87
85
86
84
83
72
71
HSYNC
VSYNC
TP106
TP107
TP108
T POINT R
T POINT R
T POINT R
R441
R442
R443
R447
B S
B
B
S
S
IN1CLK
33
33
33
33
T
T
T
T
S
S
S
S
7
IN1FLD
IN1HS
IN1VS
IN1PEN
7
7
7
7
nf
AVDPLL AMXCLK TP109 T POINT R B S
67 AVDPLL#67 ASCLK 70
C628 + C629 C858 69 TP110 T POINT R B S
10uF/16V 100nF 100nF ALRCLK
B
38 AVSPLL B
T T T 66 HSYNC R652 33 B S TTX_HSYNC 5
AVSPLL#66
3
Q6 S S S
MMBT3904 1 TW9919
T T S VSYNC R653 33 B S
S TTX_VSYNC 5
2
I
2
C
A
d
d
r
e
s
s
=
8
8
h
(
P
o
r
t
3
)
R450 R451
0 1K
Co
T T
S S
+ + +
C646 C648 C649 C650 C651 C647 C652 C653 C654 C859 C630 C631 C632 C633 C634 C635 C636 C637 C638 C639 C640 C641
10uF/16V 100nF 100nF 100nF 100nF 10uF/16V 100nF 100nF 100nF 100nF 10uF/16V 100nF 100nF 100nF 100nF 100nF 2.2nF 2.2nF 2.2nF 470pF 470pF 470pF
T S T S T S T S T S T S T S T S T S T S T S B S T S T S B S T S B S T S T S T S B S B S
C622 C624 C614 C616 C618
100nF 100nF 100nF 100nF 100nF
B S T S B NS T NS B NS
A
for 4x16 SDRAM for 1x16 SDRAM A
Date
CONFIDENTIAL Friday, February 10, 2006
Title Sheet 4 of 10
Size Rev Document Number
C A1 <Doc>
04 Video_Decoder & CC Note
Designer LAB 3
Address
5 4 3 2 1
5 4 3 2 1
SDA3.3V
UD[0:7]
SA[0:19] U55
SA0 C735
40
75
92
73
22
56
U56 12 A0 VCC 32
6
U54 SA1 11 100nF
SA0 UD0 SA2 A1 PSEN-P B S
50 20 21 10 24
VDD3.31
VDD3.32
VDD3.33
VDD3.34
VDD2.51
VDD2.52
VDDA2.51
VDDA2.52
3,4,6,7 RESET_DEVICE RST SA[0:19] A0 I/O1 A2 G
SA1 19 22 UD1 SA3 9 22
C736 20pF T S UD0 SA2 A1 I/O2 UD2 SA4 A3 E
53 XTAL1 D0 99 18 A2 I/O3 23 8 A4 VPP 1
1 UD1 SA3 17 25 UD3 SA5 7
D1 UD2 SA4 A3 I/O4 UD4 SA6 A5
D2 3 16 A4 I/O5 26 6 A6
X1 4 UD3 SA5 15 27 UD5 SA7 5 13 UD0
6Mhz D3 UD4 SA6 A5 I/O6 UD6 SA8 A7 Q0 UD1
52 XTAL2 D4 2 14 A6 I/O7 28 27 A8 Q1 14
T S 100 UD5 SA7 13 29 UD7 SA9 26 15 UD2
D5 UD6 SA8 A7 I/O8 SA10 A9 Q2 UD3
D6 98 3 A8 23 A10 Q3 17
C737 20pF T S 9 96 UD7 SA9 2 SA11 25 18 UD4
P0.0 D7 SA10 A9 SDA3.3V SA12 A11 Q4 UD5
10 P0.1 31 A10 4 A12 Q5 19
11 SA11 1 SA13 28 20 UD6
SDA3.3V P0.2 SA0 SA12 A11 SA14 A13 Q6 UD7
12 P0.3 A0 97 12 A12 29 A14 Q7 21
13 94 SA1 SA13 4 SA15 3 UD[0:7]
P0.4 A1 SA2 SA14 A13 C729 SA16 A15
14 P0.5 A2 93 11 A14 2 A16
< Local settings > R507 R508 R509 R510 R511 R512 R513 R514
15
16
P0.6 A3 89
86
SA3
SA4
SA16
SA17
7
10
A15
100nF
T
SA17
SA18
30
31
A17
16
R506
0
3.3K 3.3K 3.3K 3.3K 3.3K 3.3K 3.3K 3.3K P0.7 A4 SA5 SA18 A16 S A18 VSS T S
A5 84 9 A17 VCC 8
B B B B B B B B 82 SA6 24
(P1.7) (P1.6) (P1.0) : Language selection NS NS NS NS S S S NS A6 SA7 VSS R515 M27W101_PLCC32
41 P1.0/PWM0 A7 79
42 81 SA8 0 T S
(P1.5) : LCB P1.1/PWM1 A8 SA9 RAM_OE 32 T NS
43 P1.2/PWM2 A9 83 OE CS2 6
44 90 SA10 RAM_WE 5 30
(P1.4) : 8/30 Info display P1.3/PWM3 A10 SA11 WE CS1
45 85
l
P1.4/PWM4 A11 SA12
46 P1.5/PWM5 A12 77
(P1.3) : Default LIST 47 78 SA13 CS18LV20483/b
P1.6/PWM6 A13 SA14 SA15 B S SDA3.3V
62 P1.7PWM7 A14 76
(P1.2) : Enable I2C(1) 71 SA15
tia
A15 SA16 R536
A16 69
(P1.1) : RGB Gain R516 R517 R518 R519 R520 R521 R522 R523 24 70 SA17 100
0 0 0 0 0 0 0 0 P2.0/ADC0 A17 SA18 B S U57
25 P2.1/ADC1 A18 68
B B B B B B B B 26 67 SA19 TTX_EEP_SCL 6 8
S S S S NS NS NS S P2.2/ADC2 A19 TTX_EEP_SDA SCL VCC C739
27 P2.3/ADC3 5 SDA
SDA3.3V 88 PSEN-P 100nF
R681 PSEN R537 T S
C
ALE 87 1 A0 WP 7 C
100 31 100 2
B NS P3.0 RAM_OE B S A1
32 P3.1/TXD RD 65 3 A2 GND 4
33 64 RAM_WE
C730 + C731 C732 C733 C734 P3.2/INT0 WR
34 P3.3/INT1
22uF/16V 100nF 100nF 100nF 100nF TTX_EEP_SCL 35 28 AT24C02N/24LC21
7,10 AV3_DET_ID P3.4/T0 NC1
T B B T T TTX_EEP_SDA 36 51 B S
S S S S S R524 100 B S P3.5/T1 NC2
7,8,10 SCL2 37 P3.6 NC3 54
38 P3.7/RXD NC4 61
R525 100 B S 63
7,8,10 SDA2 NC5
66
en
NC6
48 P4.2 FL_CE 95
49 P4.3 FL_RST 80
SDA2.5V SDA2.5AV 72
R527 FL_PGM
17 ENE
0 18 57 R526 100 B S TTX_R
STOP R TTX_R 4
B S 19
C723 C724 C725 C726 C727 C728 OCF R528 100 B S TTX_G
20 EXTIF G 58 TTX_G 4
22uF/16V 100nF 100nF 22uF/16V 100nF 100nF
T B B T B B 59 R529 100 B S TTX_B
B TTX_B 4
S S S S S S 21
4 TTX_CVBS CVBS
29 60 R530 5.6K B S TTX_FB
VSSA1
VSSA2
HS/SSC BLANK/COR TTX_FB 4
VSS1
VSS2
VSS3
VSS4
C738 30 5
R531 100nF VS XROM C848 C849 C850 C851
75 B S R532 560pF 560pF 560pF 100pF R533 R534 R535 C852
B 0 B B B B 120pF 120pF 120pF 100pF
4 TTX_HSYNC
55
23
91
74
39
7
NS SDA5550_PQFP100 B S S S S NS B B B B
4 TTX_VSYNC
Euro Version id T
S
S S S NS
I
2
C
A
d
d
r
e
s
s
=
2
2
h
(
P
o
r
t
2
)
TTX Decoder
nf
B B
CC_5V
Co
U52
US Version 4,7,10
4,7,10
SCL3
SDA3
R578
R579
100 B NS
100 B NS
15
14
SCL
SDA
VDD 12
16 SDO BOX 17
CC Decoder 4 TTX_VSYNC
R580 0 B NS
RED
GREEN
18
2
7 VVINT 13 VIN_INTRO BLUE 3
4 TTX_HSYNC 5 HIN
Z86229
C693 C692
100nF 560pF
C690 100nF T NS R479 470 T NS 7 B B
4 TTX_CVBS VIDEO NS NS
R490 100 B NS 4
3,4,6,7 RESET_DEVICE SEN
6 SMS
1 ASEL CSYNC 8
LPF 9
C691 10
560pF RREF R492
11 VSSA
T 6.8K
NS R491 C694 B C696
Z86129 10K 1% 6.8nF NS 100nF
B B B B
NS NS NS C695 NS
I
2
C
A
d
d
r
e
s
s
=
2
8
h
(
P
o
r
t
3
)
68nF
B
A NS A
Date
CONFIDENTIAL Friday, February 10, 2006
Title Sheet 5 of 10
Size Rev Document Number
A2 A1 <Doc>
05 Video_TTX Note
Designer LAB 3
Address
5 4 3 2 1
5 4 3 2 1
+
1 Line_L_OUT
R654 100 T S C860 330nF T S C667
W
D 10 AV_L D
R655 100 T S C861 330nF T S 100nF T S
10 AV_R
2 Line_R_OUT
C674 FB99
R
2
100pF C862 C863 1K_OHM_200MA
MMBZ5V6ALT1
MMBZ5V6ALT1
T S 300pF 300pF B S
3
C668 C669 B B
10 TUNER_SIF
100nF + 10uF/16V MSP_8V 3 3 S S
T T SJB0213-W-W.R-N
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
R480 S S C670 T
+
10uF/16V TV_L_OUT 10
4.7K MSP_5V T S S
VREFTOP
NC10
NC11
AVSS1
AVSS2
SC5_IN_L
SC1_IN_L
ASG1
SC2_IN_L
ASG2
SC3_IN_L
ASG3
SC4_IN_L
NC13
AHVSS1
AHVSS2
SC3_OUT_L
SC5_IN_R
SC1_IN_R
SC2_IN_R
SC3_IN_R
SC4_IN_R
AGNDC
SC3_OUT_R
T C671
+
TV_R_OUT 10
1
S 65 40 C672 10uF/16V T S 10uF/16V T S
AVSUP1 CAPL_M C673 Audio Line Out
+
+
66 AVSUP2 AHVSUP 39 Line_L_OUT
C675 56pF T S 67 38 C676 10uF/16V T S 10uF/16V T S D33 D32
T S C677 56pF B S ANA_IN1+ CAPL_A R477 100 B S C678 T T
+
+
68 ANA_IN- SC1_OUT_L 37 Line_R_OUT
18pF C680 56pF B S 69 36 R478 100 B S 10uF/16V T S NS NS
C679 ANA_IN2+ SC1_OUT_R
70 TESTEN VREF1 35
71 34 R481 100 B S
XTAL_IN SC2_OUT_L R483 100 B S
72 XTAL_OUT SC2_OUT_R 33
2
TP112 B S 73 32
Y6 T POINT R TP DACM_SL C681 C682 C683 C684
74 AUD_CL_OUT DACM_SR 31
18.432MHz 75 30 R484 6.8nF 6.8nF 6.8nF 6.8nF
T NC16 DACM_SUB 470 B S B S B S B S B S
10 SPDIF_OUT 76 29
1
S SPDIF_OUT DACM_C
10 MUX_SEL2 77 D_CTR_1/O_1 DACM_L 28 MSP_L_OUT1
10 MUX_SEL 78 D_CTR_1/O_0 DACM_R 27 MSP_R_OUT1
C685 79 26
I2S_DEL_OUT
ADR_SEL VREF2
I2C_DEL_WS
I2S_DA_OUT
I2C_DEL_CL
18pF 80 25 C686 C687 R485
I2S_DA_IN1
I2S_DA_IN2
I2S_DA_IN3
I2S_DA_IN4
I2S_DEL_IN
MSP_5V STANDBYQ DACA_L
l
T S 1nF 1nF 470 B S C688 C689
I2S_WS3
RESETQ
DACA_R
DVSUP2
DVSUP3
I2C_CL3
I2S_WS
R486 B B 1nF 1nF
I2C_DA
I2C_CL
I2S_CL
DVSS1
DVSS2
DVSS3
1k S S B B
NC1
NC2
T S S S
tia
MSP44x0K
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I
2(
Co
Ar
d3
d)
r
e
s
s
=
8
0
h
T S
P
t
R488 100 B S
7,10 SCL3_5
C TP113 TP114 C
R489 100 B S T POINT R T POINT R
7,10 SDA3_5
B S B S R656 100 B S MSP_8V MSP_5V
HDMI_DAT 3
en
T B 22uF/16V 100nF 100nF
R661 100 B S S S T B B
10 I2S_DTV_DATA
R487 S S S
1.2K
B S
MSP_5V RESET_DEVICE 3,4,5,7
+
C708 C709 C710 C711 C700
22uF/16V 100nF 100nF 100nF 100nF
T B B B B S
S S S S
id
A
u
d
i
o
P
o
w
e
r
A
M
P
nf
B B
AMP_Vcc
U53
9 EC1
VCC1 2200uF/16V CON15
3 ST-BY
R502 T S 6 X
Co
2.2K R493 6
10 5 Right
B S 220 OUT_R+ 5
4 GND
AMP_R R496 B EC3 T S EC2 220uF/16V R494 4
MSP_R_OUT1 2 3 X
10K S R495 2.2uF/35V OUT_R- T S 1.3K EC4 3
2 2 Left
3
4
3
2
1
S S S S T S 100nF 100nF
B S B S
4
3
2
1
7 + EC8 BC1 C720 R498
NC1 100uF/50V(8X10) 100nF 1nF 18 R499 R500 R501 CON35
11 T S B B B 18 5.1 5.1 SMW250-04P
GND_AMP GND_AMP GND_AMP GND_AMP GND_AMP GND_AMP NC2 S S S B S B S B S T GND_AMP
NS
TDA7262
T
S GND_AMP GND_AMP GND_AMP GND_AMP GND_AMP GND_AMP GND_AMP GND_AMP
A A
Date
CONFIDENTIAL Friday, February 10, 2006
Title Sheet 6 of 10
Size Rev Document Number
C A1 <Doc>
06 Audio Note
Designer LAB 3
Address
5 4 3 2 1
5 4 3 2 1
L4 K3 R685 47 B S
3 IN0CLK IN0CLK IN0CLP DVD_1 10
L5 K2 R686 47 B S J1
3 IN0SOG IN0PEN IN0CST DVD_2 10
R225 L3 T NS
0 T S IN0VBI Header 2x1 Stby_5V 3.3V(St-by)
3 IN0SOG L1 IN0SOG
J3 10 RX RX PW_D3.3V
3 IN0HS IN0HS
3 IN0VS J1 IN0VS
TP3 M4 10 TX TX
2
1
T POINT R IN0FLD R226 C243
T S 2K R247 R248 U22 100nF
R307 T S 4.7K 4.7K 2n7002(SOT-23) T S
GRE2 C6 Y3 0 RP30 B S B S T S
GRE3 IN0RE2 14.318MHz T S 47R
A5 IN0RE3 8 RESET_PW S 2 SDA3 4,5,10
GRE4 B5 T S T S 3
IN0RE4 6,10 SDA3_5 D
GRE5 C5 C238 V19 1 8
IN0RE5 DVS DCLK
GRE6 A4 100nF V18 2 7 1
IN0RE6 DHS DEN G
GRE7 D6 T S V17 3 6
IN0RE7 DCLK DVS
GRE8 B4 R229 0 T S AA19 4 5
IN0RE8 10 IRRCVR A[20:1] 8 DEN DHS
GRE9 C4 AA8 D12 A1 U23 2n7002(SOT-23) T S
IN0RE9 RESET A1 A20
3 GRE[9:2] A20 B7 S 2 SCL3 4,5,10
C239 R230 C240 PW_D3.3V W7 D9 A17 DR0 DR1 3 D
XO A17 DRE[9:0] 6,10 SCL3_5
18pF 1M 18pF V7 B11 A16
GGE2 T S T S T S XI A16 A15
D
B3 IN0GE2 A15 C7 DR0 AB14 G 1 D
GGE3 D4 RX Y13 B8 A14 AB15
IN0GE3 RXD A14 DR1
1
2
3
4
1
2
3
4
GGE4 F5 TX W13 D7 A13 AA15 DRE6
GGE5 IN0GE4 U20A R302 RP28 RP29 TXD A13 A12 DR6 T T DRE5 R300 0 B NS
N3 IN0GE5 A12 D8 DR5 AB18
GGE6 E6 10K 10K 10K C10 A11 AA14 DRE4
GGE7 IN0GE6 T B B A11 A10 DR4 S S DRE3 R301 0 B NS
B2 IN0GE7 A10 C9 DR3 AB17
GGE8 E5 PW218 S S S AB13 A11 A9 PW218 AB16 DRE2
8
7
6
5
8
7
6
5
GGE9 IN0GE8 IRRCVR0 A9 A19 DR2 DRE8
D3 IN0GE9 5 VVINT AA13 IRRCVR1 A19 D10 DR8 W14
RP33 47R T S A7 A18 W20 DRE9
3 GGE[9:2] Graphics 8 1 Y9
A18
C8 A8 DisplayPort DR9
Y14 DRE7
Port 4,5,10 SDA3 PORTA0 A8 DR7
7 2 AB11 C11 A7 U20C
3,8,10 SCL1 PORTA1 A7
GBE2 D2 6 3 AA10 E12 A6 DG0 DG1
IN0BE2 5,8,10 SDA2 PORTA2 A6 DGE[9:0]
GBE3 E3 5 4 AA9 D11 A5 PW_A3.3V PW_D1.8V
IN0BE3 4,5,10 SCL3 PORTA3 A5
GBE4 N4 8 1 AB12 C12 A4 AA16
IN0BE4 5,8,10 SCL2 PORTA4 A4 DG0
GBE5 A2 7 2 AB10 A10 A3 AA17
IN0BE5 3,8,10 SDA1 PORTA5 A3 DG1
GBE6 E4 6 3 W9 B12 A2 AB19 DGE2
IN0BE6 3,4,5,6 RESET_DEVICE PORTA6 A2 DG2 T T
GBE7 A1 5 4 W10 A8 R234 47 T S Y15 DGE3
IN0BE7 LVDS_ON PORTA7 A21 DTV1_DET 2 DG3
GBE8 F4 B10 R235 47 T S V20 DGE4 C271 C272 C273 C274
IN0BE8 A22 DTV2_DET 2 DG4
GBE9 B1 RP35 47R T S Y10 U20D E9 R236 47 B S W15 S S DGE8 47uF/16V 100nF 47uF/16V 100nF
IN0BE9 PORTB0 A23 DG8 DGE9 T T T B
3 GBE[9:2] W11 PORTB1 DG9 AB20
RP38 47R T S AA11 PORTB2
PW218 D0 B17 D0 RS232_SEL
RS232_SEL 10 DG5 V14 DGE5 S S S S
5 4 AA12 A16 D8 AA18 DGE6
10 POWER PORTB3 D8 DG6
H4 6 3 AB9 D14 D1 Y16 DGE7
E2
IN0RO2 10 SOURCE
7 2 W12
PORTB4 Misc D1
C16 D9 DG7 PW_D2.5V
IN0RO3 10 MENU PORTB5 D9
P2 8 1 Y11 D17 D2 DB0 DB1
IN0RO4 10 CH+ PORTB6 D2 DBE[9:0]
D1 R544 47 B S Y12 B15 D10
IN0RO5 Internal PD 10 CH- PORTB7 D10
G4 R545 47 B S C17 D3 Y17
IN0RO6 10 VOL+ D3 DB0
M2 R546 47 B S AA6 B16 D11 Y18
IN0RO7 10 VOL- ADC0 D11 DB1
M3 R547 47 B S AB7 D16 D4 W16 DBE2 C249 C250 C251 C252 C253 C254 C255 C256 C257 C258 C259
IN0RO8 3 ADC_INT ADC1 D4 DB2 T T
F3 R636 0 B S V6 D13 D12 Y20 DBE8 47uF/16V 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
IN0RO9 8,10 FSCART_ID ADC2 D12 DB8
R637 0 B S V5 D15 D5 W19 DBE9 T B B B B B B B B B T
8,10 HSCART_ID ADC3 D5 DB9
TP100 T POINT R T S B14 D13 V21 S S DBE3 S S S S S S S S S S S
TP101 T POINT R T S D13 D6 DB3 DBE4
D6 C14 DB4 AA20
P1 TP4 T POINT R T S W21 A14 D14 Y19 DBE5
IN0GO2 TP5 T POINT R T S TMS D14 D7 DB5 DBE6
E1 IN0GO3 Y21 TDO D7 C15 DB6 W17
K5 TP6 T POINT R T S AA22 A15 D15 W18 DBE7 PW_D2.5V
IN0GO4 TP7 T POINT R T S TDI D15 DB7
F2 AB22
l
IN0GO5 Internal PD TP8 T POINT R T S TRST TP9 T POINT R T S D[15:0] 8
N1 IN0GO6 Y22 TCK RD A12
F1 A9 TP10 T POINT R T S 3.3V(St-by)
IN0GO7 WR
J4 IN0GO8 AA21 JTAGSEL ROMOE B9 PROMOEN 8
G3 W22 A13 C260 C261 C262 C263 C264 C265 C266 C267 C268 C269 C270
IN0GO9 TESTMODE ROMWE PROMWEN 8 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
AB21 C13 TP11 T POINT R B S R243 100nF
tia
ADR24B CS0 TP12 T POINT R T S 1K B B B B B B B B B B B
AB8 EXTRSTEN CS1 B13
Y6 Y8 NMI T S PW218_10 S S S S S S S S S S S
ANLGTST NMI T
L2 IN0BO2
G1 S
IN0BO3 R244 R624 R245 PW218_10 R246 C242
H2 IN0BO4
1
2
K1 0 0 0 T 4.7K 100nF PW_A1.8V
IN0BO5 Internal PD T T B S T S T S
K4 IN0BO6
H1 S S S
IN0BO7
C J2 IN0BO8
C
P3 J2
IN0BO9 HEADER 2 C275 C277 C278 C279 C280 C281 C282 C283 C284 C285 C286 C287
T NS 47uF/16V 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
DISPLAY PORT
PW218_10 T B B B B B B B B B B B
T S S S S S S S S S S S S
S
PW_D3.3V
PW218
8 MD[31:0]
R687
U3 W3 47 B S MD0 RP49 47R T20 M22
en
4 IN1CLK IN1CLK IN1CLP DVD_3 10 MD0 MRERIN0 MREFIN 8
R4 AB1 I_PWM 9 MD1 T S T21 C22
4 IN1PEN IN1PEN IN1CST MD1 MREFIN1
TP13 T POINT R T S Y4 MD2 T22 RP50 47R
IN1VBI MD2 RKCK0 8
TP14 T POINT R T S AA1 MD3 R19 B S C276 C288 C289 C290 C291 C292 C293 C294 C295 C296 C297
IN1AHS MD4 RP51 47R MD3 47uF/16V 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
4 IN1VS AB6 IN1HS R20 MD4 MCK V22 RKCK0n 8
AB2 MD5 T S R21 U21 T B B B B B B B B B B
4 IN1HS IN1VS MD5 MCK
Y3 MD6 R22 U20 S S S S S S S S S S S
4 IN1FLD IN1FLD MD6 MCKFBK
A3 MD7 P19 T19
A3 MD8 RP52 47R MD7 MCKFBK
A6 A6 L22 MD8 MCKE A18 RMCKE 8
B6 MD9 T S N20
RP59 B6 MD10 MD9 RP53 47R
C1 C1 M19 MD10 MRAS B20 SDRAS 8
47R T S C2 MD11 K22 A19 B S
C2 MD11 MCAS SDCAS 8
id R3
W6
MD20
MD21
MD22
RP57 47R
T S
G20
E21
D21
MD20
MD21 DDR
Memory
MA0 G22
L20
RP58 47R
B S
MA0
MA1
MA[12:0] 8
PW_A3.3V
AA7
G18
U19
U17
C18
H18
H21
N18
R18
U22
V11
V12
V13
A21
E13
E14
E15
E17
P18
P20
E10
E11
E16
V10
V15
V16
F17
F18
F20
T18
W6 MD22 MA1
L18
J18
J19
J22
M5
U5
H5
R5
N5
VG0 MD23 MA2
Y7
E7
E8
V9
T5
F6
J5
V3 IN1G0 Y1 Y1 C21 MD23 MA2 L19
VG1 R1 Y2 MD24 RP60 47R B21 J21 MA3 C245 C246 C247 C248
4 VG[9:0] IN1G1 Y2 MD24 MA3
VG2 AB3 MD25 T S F19 E22 RP61 47R MA4 100nF 100nF 100nF 100nF
VAA33
DVAA18
MVAA18
PVAA18
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VG3 IN1G2 MD26 MD25 MA4 B S MA5 B B B B
R2 IN1G3 AA4 AA4 E19 MD26 MA5 B19
VG4 T2 MD27 C20 J20 MA6 S S S S
VG5 IN1G4 MD28 RP63 47R MD27 MA6 MA7
T1 IN1G5 D19 MD28 MA7 F22
VG6 MD29 T S RP64 47R MA8
VG7
V4
AA2
IN1G6 MD30
C19
E18
MD29 MA8 K19
K20 B S MA9 PW218 POWER
VG8 IN1G7 MD31 MD30 MA9 MA10
Y5 IN1G8 D18 MD31 MA10 A20
VG9 U1 G21 MA11
IN1G9 MA11 RP65 47R MA12
MA12 K18
10 LED_G RP67 B S
nf
47R M18
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
10 LED_R MBNK0 MBNK0 8
T S H22
MBNK1 MBNK1 8
LVDS_CON LVDS_CON 5 4 U2 U20E
IN1B2 RP66 47R MDM2
6 3 V1 E20 MDM2 8
B22
J9
J10
J11
J12
J13
J14
K9
K10
K11
K12
K13
K14
L9
L10
L11
L12
L13
L14
M9
M10
M11
M12
M13
M14
N9
N10
N11
N12
N13
N14
N19
P9
P10
P11
P12
P13
P14
U18
V8
W8
B IN1B3 MDM2 B S MDM3 B
9 POWERON/OFF 7 2 P4 IN1B4 MDM3 D20 MDM3 8
8 1 U4 A22 MDQS2
IN1B5 MDQS2 MDQS2 8
R548 47 T S V2 G19 MDQS3
3 DTV_2_3_SEL IN1B6 MDQS3 MDQS3 8
R549 47 T S W5
2 HPD0 IN1B7
6 S_MUTE R550 47 T S P5 IN1B8 "AV3_DET_ID" => NT = AV3_DET / EURO = TTX I2C_ID PW218_10
9 LCDON R551 47 T S T4 PW218_10
IN1B9 T S T S
PW218_10
T S
Co
44
34
LVDS_3.3V 27 27
1
9
B NS
26
44
34
31
26 26 CON17
1
9
R552 25 U59
RS
VCC1
VCC2
LVDSVCC
PLLVCC
DRE[9:0] 25
DRE2 50 4.7K 24 1 TP122
31
VCC
VCC
VCC
LVDS VCC
PLL VCC
TD0(R0) 24 DBE[9:0] 1
DRE3 2 B NS 23 DBE2 15 R665 0 T NSLV1 2 LV1 TP130
TD1(R1) 23 TxIN15 3,8,10 SDA1 2
DRE4 51 22 DBE3 19 3 TP127
DRE5 TA0(R2) 22 DBE4 TxIN18 R664 0 T NSLV2 3 LV2 TP126 LVDS_3.3V
52 TA1(R3) 21 21 20 TxIN19 3,8,10 SCL1 4 4
DRE6 54 20 DBE5 22 5 TP128
DRE7 TA2(R4) 20 DBE6 TxIN20 LV3 5 LV3 TP129
55 TA3(R5) 19 19 23 TxIN21 6 6
DRE8 56 18 DBE7 24 LV4 7 LV4 TP123 R573
DRE9 TA4(R6) 18 DBE8 TxIN22 ODD3+ R557 22 T S 7 TP124 0
DGE[9:0] 3 TA5(R7) 17 17 16 TxIN16 TxOUT3+ 37 8 8
DGE2 8 16 DBE9 18 LV5 9 LV5 TP125 T NS
DGE3 TD2(G0) R553 22 B NS 16 TxIN17 ODD3- R560 22 T S LV6 9 LV6 TP121 LVDS_OPT1
10 TD3(G1) TD+ 37 15 15 DGE[9:0] TxOUT3- 38 10 10
DGE4 4 38 R554 22 B NS 14 DGE2 4 11 TP131
DGE5 TA6(G2) TD- 14 DGE3 TxIN7 LV7 11 LV7 TP132 R574
6 TB0(G3) 13 13 6 TxIN8 12 12
DGE6 7 39 R555 22 B NS 12 DGE4 7 39 ODDCLK+R563 22 T S LV8 13 LV8 TP133 0
DGE7 TB1(G4) TCLK+ R556 22 B NS 12 DGE5 TxIN9 TxCLKOUT+ 13 TP134 T S
11 TB2(G5) TCLK- 40 11 11 11 TxIN12 14 14
DGE8 12 10 DGE6 12 40 ODDCLK-R565 22 T S LV9 15 LV9 TP135
DGE9 TB3(G6) U58 R558 22 B NS 10 DGE7 TxIN13 TxCLKOUT- LV10 15 LV10 TP136
DBE[9:0] 14 TB4(G7) TC+ 41 9 9 14 TxIN14 16 16
DBE2 16 42 R559 22 B NS 8 DGE8 8 17 TP137
DBE3 TD4(B0) THC63LVDM83R TC- 8 DGE9 TxIN10 ODD2+ R567 22 T S LV11 17 LV11 TP138
18 TD5(B1) 7 7 10 TxIN11 TxOUT2+ 41 18 18
DBE4 15 45 R561 22 B NS 6 TSSOP56 LV12 19 LV12 TP140
TB5(B2) TB+ 6 DRE[9:0] 19 12Vcc
DBE5 19 46 R562 22 B NS 5 DRE2 51 42 ODD2- R568 22 T S 20 TP139 FB49 V_LCD
DBE6 TB6(B3) TB- 5 DRE3 TxIN0 TxOUT2- LVDS_OPT2 20 LVDS_OPT2 TP141 FB_50_3A
20 TC0(B4) 4 4 52 TxIN1 21 21
A DBE7 22 B NS 47 R564 22 B NS 3 DRE4 54 LVDS_OPT1 22 LVDS_OPT1 TP143 T S A
DBE8 TC1(B5) TA+ R566 22 B NS 3 DRE5 TxIN2 ODD1+ R569 22 T S 22 TP142
23 TC2(B6) TA- 48 2 2 55 TxIN3 TxOUT1+ 45 23 23
DBE9 24 1 31 DRE6 56 24 TP144
TC3(B7) 1 31 DRE7 TxIN4 ODD1- R570 22 T S V_LCD 24 V_LCD TP145
DHS 27 TC4(H_sync) 3 TxIN6 TxOUT1- 46 25 25
28 DRE8 50 26 TP146 5Vcc FB50
DVS TC5(V_sync) TxIN27 26
30 12507WR-30000 DRE9 2 27 TP147 FB_50_3A
DEN TC6(BLANK) TxIN5 27
25 B 47 ODD0+ R571 22 T S 28 TP148 T NS
TD6 NS TxOUT0+ 28 TP149
DHS 27 TxIN24 29 29
28 48 ODD0- R572 22 T S 30 TP150
32
LVDSGND1
LVDSGND2
LVDSGND3
32 12507WR-30000
GND
LVDS_ON PWRDN
LVDS GND
LVDS GND
LVDS GND
25 T S
PLL GND
PLL GND
TxIN23
LVDS_ON 32 PWRDWN
For LG PDP Panel 17
GND
GND
GND
GND
GND
5
13
21
29
53
36
43
49
33
35
R_FB Date
CONFIDENTIAL Friday, February 10, 2006
5 4 3 2 1
5 4 3 2 1
DDR_2.5V
R249
1K
T S
FLASH 8M
R250
1K
C298
100nF
C299
100nF
C300
100nF
FBGA DDR SDRAM 128M D[15:0] 7
T T T T
S S S S
D D
PW_D3.3V
U25A
R251 47K
MD[31:0] 7
N13 B S
7 MREFIN VREF
B7 MD0 R252 10K PW_D3.3V
DQ0 MD1 B S
7 RKCK0 M11 CK DQ1 C6
M12 B6 MD2 R253 10K
7
7
RKCK0n
RMCKE N12
CK
CKE
DQ2
DQ3 B5 MD3 T S U26 N.C
C2 MD4 26 37
DQ4 MD5 CE VCC PW_D3.3V
7 SDRAS M2 RAS DQ5 D3 7 PROMOEN 28 OE
L2 D2 MD6 11 13 R254 0
7 SDCAS CAS DQ6 7 PROMWEN WE NC1
L3 E2 MD7 12 B NS
7 SDWE WE DQ7 RP
N2 K13 MD8 R255 0 14 29 D0
7 SDCLK CS DQ8 NC2 D0
K12 MD9 B NS 47 31 D1
DQ9 MD10 BYTE D1 D2 C301 + C302 C303 C304
7 MDM0 B3 DM0 DQ10 J13 D2 33
H12 J12 MD11 A1 25 35 D3 47uF/16V 100nF 100nF 100nF
7 MDM1 DM1 DQ11 A0 D3
H3 G13 MD12 A2 24 38 D4 T B B B
7 MDM2 DM2 DQ12 A1 D4
B12 G12 MD13 A3 23 40 D5 S S S S
7 MDM3 DM3 DQ13 A2 D5
B2 F13 MD14 A4 22 42 D6
7
7
MDQS0
MDQS1 H13
DQS0
DQS1
DQ14
DQ15 F12 MD15 N.C A5 21
A3
A4
D6
D7 44 D7
H2 F3 MD16 A6 20 30 D8
7 MDQS2 DQS2 DQ16 A5 D8
B13 F2 MD17 A7 19 32 D9
7 MDQS3 DQS3 DQ17 A6 D9
G3 MD18 R256 A8 18 34 D10
MA0 DQ18 MD19 1K A9 A7 D10 D11
N5 A0 DQ19 G2 8 A8 D11 36
MA1 N6 J3 MD20 B A10 7 39 D12
MA2 A1 DQ20 MD21 NS A11 A9 D12 D13
M6 A2 DQ21 J2 6 A10 D13 41
MA3 N7 K2 MD22 A12 5 43 D14
A3 DQ22 A11 D14
l
MA4 N8 K3 MD23 A13 4 45 D15
MA5 A4 DQ23 MD24 A14 A12 D15
M9 A5 DQ24 E13 3 A13
MA6 N9 D13 MD25 A15 2 27 PW_D3.3V
MA7 A6 DQ25 MD26 A16 A14 GND1
N10 D12 1 46
tia
MA8 A7 DQ26 MD27 A17 A15 GND2
N11 A8/AP DQ27 C13 48 A16
MA9 M8 B10 MD28 A18 17
MA10 A9 DQ28 MD29 A19 A17
L6 A10 DQ29 B9 16 A18 RY/BY 15
MA11 M7 C9 MD30 9 10 R258 R257
MA12 A11 DQ30 MD31 NC3 NC4 10K 10K
L9 RFU1 DQ31 B8
M10 B B
7 MA[12:0] RFU2
C M29W800DT-70/b S S C
N4 M13 B
7 MBNK0 BA0 MCL
M5 S CON13
7 MBNK1 BA1
1 1
HY5DU283222AF R259 22 B S 2
T 2
3 3
S ICEn
HDR_3X1
T NS
en
DDR_2.5V
PW_D3.3V JP2
G11
C11
H11
C10
C12
E11
E12
K11
F11
L12
L13
L11
J11
M3
M4
G4
C4
H4
N3
D7
D8
C3
C5
C7
C8
* NOTE
E4
E3
K4
F4
L4
L7
L8
1 2
J4
A1 1 2
3 3 4 4
U25B 5 6 1-2 : SELECT FLASH
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
T D0 5 6 D8
7 7 8 8
S D1 9 10 D9 2-3: SELECT PROMJET
D2 9 10 D10
11 11 12 12
D3 13 14 D11
HY5DU283222AF 13 14 D4
15 15 16 16
D12 17 18 D5
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
17 18
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
D13 19 20 D6
id D14
D15
21
23
25
19
21
23
20
22
24
22
24
26
D7
A17
B4
B11
D4
D5
D6
D9
D10
D11
E5
E6
E7
E8
E9
E10
F5
F6
F7
F8
F9
F10
G5
G6
G7
G8
G9
G10
H5
H6
H7
H8
H9
H10
J5
J6
J7
J8
J9
J10
K5
K6
K7
K8
K9
K10
L5
L10
A15 25 26 A16
27 27 28 28
A13 29 30 A14
A11 29 30 A12
31 31 32 32
A9 33 34 A10
33 34
35 35 36 36
DDR_2.5V 37 38
37 38
39 39 40 40
A19 41 42 A20
nf
A8 41 42 A18
43 43 44 44
A6 45 46 A7
C305 C306 C307 C308 C309 C310 C311 C312 C313 A4 45 46 A5
B
47 47 48 48 B
100uF/16V 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF A2 49 50 A3
51
52
T B B B B B B B B 49 50
S S S S S S S S S
51
52
HDR_25X2
DDR_2.5V T
NS
7 A[20:1]
Co
1.27mm X 2.54mm
C314 C315 C316 C317 C318 C319 C320 C321 N.C
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
B B B B B B B B
S S S S S S S S
I
2
C
A
d
d
r
e
s
s
=
4
0
h
(
P
o
r
t
2
)
PW_D3.3V
3.3V(St-by)
U24
C453
6 8 100nF 3.3V(St-by)
3,7,10 SCL1 SCL VCC
5 T
3,7,10 SDA1 SDA S U40
1 7 C244 1 8
A0 WP 100nF R538 100 B NS 2 VDD VSS R539 0 B NS
2 A1 5,7,10 SDA2 GP5 GP0 7 FSCART_ID 7,10
3 4 T R540 100 B NS 3 6 R541 0 B NS
A2 GND 5,7,10 SCL2 GP4 GP1 HSCART_ID 7,10
A S 4 5 A
GP3 GP2
24LC256 7 Reset_Debug Reset_Debug R543 0 B S RESET_PW
RESET_PW 7
T PIC12F675
I
2
C
A
d
d
r
e
s
s
=
a
0
h
(
P
o
r
t
1
)
S T S
SOP type
Date
CONFIDENTIAL Friday, February 10, 2006
Title Sheet 8 of 10
Size Rev Document Number
C A1 <Doc>
8 Memory_Flash&DDR Note
Designer LAB 3
Address
5 4 3 2 1
5 4 3 2 1
Supply_12V
3 U62
NC Supply_5V Stby_5V(Supply) Stby_5V U61 FB51 5Vcc RC1117_3.3V FB54 B S VADC3.3V
GND1 4
5 RC1117_2.5V FB_50_600mA PW_D2.5V B S FB_50_600mA
+5VDD/4A FB88 B S B S
+5VDD/4A-2 6 3 VI VO 2
7 FB_50_3A 3 2
GND
Power Filter
+5VST/1A EC15 + BC5 T + VI VO FB56 B S VDVI3.3V
8 4
GND
GND2 Vbr-A 470uF/16V 100nF S C864 BC3 BC4 C760 + C765 C772 + C774 TAB C777 C775 + FB_50_600mA
BRI-ADJ 9 TAB 4
10 T B 470uF/16V 100nF 10nF C764 + C767 22uF/16V 100nF 22uF/16V 100nF 100nF 100uF/16V
1
GND3 BL_VS_ON S S T B B 22uF/16V 100nF C768 EC9 T S T T B B T
11
1
BL ON/OFF R577 100 T S S S S T B 100nF 100uF/16V S S S S S FB58 T S VMPLL3.3V
D CONTROL 12 Relay_ON(LCD_LG) D
SC_GND SC_GND S S B T FB52 FB_50_600mA
SMW200-12/YEONHO L15 S S FB_50_600mA DDR_2.5V
T S 33uH_3A B S
SC_GND T NS
LVDS Power FB59 B S VPLL3.3V
Power1 C770 + C769
ADC FB_50_600mA
T 2.5V ; 600mA Requirement 100nF 22uF/16V
DVI
Supply_5V FB89 S 5Vcc B T
FB_50_3A (include Power for DDR) S S Master PLL
Supply_5V PLL FB60 B S VDDP3.3V
CON36 FB87 FB_50_600mA
FB_50_3A
Output
ACD 1
2 C837 + C838 T + U63 FB55 TTX Power
RLY_ON 470uF/16V 100nF S C865 C839 C840 Stby_5V RC1117_3.3V 3.3V(St-by) FB_50_600mA PW_D3.3V FB62 T S
5VSB 3
4 Supply_12V T B 470uF/16V 100nF 10nF B S B S FB_50_600mA SDA3.3V
GND S S T B B
VS_ON 5 3 VI VO 2
6 S S S
GND
5VD
NC 7 SC_GND SC_GND TAB 4 + C771
C773 + C776 C778 EC10 22uF/16V
A-5045-7A 22uF/16V 100nF 100nF 100uF/16V T
1
T NS SC_GND T B B T S U65 MST_2.5V
Power2 S S S S FB24 5Vcc RC1117_2.5V FB64 B S
L16 1k_OHM_200MA PW_A3.3V B S FB_50_600mA
(for LG PDP only) 33uH_3A B S 3 2 VDDC2.5
Supply_12V T NS 12Vcc VI VO
GND
3.3V ; 100mA Requirement TAB 4 FB65 B S
+ C779 C784 + C785 C786 C787 FB_50_600mA
22uF/16V 22uF/16V 100nF 100nF 22uF/16V SDA2.5AV
1
FB75 T T B B T
Supply_AMP FB_50_3A + S S S S S FB66 T S
l
C800 + C799 T C866 C801 C802 FB_50_600mA
CON31 470uF/16V 100nF S 470uF/16V 10nF 100nF SDA2.5V
1 T B T B S
B
1 S S S S U64
2
tia
2 Stby_5V AP1117E18-SOT223 PW_D1.8V
3 3
4 4 SC_GND SC_GND B S Digital Core
3 VI VO 2 TTX
5045-04A
GND
T S 4
TTX
L4 C780 + C781 TAB C783 + C782 FB63
C GND_AMP 33uH_3A 22uF/16V 100nF 100nF 47uF/16V FB_50_600mA PW_A1.8V C
1
T NS T B B T T S
Power3 Supply_AMP AMP_Vcc S S S S
(Audio Power) EC12
FB83 100uF/16V
C841
100nF
C842
10nF
FB_50_3A
T
EC23
1000uF/50V
T
S
TW9919 Power
B B S T 5Vcc U67
TW_3.3V VDDE_3.3V
S S S RC1117_3.3V FB70 B S
1.8V ; 800mA Requirement B S FB_50_600mA
en
3 VI VO 2
GND_AMP GND_AMP
GND
GND_AMP 4
C791 + C793 TAB C794 C792 + FB72 B S AVDP_3.3V
3.3V(St-by) U74 22uF/16V 100nF 100nF 100uF/16V FB_50_600mA
1
Stby_5V AP1117E18-SOT223 PW_D1.8V T B B T
Open or High For
B S S S S S
Max Lum For LG
2
Supply_33V Tuner_33V 3 2
R598 VI VO FB74 B S V-MEM_3.3V
GND
4.7K 4 FB_50_600mA
T C867 TAB C868 + C869 FB102
S Vbr-A 2 1 I_PWM 7 FB101 100nF 100nF 47uF/16V FB_50_600mA PW_A1.8V
21
1
FB_50_3A B B T T S
R602 R600 EC24 + BC6 T S S S
4.7K 100 100uF/16V 100nF NS
MST_2.5V
T T T T
NS NS
id NS NS
1
GND
4 FB73
C870 + C877 TAB C878 EC25 FB_50_600mA VDD_2.5V
Relay_ON(SS) Relay_ON(LCD_LG) GND_AMP SC_GND SC_GND 22uF/16V 100nF 100nF 100uF/16V T S
1
nf
T T T T
High : Power OFF High : Power On NS NS NS S
B Low : Power ON Low : Power Off B
Stby_5V
2
POWERON/OFF
R588 R589
High : Power ON 10K 1.2K
T T
Low : Power OFF S S
MSPG34XX POWER
1
Co
S S 1 3
FB69
4
C788 + C789 C790 EC13 FB_50_600mA CC_5V
100uF/16V 100nF 100nF 100uF/16V B S
4
T B B T
NS NS NS S
Relay_ON(SS) 2 1Relay_ON(LCD_LG)
R667
1.2K
T NS
GND
TAB
C795 + C796 C797 EC14 BC2
2
4
R640 R641 R642 T B B T B
High : Power ON 10K 4.7K 4.7K S S S S S
T T T
Low : Power OFF S NS S
1
BL_VS_ON
3
1 Q15 C843
R643 MMBT3904 10nF
3
10K T T
2
7 DVDIR 59 60 R682
57 58 0
55 56 R604 R605 R606 R607 R608 Stby_5V T S
TXD_DTV RXD_DTV
53 54 10K 10K 10K 10K 10K
51 52 I2S_OUT 6 T S T S T S T S T NS FB104
6 I2S_DTV_DATA Stby_5V
49 50 I2S_DTV_CLK 6 1k_OHM_200MA
D 6 I2S_DTV_WS D
47 48 SPDIF_OUT 6 AV1_DET T NS
7 SVIDEO2_DET
1
3 DTV3_Pr 45 46 R684 0 C49 Stby_5V
3 DTV3_Pb 43 44 T S DTV3_Y 3 AV2_DET D34 D35 100nF C38
41 42 BAV99 BAV99 B 100nF C871
2
39 40 AV3_DET_ID T T S Stby_5V B S 18pF
NS NS U1 T NS
6,7 SCL3_5 37 38 SDA3_5 6,7 1 2
6 MUX_SEL 35 36 MUX_SEL2 6 SVIDEO1_DET
16
MUX_R 33 34 MUX_L 16 VCC C1P 1
Tuner_33V 31 32 SVIDEO2_DET FB105 T S 2 3 U4
JACK4 1k_OHM_200MA VP C1M RX
29 30 12 13
VDD
6 TV_R_OUT TV_L_OUT 6 RXD X0 X RX 7
27 28 MUX_9V d D 13 RIN1 ROUT1 12 RXD RXD_DTV 14 X1
6 TUNER_SIF 25 26 f F 8 RIN2 ROUT2 9 15 X2
23 24 Stby_5V E 11
TUNER_CVBS 4 e X3
Stby_5V 21 22 c C 14 T1OUT TIN1 11 TXD
19 20 CH1_IN 4 B 7 10 1 3 TX TX 7
7 AV2_DET b TOUT2 TIN2 TXD Y0 Y
4 AV2_CVBS_IN 17 18 FB106 T S 5
TXD_DTV Y1
7 SVIDEO1_DET 15 16 LU1_IN 4 C808 C809 C810 TC38-066-01 1k_OHM_200MA 6 4 2
100uF/16V 100nF 10nF T VM C2P Y2
4 AV1_CVBS_IN 13 14 15 GND C2M 5 4 Y3
7 AV1_DET 11 12 T T T S 6
H_CVBS_OUT 4 INH
9 10 S S S 2 1 7 RS232_SEL RS232_SEL 10
7,8 HSCART_ID FSCART_ID 7,8
VSS
VEE
A
4 HS/AV3_CVBS 7 8 FS_CVBS/LU2 4 9 B
1
R638 5 6 R639 C46 C47 C48 C50 B MAX232A C41 R668
10K 3 4 10K 10nF 10nF 100nF 100nF S 100nF 10K
4 SCART_R SCART_FB 4
7
B 4 SCART_G 1 2 B T T B B B S T
SCART_B 4
2
S S R669 NS NS S S NS 4052
0 T NS T
SH1605-230_female 7,8 FSCART_ID NS
ID2mstar 3
l
T S
tia
IR Port M2
C 3.3V(St-by) R620 C
CON32 5V_Amux 0
1 FB107 T
2 1k_OHM_200MA S
3.3V(St-by) 7 IRRCVR
3 R670 R671 B NS GND_AMP
7 LED_R
4 C872 4.7K 4.7K 5V_Amux MSP_5V M3
7 LED_G
5 330nF T T
T NS NS NS C873
R688 R689 R690 12505WS05A 18pF R623
MUX_R
en
10K 10K 10K T NS B NS 0
B B B T
MUX_L
NS NS NS S
16
C874 U75 GND_AMP
330nF R672 R673 12 13 M4
VDD
X0 X AV_R 6
T NS 4.7K 4.7K 14
C879 C880 C881 B B X1
15 X2
100nF
B
100nF
B
100nF
B Side Port (AV3 & S-Video2) NS NS 11 X3
R621
0
NS NS NS 1 3 T
Stby_5V Y0 Y AV_L 6
5 S
CON37 CON34 Y1 R677
2 Y2
1 2 5V_Amux 4 0 T S M1
6 AV3_DET_ID 5,7 Y3
7 DVD_3 5 3 4 HS/AV3_CVBS 4 6 INH MUX_R AV_R 6
5 6 10
7 DVD_2
VSS
VEE
4 R674 R675 A R619
7 DVD_1 3 HS/AV3_R 7 8 FS_CVBS/LU2 4 9 B
T S T POINT R TP178 9 10 C876 4.7K 4.7K R676 0
2 CH2_IN 4 MUX_L AV_L 6
T S T POINT R TP179 C857 330nF T T 10K T
7
1 100nF CON10A T NS NS NS B NS 4052 R678 S
T NS T NS NS 0 T S
HS/AV3_R
B SC_GND
12505WS06 M5
HS/AV3_L
T NS C875
330nF R679 R680 R622
T NS 4.7K 4.7K 0
nf
B B T
NS NS S
B B
I
2
C
A
d
d
r
e
s
s
=
4
0
h
(
P
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t
2
)
13
7 IRRCVR 12 IR Control Zig points
7 SOURCE 11 3.3IR C882
7 MENU 10 100nF
9 T S T POINT R TP161 B S U77
7 POWER 8 T S T POINT R TP162 1 8
7 CH- 7 VDD VSS
T S T POINT R TP163 R691 100 B S 2 7
7 VOL- 6 IRRCVR 7 5,7,8 SDA2 GP5 GP0
T S T POINT R TP164 R692 100 B S 3 6
7 VOL+ 5 SOURCE 7 5,7,8 SCL2 GP4 GP1
T S T POINT R TP165 4 5 DVDIR
7 CH+ 4 MENU 7 GP3 GP2
T S T POINT R TP166
3 T S T POINT R TP168
7 LED_R 2 POWER 7 PIC12F675
T S T POINT R TP167
7 LED_G 1 CH- 7
T S T POINT R TP169 B S
VOL- 7
12505WS14A T S T POINT R TP170
VOL+ 7 SOP type
T S T S T POINT R TP171
CH+ 7
T S T POINT R TP172 IRRCVR
A T S T POINT R TP174 R695 100 B NS A
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LED_R 7
T S T POINT R TP173
LED_G 7
T S T POINT R TP175
DVD_3 7
T S T POINT R TP176
SM
DI
AC
5O
5
0M
0;
;4
2h
2
h
3.3V(St-by) DVD_2 7
T S T POINT R TP177
DVD_1 7
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3.3V(St-by) 3.3V(St-by)
0
CON26
CON27 CON28
MEP
SE
TPn
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8
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1
3,7,8 SCL1 2 1 1
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SD
PA
x4
5 4 3 2 1
5 4 3 2 1
Stby_5V
Stby_5V D21 D22
D9 D10 D11
MMBZ5V6ALT1
T NS
MMBZ5V6ALT1
T NS Mechanical EMI용 저항
//BAV99//BAV99 T
BAV99
2
T NS T NS NS
2
M1 M2
3
3 R619 R620
0 0
Detect : HIGH T T
S S
1
AV1_DET 1
1
M3
M4
AV2_DET 1
JACK4
10
D D
4
RCA-623(GBRx2) R623
3 9 R621 0
Y Y AV2_CVBS_IN 1
0 T
T S
2 8 FB14 T S R35 1K S
AV2_L_IN 1
W W 1K_OHM_200MA T S GND_TU
GND_TU
1 7 FB15 T S R36 1K
R R AV2_R_IN 1
1K_OHM_200MA T S
TOP Side
5
6
11
2
NS TUNER_SIF 25 26
23 24 TUNER_CVBS
Stby_5V 21 22 + +
3 3 19 20 Svideo1_C C17 C18 C23 C19 C20 C21
7 AV2_DET
4 AV2_CVBS_IN 17 18 100uF/16V 100nF 10nF 100uF/16V 100nF 10nF
SVIDEO1_DET 15 16 Svideo1_Y T T T T T T
13 14 S S S S S S
l
AV1_CVBS_IN
AV1_DET 11 12
1
1 9 10
AV1_CVBS_IN 1 7 8
5 6
tia
3 4
FB12 T S R29 1K 1 2
AV1_L_IN 1
5V_Amux
FB107
1k_OHM_200MA
R670 R671 T S
Stby_5V C872 22K 22K 5V_Amux
en
Stby_5V 5Vcc
330nF T T
T S S S C873
D17 D18 D20 AV1_R_IN 18pF
T
BAV99 T
BAV99 T
BAV99 T S
NS NS NS AV1_L_IN
16
C874
SVIDEO1_DET 1
330nF R672 R673 12 13
VDD
X0 X MUX_R
T S 22K 22K 14
T T X1
15 X2
S S 11 X3
Svideo1_C 1 Y0 Y 3 MUX_L
Top view 5 Y1
7
2 Y2
11 D 12 5V_Amux 4 U75
1 C Y 2
15
id Svideo1_Y
6 MUX_SEL2
6
10
Y3
INH
4052
S
VSS
VEE
3 1 6 8 10 R674 R675 6 A T
3 4 MUX_SEL 9 B
5 13 14 C876 22K 22K
330nF T T
7
4 2 7 9 11 C60 C61 T S S S
6
10
Tuner_33V_Inlet Tuner_33V
Tuner Block
Co
R15 0 AS R16
T 100 T S
NS TU1 ANT TSCL SCL3_5
12Vcc FI1 Tuner_33V
SDOS-1608-472M D19 T S R18 R19 TSDA
T S RB160L-60 (SOD-106) 1.2K T S 4.7K R17 SDA3_5
1 2 2 1 T C28 C29 100 T S
S 33pF 33pF
+ C26 + C27 T T
U1 R20 5 22uF/16V 47uF/50V S S
N.C5
1 DRIVE FB 8 0 T T GND_TU
T 6 NS S
N.C1
2 NC1 NC4 7 S GND_TU Tuner_5V
+ C25
N.C2 7 GND_TU GND_TU Tuner_5V Tuner_5V
3 6 4.7uF/50V(4X5.3)
NC2 NC5 T R25
RF ACC 8
4 5 S R24 15K
Vin GND 36K AS C39 + C40 C36 T S T
SAS 9
3
BA6161F-SOP8 T 22pF 470uF/16V 47uF/16V S Q1
C35 + C38 T GND_TU NS 20 20 SCL 10 TSCL T T CVBS 1 MMBT3904
33uF/16V 100nF S S S T S
+
2
21 SDA
S S GND_TU GND_TU GND_TU R26 56 100
5Vcc L16 22 12 Tuner_33V 75 T R23 T R27
22 MB
GND_TU GND_TU 33uH_3A T S 22K S R28 75
T NS 23 13 FB10 T S S T 1K T S
23 SIF OUT TUNER_SIF
FB_50_600mA S T S
VT 14
A FB11 GND_TU A
FB_50_3A T NS GND_TU AUDIO 15 GND_TU
R31 C45 C46
16 TP2 10K 100nF + 100uF/50V(8X10)
12Vcc U3 Tuner_5V AFT T S T T T
T NS 17 CVBS S S S
VIDEO
1 INPUT OUTPUT 3
GND_TU
GND_TU GND_TU GND_TU GND_TU
GND_TU
5 4 3 2 1
[NP-42S5**] TANGO TRI-BOM 06. 03. 20
General Instructions
4. Conditions :
The inspection is conducted at a normal temperature of 20℃and a normal humidity of 65% and unless
otherwise specified, a higher temperature (15 - 35℃) and humidity (45 - 85%) may be permitted.
5. . Notes :
If you have any problems or require additional information with regard to this inspection,
contact our Institute.
WoosungNextier Corp.
6. Inspection of Standardization
(2)External Speaker
(W x H x D)
2 Weight 5Kg(L + R) 3Kg(L + R)
3 Freq. Response 0.045 ~ 20 KHz Speaker
Output
4 T.H.D Max. : 5 % 400Hz 10W
5 Output 10 + 10 W RMS
6 Impedance 8 + 8 Ω
7 Output 87 dB/W/M
sound pressure
7.2 Inspection of Standardization
1) TEST PATTERN
(1) MONO SCOPE
ITEM Condition Standard
MONOSCOPE
Resolution 400 (H) or Higher
Normal Screen Mode
PRE SHOOT ″ ″
More than±120lines and less than
Horizontal
Synchronous Lead-in ±480lines
MONOSCOPE
Range More than –15 lines and less than –9
Vertical
lines
<MONO SCOPE>
(2) Stair 10-Steps
- Check the left/right black/white patterns for saturation (Brightness, Contrast test)
- Should be saturated less than Step 2 black and less than step 2 white to the left and to the right.
- Check if any unnecessary chrominance signals other than black and white enter the picture.
- No distortion or noise on the screen
Magenta
Yellow
Yellow
White
Green
Green
Black
White
Green
Cyan
Cyan
blue
Red
Red
(8) Crosstalk
- Check if burst lines are properly displayed.
- Check for any distortion or noise on the screen.
< Crosstalk>
- Check to ensure that the corresponding areas at the top, bottom, right and left are balanced,
based on the vertical line in the center.
- Check if the central horizontal line matches the physical center of the PDP panel.
- Check for any distortion or noise on the screen
(11) SMPTE RP-133
- Check the cross patterns for any loss.
- Check if there is any problem dealing with high frequencies.
- Check multi-burst for its signal frequencies.
- Check for any distortion or noise on the screen.
]
< SMPTE RP-133>
(12) 256Gray+RGBW Color Bar
- Check each color bar for the boundary nesting.
- Check if the color of the color bar is properly displayed.
- Check for the saturation areas.
- Check if any horizontal or vertical noise occurs.
2) Speaker Output
Item Condition Standard
Sound: 1KHz, MODULATION over 30%
Signal/Noise
Picture: Black 37dB or Higher
Ratio
50mW output
Sound : 1KHz, MODULATION over 30%
Signal/Buzz
Picture: COLOR BAR 35dB or Higher
Ratio
50mW output
Max. Audio Sound : 1KHz, 100% MODULATION 9 W or higher
output Volume : Max. A resistance of 8Ω
3) Input
Input Condition Standard
Digital RGB
No distortion or noise on the screen
HDMI Input Audio
Audio In No distortion or noise in the audio output
Video Input V Signal No distortion or noise on the screen
Y Signal
No distortion or noise on the screen
S-Video Input C Signal
Audio In No distortion or noise in the audio output
Y
No distortion or noise on the screen
Component Input Pb, Pr
Audio In No distortion or noise in the audio output
R,G,B
No distortion or noise on the screen
R,G,B Input H,V
Audio In No distortion or noise in the audio output
No distortion or noise on the screen
Antenna In RF Signal
No distortion or noise in the audio output
Input Sources
TV
.
AV1 (AV2)
(4) Check if the video signals display properly on the screen for each mode.
(5) Check if there is any problem with the audio output by pressing the CONTROL key or the VOL key on
the remote control.
* The video signals should be tested for both NTSC and PAL systems respectively, as they have
different signaling routes according to the broadcasting system.
.
5) S-VIDEO Input
(1) Connect the video input signals to the S-VIDEO Input terminals using the S-Video cable..
(2) Connect the Audio Input terminal (Video1’s Audio Port) to the Audio Output terminal
of the video signal generator using the RCA audio cable
(3) Turn on the power by pressing the front key or the POWER key on the remote control.
(4) Select the “S-Video” port using front panel button or Remote Controller..
Input Sources
TV
S-VIDEO
.
.
(5) ) Check if the video signals display properly on the screen for each mode.
(6) Check if there is any problem with the audio output by pressing the CONTROL key or the VOL key on
the remote control.
6) COMPONENT Input
(1) Connect the Component Video Input terminal to the video signal generator’s output terminal
using the RCA cable
(2) Connect the Audio Output terminal of the video signal generator to the
Component Audio Input using the RCA cable
(3) Turn on the power by pressing the front key or the POWER key on the remote control.
(4) Select the “Component” port using front panel button or Remote Controller..
Input Sources
TV
.
COMPONENT1 (2)
.
(5) ) Check if the video signals display properly on the screen for each mode.
(6) Check if there is any problem with the audio output by pressing the CONTROL key or the VOL key on
the remote control..
(Check if there is any problem with the signals from the Component/HDMI Mode Table.)
Horizontal Frequency Vertical Frequency Pixel Clock
7) RGB Input
(1) Connect the Output terminal of the RGB video signal generator to the RGB Input
using the 15 Pin D-Sub cable
(2) Connect the Output terminal of the RGB audio signal generator to the RGB Audio Input
using the 3.5mm Stereo audio cable.
(3) Turn on the power by pressing the front key or the POWER key on the remote control.
(4) Select the “PC” port using front panel button or Remote Controller..
Input Sources
TV
.
PC
(5) Switch to RGB mode and check if the RGB video signals are properly displayed on the screen.
(Check if there is any problem with the signals from the RGB Mode Table.)
(6 ) Check if there is any problem with the audio output by pressing the CONTROL key or
the VOL key on the remote control..
Horizontal Frequency Vertical Frequency Pixel Clock Frequency
Mode Resolution
(kHz) (Hz) (MHz)
Input Sources
TV
.
HDMI
PC
(5) Switch to HDMI mode and check if the HDMI video signals are properly displayed on the screen.
(Check if there is any problem with the signals from the Component/HDMI Mode Table.)
(6 ) Check if there is any problem with the audio output by pressing the CONTROL key or
the VOL key on the remote control..
9) Picture Menu
(1) Enter into “Picture Menu” by pushing “front Key” or “Menu Key of Remocon.”
Picture
Size
Picture Mode
Brightness
Contrast
Sharpness
Tint
Color
Color Tone
(2) Check that any mode you can control is O.K by pushing front key or key of remocon.
- Size : Wide/Panorama/Zoom/4;3/14:9
- Picture Mode : Standard/Movie/Mild/Custom/Dynamic
You can enter into “Custom Mode” by pushing “Enter Key” in Picture Mode.
-- Brightness
-- Contrast
-- Sharpness
-- Tint
-- Color
- Color Tone : Choose White Balance (Norma;/Warm2/Warm1/Cool2/Cool1)
10) Channel
- Setting TV Channel
11) Sound Menu
(1) Enter into “Sound Menu” by pushing front key or “menu key” of remocon.
Sound
Sound Mode
Equalizer
Auto Volume
(2) Check that any mode you can control is O.K by pushing front key or key of remocon.
- Sound Mode : Standard / Music / Movie / Speech / Custom
You can enter into “Custom Mode”by pushing “Enter key” in Sound mode.
- Equalizer : Audio control for each Volume, Left/Right Balance 및 100Hz, 300Hz, 1kHz,
3kHz, 10kHz
- Auto Volume : Setting volume level for each broadcasting
PIP
PIP
Input Source
Size
Position
Swap
(2) Time : You can enter into Sub Menu by pushing “Enter Key”.
Clock : Setting on current time
On Timer : TV is automatically on when it is appointed.
Off Timer : TV is automatically off when it is appointed.
Sleep Timer : TV is automatically when it is Off/30/60/90/120/150/180
On Time Channel : The appointed channel after it is On Timer
On Volume : The appointed volume after it is On Timer
(3) Blue Screen : Setting “Blue” color in screen when it is no signal.
(4) Language : Choosing OSD
(5) DNR : Digital Noise Reduction
(6) Screen Wiper : Deletion for the Screen Noise of PDP
(7) Pixel Shift : Protection for the Screen Noise
(8) Caption :
(9) V-Chip :
16) Remocon Function Key Test
(1) MUTE : Once it is pushed there is no sound.
Once it is pushed again it return to default.
(2) Source Select
- TV : TV Hotkey
- PC/HDMI : PC/HDMI Hotkey
- AV.SEL : Component, S-Video, Video Source toggle
- SOURCE
(3) Screen Function
- PIC.SIZE : Controlling Screen Size
- PIC.MODE : Controlling Screen Mode
- STILL : Screen Still
(4) Audio Function
- MTS : To choose Mono, Stereo or Bilingual
- S.MODE : Controlling the audio mode
- AVC : Auto Volume control Hotkey
(5) SLEEP : Sleeper Timing
(6) PIP Function
- PIP : PIP On/Off
- P.INPUT : PIP Source
- P.POSITION : Adjusting position when PIP size is small
- P.SIZE : Adjusting PIP Size
- P.SWAP : Main / Sub Swap
(7) Number Key & PRE-CH
- 1~9 : Choosing the broadcasting channel number
- PRE-CH : Moving to the previous channel
- CH.ADD : Save/Delete the present broadcasting
(8) Direction Key & Menu/EXIT
(9) KEY LOCK : Locking the button of TV System
(10) POWER : POWER On/Off
7.4 Out Going Specification
1) Menu Mode Setting
(1) TV, Video, S-Video, Component Input
PAL
B/G D/K N M I
SECAM
B/G D/K I L
Country KOREA
USA
CANADA
JAPAN
PDP TV Firmware Update
Remove
Power Cord
You must do system reset after updating the firmware of main board.
1. Calibration
2. Option Table
3. Color Control
4. Device Adjustment
5. Heatrun
6. Version
7. Reset
7. Reset
Press Enter To Reset Factory Default
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