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# PART A

EXPERIMENT: 1

## AIM: To verify the truth tables of various logic gates

COMPONENTS REQUIRED:
 Trainer kit.
 Connecting patch chords.
 IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, IC 7404, IC 7486

Procedure:
1. Insert the IC into the IC checker, check for its functioning.
2. Write down the pin numbers of the IC/Logic diagrams.
3. Place the IC in IC holder of trainer kit.
4. Make the required connections according to the pin/logic diagram.
5. Turn on the IC Trainer Kit.
6. verify the truth table

1. AND gate (IC 7408):- The AND gate is an electronic circuit that gives a high output (1) only if all its
inputs are high.

2. OR gate (IC 7432):- The OR gate is an electronic circuit that gives a high output (1) if one or more
inputs are high.

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3. NOT gate (IC 7404):- The NOT gate is an electronic circuit that produces an inverted version of the
input at its output. It is also known as an inverter.

4. NAND gate (IC 7400):- The outputs of all NAND gates are high if any of the inputs are low. The
symbol is an AND gate with a small circle on the output.

## 5. NOR gate (IC 7402)

The outputs of all NOR gates are low if any of the inputs are high.The symbol is an OR gate
with a small circle on the output.

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6. EXOR gate (IC 7486):- The 'Exclusive-OR' gate is a circuit which will give a high output if
either, but not both, of its two inputs are high.

INPUTS OUTPUT
A B C Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

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INPUTS OUTPUT
A B C D
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

RESULT:
Teachers signature: ________________________

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EXPERIMENT: 2
SIMPLIFICATION, REALIZATION OF BOOLEAN EXPRESSIONS USING LOGIC
GATES/UNIVERSAL GATES.

AIM : To simplify the given expression and to realize it using basic gates/ universal gates.

## COMPONENTS REQUIRED: IC 7400, IC 7408, Patch Cords & IC Trainer Kit.

BRIEF THEORY: Using karnaugh maps (K-maps) Boolean functions are simplified and then are realized
using the various gates. K-maps are mostly used for the functions having up to five variables beyond which
it is very cumbersome. In an n-variable K-map there are 2n cells. Each cell corresponds to one of the
combination of n variable, since there are 2n combinations of n variables.

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

## 1) Y = ABCD. Implement this equation using NAND gates.

TRUTH TABLE
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
Fig:- logic diagram
1 1 1 0 1
1 1 1 1 0

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2) Y = A + B + C + D Implement this equation using NOR gates

Truth Table

A B C D Y
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
Fig:- Logic diagram 1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

Result:

Teacher’s Signature:______________________________
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EXPERIMENT: 3
. REALIZATION OF HALF/FULL ADDER AND HALF/FULL SUBTRACTORS
USING LOGIC GATES.

## AIM: To realize a suitable circuit by using NAND gates of the following

2) Half subtractor and Full subtractor.

## COMPONENTS REQUIRED: IC 7400, Patch Cords & IC Trainer Kit.

PROCEDURE:
 Check the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

THEORY:

Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B, is called a
half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the other is the carry
bit, C. The Boolean functions describing the half-adder are:
S =A  B
C=AB

Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry bit
from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits, A and B,
and a carry-in bit, Cin , is called a full-adder. The Boolean functions describing the full-adder are:
S = (x  y)  Cin C = xy + Cin (x  y)

Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B ) produces a difference
bit D and a borrow out bit B-out. This operation is called half subtraction and the circuit to realize it is called
a half subtractor. The Boolean functions describing the half- Subtractor are:
S =A  B
C = A’ B
Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A produces a
difference bit D and a borrow out Br bit. This is called full subtraction. The Boolean functions describing the
full-subtracter are:
D = (x  y)  Cin
Br= A’B + A’(Cin) + B(Cin)
TRUTH TABLE
INPUTS OUTPUTS
A B S C

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
k-map for sum and carry:
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sum: carry:

S= C=

Logic diagram

TRUTH TABLE
k-map for sum and carry:
INPUTS OUTPUTS
sum:
A B Cin S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0 S=
0 1 1 0 1
1 0 0 1 0 carry:
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

C=

Logic diagram:

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III) HALF SUBTRACTOR
TRUTH TABLE
INPUTS OUTPUTS
A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

## k-map for sum and carry:

difference: Borrow:

D= Br=

Logic diagram:

4) FULL SUBTRACTOR
INPUTS OUTPUTS
TRUTH TABLE
A B Cin D Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
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1 1 0 0 0
1 1 1 1 1
K-map for sum and carry:
Difference: Borrow:

D= Br=

Logic diagram:

Result:

Teachers signature:_________________________
EXPERIMENT: 4
REALIZATION OF PARALLEL ADDER/SUBTRACTORS USING 7483 CHIP

AIM: To design and set up the following circuit using 4-bit binary adder/subtractor IC 7483.
ii) 4-bit binary subtractor.

## COMPONENTS REQUIRED: IC 7483, IC 7486, Patch Cords & IC Trainer Kit.

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
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 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

MSB LSB

Cin

INPUT A3 A2 A1 A0

B3 B2 B1 B0

OUTPUT Cout S3 S2 S1 S0

## 1) 4-Bit Binary Parallel adder:-

Example : 9+2=11 (1011)

 9 is realized at A3 A2 A1 A0 = 1001
 2 is realized at B3 B2 B1 B0 = 0010
Sum = 1011

## Subtraction is carried out by adding 2’s complement of the subtrahend.

Example : 9 – 5 = 4 (0100)
 9 is realized at A3 A2 A1 A0 = 1001
 5 is realized at B3 B2 B1 B0 = 0101
 Output of X-OR gate is 1’s complement of 5 i.e 1010
 2’s Complement of 5 is 1010
+ 1 (cin)
= 1011
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 Therefore 1001
+1011
= 1 0100

## In this example Cout is 1 and is ignored.

i) 2 and 9 ii) 6 and 13

Subtract
i) 4 from 7 ii) 5 from 14

Result:
Teachers signature:_________________________

EXPERIMENT: 5
BCD TO EXCESS-3 CODE CONVERSION AND VICE VERSA.

## AIM : To design and set up the following circuit using IC 7483.

i) BCD to Excess- 3.
ii) Excess-3 to BCD.

## COMPONENTS REQUIRED: IC 7483, IC 7486, Patch Cords and IC Trainer Kit.

THEORY: Code converter is a combinational circuit that translates the input code word into a new
corresponding word. The excess-3 code digit is obtained by adding three to the corresponding BCD digit.

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To Construct a BCD-to-excess-3-code converter with a 4-bit adder feed BCD-code to the 4-bit adder as the
first operand and then feed constant 3 as the second operand. The output is the corresponding excess-3 code.
To make it work as a excess-3 to BCD converter, we feed excess-3 code as the first operand and then feed
2's complement of 3 as the second operand. The output is the BCD code.

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

Circuit Diagram

BCD to EX-3
EX-3 TO BCD EX-3 BCD
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
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1 0 1 1
1 1 0 0
Result:

Teachers Signature______________________

Experiment: 6
REALIZATION OF BINARY TO GRAY CODE CONVERSION
AND VICE VERSA

## AIM: To realize Binary to Gray code converter and vice versa.

COMPONENTS REQUIRED: IC 7400, IC 7486, and IC 7408, Patch Cords & IC Trainer Kit.

THEORY:

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PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

## 1) Binary to Gray code conversion using Ex-OR gates.

Binary Gray
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
TRUTH TABLE 0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
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1 1 1 0
1 1 1 1
K-maps: for G0, G1, G2 and G3
K-map For G3: K-map For G2

G3= G2=

G1= G=0

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TRUTH TABLE

Gray Binary
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0
0 0 0 1
0 0 1 1
0 0 1 0
0 1 1 0
0 1 1 1
0 1 0 1
0 1 0 0
1 1 0 0
1 1 0 1
1 1 1 1
1 1 1 0
1 0 1 0
1 0 1 1
1 0 0 1
1 0 0 0

## K-map for B0,B1,B2 and B3

K-map For B3: K-map For B2

B3= B2=

B1= B0=

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Result:

Teachers Signature:________________

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Experiment: 7
MULTIPLEXER AND DEMULTIPLEXER

AIM : To realize
a) 4:1 Multiplexer using gates
b) 1:8 Demux

## COMPONENTS REQUIRED: IC7400, IC 7408, Patch Cords & IC Trainer Kit.

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

4:1 MULTIPLEXER:-

Select Enable
Inputs Outputs
Inputs Input
S1 S0 E I0 I1 I2 I3 Y
X X 1 X X X X 0
0 0 0 0 X X X 0
0 0 0 1 X X X 1
0 1 0 X 0 X X 0
0 1 0 X 1 X X 1
1 0 0 X X 0 X 0
1 0 0 X X 1 X 1
1 1 0 X X X 0 0
1 1 0 X X X 1 1

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1:8 DEMULTIPLEXER:

logic diagram
1:8 DE-MUX using NAND Gates

Truth Table

RESULT:

Teachers Signature____________________

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Experiment: 8
REALIZATION OF PRIORITY ENCODER AND 3:8 DECODER USING IC 74183

## COMPONENTS REQUIRED :IC 74148, IC 74138,Patch chords & IC Trainer Kit.

PROCEDURE :
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

## Priority 8:3 ENCODER:

E1 I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0
1 X X X X X X X X
0 1 1 1 1 1 1 1 1
0 X X X X X X X 0
0 X X X X X X 0 1
0 X X X X X 0 1 1
0 X X X X 0 1 1 1
0 X X X 0 1 1 1 1
0 X X 0 1 1 1 1 1
0 X 0 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1

3:8 DECODER:

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Truth Table

RESULT:

Teachers Signature____________________

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EXPERIMENT: 9
REALIZATION OF ONE/TWO BIT COMPARATOR

## AIM : 1)To realize One Bit Comparator

2) To realize Two Bit Comparator

## COMPONENTS REQUIRED: IC 7400, IC 7410, IC 7420, IC 7432, IC 7486, IC 7402,

IC 7408, IC 7404, Patch Cords & IC Trainer Kit.
PROCEDURE :
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

Inputs Outputs
A> A= A<
A B
B B B
0 0 0 1 0

0 1 0 0 1

1 0 1 0 0

1 1 0 1 0

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K-map for A<B

## 2. TWO BIT COMPARATOR

Inputs Outputs
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

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k-maps:

RESULT:

Teachers Signature:______________________

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EXPERIMENT: 10
FLIP FLOPS

## AIM : Truth Table verification of

1) JK Master Slave Flip Flop.
2) D Flip Flop.
3) T Flip Flop.

COMPONENTS REQUIRED: IC 7408, IC 7404, IC 7402, IC 7400, Patch Cords & IC Trainer Kit.

PROCEDURE :
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

## 1) JK MASTER SLAVE FLIP FLOP

Clock J K Q Comment
Q
No
1 0 0 Qn Qn Change
1 0 1 0 1 Reset

1 1 0 1 0 Set

1 1 1 Qn
Qn

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(c)Logic diagram

3) D FLIP FLOP

Comment
Clock D Q Q
No
0 X Qn Qn Change
1 0 0 1 RESET

1 1 1 0 SET

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3)T Flip Flop

Comment
Clock T Q Q
No
0 X Qn Qn Change
1 0 No change
Qn Qn
1 1 Toggle
Qn Qn
(a) symbol
(b) Truth table

## (c) Logic diagram

RESULT:

Teachers Signature:_____________
RNSIT DIGITAL DESIGN AND HDL LAB
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EXPERIMENT: 10
REALIZATION OF 3 BIT COUNTERS AS A SEQUENTIAL CIRCUIT AND MOD –
N COUNTER DESIGN

AIM: 1)To design and implement3-bit binary asynchronous counters using IC 7476
2)To design and implement3-bit binary synchronous counters using IC 7476
3) To design and implement various counters using IC 7490

COMPONENTS REQUIRED: IC 7476, IC 7432, IC 7400, IC 7408, Patch Cords & IC Trainer Kit.

THEORY:
A counter in which each flip-flop is triggered by the output goes to previous flip-flop. As all the flip-
flops do not change state simultaneously spike occur at the output. To avoid this, strobe pulse is required.
Because of the propagation delay the operating speed of asynchronous counter is low. Asynchronous counter
are easy and simple to construct.

PROCEDURE :
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

A. ASYNCHRONOUS COUNTER:

1. MOD-8 UP COUNTER
CIRCUIT DIAGRAM: TRUTH TABLE
CLK Qc Qb Qa
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

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2. MOD-8 DOWN COUNTER

CLK Qc Qb Qa
0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1

CLK Qd Qc Qb Qa

1
2
3
4
5
6
7
8
9
10

CLK Qc Qb Qa
0
1
2
3
4
5

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RESULT:

Teachers Signature:____________________

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PART B:
HDL- VERILOG

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Overview of digital design with HDL

Digital circuit design have evolved rapidly over the last 25years. The earliest digital circuits
were designed with vaccum tubes and transistors. Integrated circuits were then invented where
logic gates were placed on a single chip. The first Ic integrated circuit chips – were SSI – Small
Scale Integration in which the gate count was very small. As technologies became sophisticated,
designers were able to place circuits with hundreds of gates on a chip. These chips were called
MSI – Medium Scale Integration. With the advent of LSI (Large Scale Integration) designers can
put thousands of gates on a single chip. At this point design processes started getting very
complicated, and designers felt to automate these processes.

## Computer Aided Design (CAD) technique began evolve.

Chip designers began to use circuit and logic simulation technique to verify the functionality
of building blocks of the order of about 100 transistors.

With advent of VLSI (Very Large Scale Integration) technology, designers could design
single chips with more than 100,000 transistors. Because of the complexity of these circuits, it was
not possible to verify these circuits on a breadboard and systems cannot be realized using
discrete integrated circuits. They are usually realized using high – density, programmable chips,
such as ASICs application –specific integrated circuit and FPGA field –programmable gate arrays.

Emergence of HDL’s

For a long time programming language such as FORTRAN, PASCAL & C were being
used to describe computer programs that were sequential in nature.

Parallely in the digital design field designers felt the need for a standard language to
describe digital circuits. Thus hardware description language (HDLs) came into existence HDL
allowed the designers to model the concurrency of processes found in hardware elements. HDL
such as Verilog HDL and VHDL became popular.

Why HDL:

Hardware description language (HDL) is a CAD tool for the modern design and synthesis of
digital systems. The recent semiconductor technology continues to increases the power and
complexity, such systems cannot be realized using high-density, programmable chips. Such as
application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGAs) and

The designer uses HDL to describe the systems in a computer language that is similar to
several commonly used software language, such as C debugging the design is easy. Since HDL
packages implement simulators and test benches.

## The two widely used HDL

1. Verilog 2.VHDL

STRUCTURE OF VERILOG MODULE:- The verilog module has a declaration and a body. In the
declaration, name, inputs and outputs of the module are listed.

Syntax:

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Module <modulename> (module terminal list);

- ----- -
- ----- -- -
<module internals> The body shows the relationship between the

## - --- --- input and output.

- ------
END MODULE

ARCHITECTURE: The internal details of an entity are specified by an architecture body using any
of following 5 styles
1. DATAFLOW ARCHITECTURE
2. BEHAVIORAL ARCHITECTURE
3. STRUCTURAL ARCHITECTURE
4. SWITCH-LEVE DESCRIPTION
5. MIXED-TYPE DESCRIPTION

DATAFLOW DESCRIPTION approach describes the system by indicating the input and output of
built in primitive components in other words description is through signal flow through the circuit.
The dataflow architecture specifies how data will be transferred from signal to
signal and input to output without the use of sequential statements. Dataflow architecture
used concurrent signal assignment.

## BEHAVIORAL DESCRIPTION is basically a black box approach. It accurately models what

happens on the input and outputs of the black box, but not inside the box. Behavioral description is
sometimes referred to as high level description because of their resemblance with the high level
languages.

VERILOG PORTS:
Input: The port is only an input port. In any assignment statement, the port should appear only on
RHS of the statement (i.e., the port is read).

Output: The port is an output port. In contrast to VHDL, the verilog output port can appear on
either side of the assignment statement.

Inout: The port can be used as both an input and output. The inout port represents a bidirectonal
bus.

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VHDL/VERILOG USER GUIDE
a. Xilinx 9.1i version software is used, for simulation ISE simulator is used.

## b. To Create a new project, go to File menu click New project

c. To open an File which is already existing go to File menu click open project

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d. Now window open like this, type the Project name and location

Click Next
Now window open like this in this select the preferred language whether VHDL/ VERILOG
1.Select Spartan3E family because hardware FPGA is of Spartan3E, then click next
2. select XC3S500E it means Xilinx spartan3E consisting of 500 logic elements.
3. select the package PQ208
4. speed grade is chosen as -4

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Click next

Click Finish

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e. Right click on the New source

f. New window opens, Select VERILOG module and give a new file name for writing the RTL
code.
Enter the input and output ports. This will create file <file.v>.
Click Next and finish the initial Project preparation.
g. Double click on synthesis. If error occurs edit and correct HDL code

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i. Click finish
j. Select Assign package pins in user constraints.
Window opens like this now type the pin numbers in Location(loc). Press enter and save
the file and click ok and close the window

k. Make the connection of hardware components like connect the FRC,bit slave serial
cable between CPU and Kit, turn ON the supply

## l. Now click on to Configure device(Impact) and Configure devices using boundary

Scan(JTAG) is chosen, then click finish

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Then Automatically Bit file will be generated for file an.vhd, open that an.bit

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Execution starts

n. Program is succeeded is displayed ,now change the input and LED’s will glow
output is verified.

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Hardware configuration:

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EXPERIMENT 1
SIMPLIFICATION, REALIZATION OF BOOLEAN EXPRESSIONS USINGLOGIC
GATES/UNIVERSAL GATES.
LOGIC GATES:

## a) Verilog code to simulate AND gate (Data flow style)

Module and1(a,b,c);
input a,b;
output c;
assign c= a & b;
endmodule

## b) Verilog code to simulate AND gate (behavioral style)

module and1(a,b,c);
input a,b;
output c;
reg c;
always@(a,b)
begin
c= a & b;
end
endmodule

c)Verilog code to simulate NOT, OR, NOR, EXOR, EXNOR, NAND (Data flow
style)
Module and1(a,b,c,d,e,f,g,h);
input a,b;
output c,d,e,f,g,h;
assign c= ~a; // NOT GATE
assign d= a|b; // OR GATE
assign e= ~(a|b); // NOR GATE
assign f= a^b; // EXOR GATE
assign g= ~(a^b); // EXNOR GATE
assign h= ~(a&b); // NAND GATE
endmodule

Result:
Teacher’s sign___________________

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EXPERIMENT 2
ADDER/SUBTRACTOR – FULL/HALF USING VERILOG DATA FLOW DESCRIPTION
Block diagram

A
HALF Sum

Cout

INPUTS OUTPUTS
A B S Cout Half adder
module ha (A,B,S,Cout);
0 0 0 0 input a,b;
0 1 1 0 output s,co;
assign s=a^b;
1 0 1 0 assign co= (a &b);
endmodule
1 1 0 1

a
L Sum
b FULL

Block diagram
TRUTH TABLE
INPUTS OUTPUTS
A B Cin S Co
0 0 0 0 0 Full adder
module fa (A,B,C,S,CO);
0 0 1 1 0 input a,b,c;
0 1 0 1 0 output s,co;
0 1 1 0 1 assign s=A^B^C;
assign co= (A&B)|(B&C)|(C&A);
1 0 0 1 0 endmodule
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

## RNSIT DIGITAL DESIGN AND HDL LAB

29
Half subtractor:
Block diagram

a
HALF D
b SUBTRACTOR

Br

TRUTH TABLE
INPUTS OUTPUTS
Half Subtractor
A B D Br
module ha (A,B,D,Br);
0 0 0 0 input A,B;
output D,Br;
0 1 1 1 assign D=A^B;
1 0 1 0 assign Br= ( &B);
1 1 0 0 endmodule

Full Subtractor:-

A
L D
B FULL
SUBTRACTOR
Br

Block diagram

FULL SUBTRACTOR:-
TRUTH TABLE

INPUTS OUTPUTS
A B Cin D Br
0 0 0 0 0
0 0 1 1 1 Full Subtractor
0 1 0 1 1 module ha (A,B,Cin, D,Br);
input A,B,Cin;
0 1 1 0 1 output D,Br;
1 0 0 1 0 assign D=A^B^Cin;
1 0 1 0 0 assign Br= ( &B)|(B&C)|(C& );
endmodule
1 1 0 0 0
1 1 1 1 1

Result:
RNSIT DIGITAL DESIGN AND HDL LAB
29
Teachers sign:_______________________

## RNSIT DIGITAL DESIGN AND HDL LAB

29
EXPERIMENT: 3
CONVERSION OF BCD TO EXCESS 3 AND VICE VERSA

Module bcd_e3(a,b);
input [3:0] a;
output [3:0] b;
reg [3:0] b;
always@(a)
begin
if (a<4’b1010)
{
b=b+1;

## RNSIT DIGITAL DESIGN AND HDL LAB

29
EXPERIMENT: 3
DECODERS AND ENCODERS

a) 3 to 8 decoder
module decodr(en,sel,Y);
input en;
input [2:0] sel;
output [7:0] y;
reg[7:0] y;
always@(en,sel)
begin
if(en)
begin
case(sel)
3'b000:y = 8'b00000001;
3'b001:y = 8'b00000010;
3'b010:y = 8'b00000100;
3'b011:y = 8'b00001000;
3'b100:y = 8'b00010000;
3'b101:y = 8'b00100000;
3'b110:y = 8'b01000000;
3'b111:y = 8'b10000000;
endcase
end
else
y = 8'b00000000;
end
endmodule

## RNSIT DIGITAL DESIGN AND HDL LAB

29
Truth Table of 2 to 4 decoder

1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 X X X

THEORY:
i7
i6 z1
i5 8:3
Parity
i4 z2
Encoder

z3
i0

en

## module encowp1(i,en,z); else if (en==1'b0 && i[4]==1'b0)

input [7:0] i; z=3'b011;
input en; else if (en==1'b0 && i[3]==1'b0)
output [2:0] z; z=3'b100;
reg[2:0] z; else if (en==1'b0 && i[2]==1'b0)
always@(i,en) z=3'b101;
begin else if (en==1'b0 && i[1]==1'b0)
if(en==1'b0 && i[7]==1'b0) z=3'b110;
z=3'b000; else
else if (en==1'b0 && i[6]==1'b0) z=3'b111;
z=3'b001; end
else if (en==1'b0 && i[5]==1'b0) endmodule
z=3'b010;

## RNSIT DIGITAL DESIGN AND HDL LAB

29
RESULT: Truth table

En I7 I6 I5 I4 I3 I2 I1 I0 Z2 Z1 Z0
1 X X X X X X X X
0 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 0 X
0 1 1 1 1 1 0 X X
0 1 1 1 1 0 X X X
0 1 1 1 0 x X X X
0 1 1 0 X X X X X
0 1 0 X X X X X X
0 0 X X X X X X X

i7
i6 z0
i5
8:3
z1
Encoder
i4
Wop
z2

i0

en

## module ewop(i,en,z); z=3'b010;

input [7:0] i; else if (en==1'b1 && i == 8'b00001000)
input en; z=3'b011;
output [2:0] z; else if (en==1'b1 && i == 8'b00010000)
reg[2:0] z; z=3'b100;
always@(i,en) else if (en==1'b1 && i == 8'b00100000)
begin z=3'b101;
if(en==1'b1 && i==8’b00000001) else if (en==1'b1 && i == 8'b01000000)
z=3'b000; z=3'b110;
else if (en==1'b1 && i ==8'b00000010) else z=3'b111;
z=3'b001; end
else if (en==1'b1 && i == 8'b00000100) endmodule

Truth table

## RNSIT DIGITAL DESIGN AND HDL LAB

29
En I7 I6 I5 I4 I3 I2 I1 I0 Z2 Z1 Z0
1 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1 0
1 0 0 0 0 0 1 0 0
1 0 0 0 0 1 0 0 0
1 0 0 0 1 0 0 0 0
1 0 0 1 0 0 0 0 0
1 0 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
0 X X X X X X X X

Result:

Teachers sign:___________________

## RNSIT DIGITAL DESIGN AND HDL LAB

29
EXPERIMENT:3
MULTIPLEXER AND DEMULTIPLEXER

A) 8 to 1 Multiplexer
Block Diagram

a
b
c 8:1Mux
d
e z
f
g

sel (0 1 2)

CODE:
module mux8to1(d,,sel,z);
input [7:0] d;
input [2:0] sel;
output z;
reg z;
always@(sel,d)
begin
case(sel)
3'd0:z=d[0];
3'd1:z=d[1];
3'd2:z=d[2];
3'd3:z=d[3];
3'd4:z=d[4];
3'd5:z=d[5];
3'd6:z=d[6];
3'd7:z=d[7];
endcase
end
endmodule
Truth table
Sel2 Sel1 Sel0 Z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

## RNSIT DIGITAL DESIGN AND HDL LAB

29
b) ii- De-multiplexer ( 1 to 8)
Block diagram:

a 1:8
en Demux
Y(7 downto 0)

sel(0-2)

VERILOG CODE:
module demux8(d,en,sel,y);
input d,en;
input [2:0] sel;
output [7:0] y;
reg[7:0] y;
always@(en or sel or d)
begin
if(en==1'b1)
y=8'b00000000;
else
case(sel)
3'b000:y[0]=d;
3'b001:y[1]=d;
3'b010:y[2]=d;
3'b011:y[3]=d;
3'b100:y[4]=d;
3'b101:y[5]=d;
3'b110:y[6]=d;
3'b111:y[7]=d;
endcase
end
endmodule

Truth table
A En Sel 2 Sel1 Sel0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
0 1 X X X

Result:

Teacher sign:____________

## RNSIT DIGITAL DESIGN AND HDL LAB

29
EXPERIMENT: 4
2-BIT COMPARATOR
Block diagram

a(1 to 0) L
2bit
Comparator E
a(1 to 0)
G

Verilog code:
module comp(a, b, L,E,G);
input [1:0] a, b;
output L,E,G;
reg L, E, G;
always@(a,b)
begin
if (a >b)
G= 1’b1; else G = 1’b0;
if (a <b)
L= 1’b1; else L = 1’b0;
if (a ==b)
E= 1’b1; else E = 1’b0;

endmodule

## RESULT: truth table

Ao A1 B0 B1 L E G

Result:

Teachers sign:___________________
RNSIT DIGITAL DESIGN AND HDL LAB
29
Experiment: 5
FLIP FLOPS

T FLIPFLOP

Black box

t
q
clk
T ff
rst qb

.
Verilog CODE:
module tflipflop(clk,rst,t,q,qb);
input clk,rst,t;
output q;
output qb;
reg q, qb;
always @(posedge clk)
begin
if (rst==1'b0)
begin
q=1'b0;
qb=1'b1;
end
else
case(t)
1'b1: q = ~q;
1'b0 : q = q;
endcase
assign qb = ~q;
end
endmodule

Rst T Clk Q
1 0 1
1 1 1
1 X No +ve edge
0 X X

## RNSIT DIGITAL DESIGN AND HDL LAB

29
D FLIPFLOP
Black box

d
D FF b

clk qb

Verilog CODE:
module dff(d,clk,q,qb);
input d,clk;
output q,qb;
wire qb;
reg q;
always @(posedge clk)
begin
q=d;
end
assign qb=~q;
endmodule

Truth table
Clk D Q Qb
X 1
1 1
1 0

SR FLIPFLOP
Block diagram

clk
S
q
R SR FF
rst qb
pr

module srff(clk,rst,s,r,q,qn);
input clk,rst,s,r;
output q,qn;
reg y;
assign q=y;
assign qn=~y;

begin
if(rst)

29
y=1'b0;
else
case({s,r})
2'b01: y=1'b0;
2'b10: y=1'b1;
2'b11: y=1'bz;
default: y=y;
endcase
end
endmodule

## Result: Truth table

Rst Pr Clk S R Q Qb
1 X X X X
0 1 X X X
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1

JK FLIPFLOP
Block diagram:
j
q
k JK FF
qb
clk

rst

Verilog CODE:
module jkff(clk,rst,j,k,q,qn);
input clk,rst,j,k;
output q,qn;
reg ff;
assign q= ff;
assign qn=~ff;

begin
if (rst)
ff=1'b0;
else
case({j,k})
2'b01:ff=1'b0;
2'b10:ff=1'b1;
2'b11:ff= ~ff;

## RNSIT DIGITAL DESIGN AND HDL LAB

29
default: ff=ff;
endcase
end

endmodule

Truth table
Rst Clk J K Q Qb
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 No+ve - -
egde
0 - - -

Result:

Teachers sign:___________________

## RNSIT DIGITAL DESIGN AND HDL LAB

29
EXPERIMENT: 6

COUNTERS
COUNTER
A sequential circuit that goes through a prescribed sequence of states upon the application of
clock pulses is called a counter . If sequential circuit follows the binary sequence then the circuit is
called binary counter An n bit binary counter consist of n flip-flop and can count in binary from 0 to
2n -1.
A register is used solely for storing and shifting data which is in the form of 1’s and /or 0’s entered
from an external source. It has no specific, sequence of states except in certain very specialized
application.
A counter is a register capable of counting the number of clock pulses arriving at its clock i/p
count represents the number of clock pulses arrived.

SYNCHRONOUS COUNTER
If Common clock i/p is connected to all of the flip-flop and thus they are clocked
simultaneously.

ASYNCHRONOUS COUNTER
If commonly ripple counter the first flip-flop is clocked by external clock pulse and then each
successive flip-flop is clocked by the q or be o/p of the previous flip-flop. Therefore in an
asynchronous counter the flip-flop are not clocked simultaneously.

Bcd Asynchronous
Black box

clk BCD
COUNT q( 3 downto 0)
ER
rst

Verilog CODE:
module bcdsyn(clk,rst,q);
input clk,rst;
output [3:0] q;
reg[3:0] temp;
assign q= temp;

## always@(posedge clk or posedge rst)

begin
if (rst)
temp=4'b0000;
else
begin
temp=temp+1'b1;
if(temp==4'b1001)
temp=4'b0000;
end
end
endmodule

29
Truth table
Rst Clk Q
1 X
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1

## b) 4 bit binary Synchronous

Block diagram:

clk
Binary
counter qout(3 downto 0)
rst

Verilog CODE:
module binarysyn(clk,rst,q);
input clk,rst;
output [3:0] q;
reg[3:0] q;
always @(posedge clk)
begin
if(rst)
q=4'b0000;
else
q=q+1;
end
endmodule

## RNSIT DIGITAL DESIGN AND HDL LAB

29
Result: Truth table
Clk Rst Qout
X 1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0

Result:

Teachers sign:___________________

## RNSIT DIGITAL DESIGN AND HDL LAB

29
EXPERIMENT:7

RELAY
Theory: A relay is an electromagnetic switch operated by a relatively small electric current that can turn
on or off a much larger electric current. switch it on with a tiny current and it switches on ("leverages")
another appliance using a much bigger current.
Relays are used where it is necessary to control a circuit by a low-power signal or where several circuits
must be controlled by one signal.
A simple electromagnetic relay consists of a coil of wire wrapped around a soft iron core, a movable iron
armature, and one or more sets of contacts.
When an electric current is passed through the coil it generates a magnetic field that activates the armature,
and the consequent movement of the movable contact(s) either makes or breaks (depending upon
construction) a connection with a fixed contact
The input circuit (black loop) in the picture is switched off and no current flows through it until something
(either a sensor or a switch closing) turns it on. The output circuit (blue loop) is also switched off.
When a small current flows in the input circuit, it activates the electromagnet (shown here as a red coil),
which produces a magnetic field all around it. The output circuit operates a high-current appliance such as a
lamp or an electric motor.

When power flows through the first circuit, it activates the electromagnet, generating a magnetic field that
attracts a contact and activates the second circuit . When the power is switched off, a spring pulls the contact
back up to its original position, switching

## The switching on and off LED is controlled by the switch button.

CODE:
Module relay1(switch,light);
Input switch;
Output light;
Assign light = switch;
endmodule

## NET "switch" LOC = "p102";

NET "light" LOC = "p4";

## RNSIT DIGITAL DESIGN AND HDL LAB

29
HARDWARE CONNECTION

Procedure:
1) Make the connection FRC9 of the FPGA board to the DC motor connector of GPIO II.
2) Make the connection between FRC1of the FPGA board to the Dip switch connector of the
GPIO II.
3) Also connect +2.5V to the relay and ground.
4) Right click on generate programming file and select properties and configure the “JTAG clock”
in the startup options.
5) Select “automatically configure device using boundary scan (JTAG)”.
6) Select the .bit file.
7) Right click on the Xilinx device icon and select program to download on to the FPGA.
8) When switch1=’0’, the relay cannot be turned ON or OFF. Once the switch1 =’1’, relay performs
its operation the relay closes the switch and circuit complete & LED glows. Thus it acts as a
switch and listen the tick sound.

RESULT: Once the cnt1 or cnt2 is switched on the tick sound is heard at the external light
junction..

Result:

Teachers sign:___________________

## RNSIT DIGITAL DESIGN AND HDL LAB

29
EXPERIMENT:- 8

STEPPER MOTOR

THEORY:

A stepper motor translates electrical pulses into mechanical movement. A conventional motor
(AC/DC motor) shaft runs freely, whereas the stepper motor shaft moves in a fixed increment & hence
the shaft position can be controlled precisely, say move by 4 ◦ & stop. Stepper motors are used for
position control applications such as dot matrix printers, disk drives, robotics, etc. There are two types
of stepper motors (SM)—permanent magnet SM & variable reluctance SM, depending on the rotor
type (whether permanent magnet is used or not).
The permanent magnet SM consists of a permanent magnet rotor (also called the shaft)
surrounded by a stator as shown in Fig. 10.13(a). Generally the stator has 4 windings that are paired
with a center-tapped common as shown in Fig. 10.14. The center tap allows a change of current
direction in each of the two coils, hence changing the direction of polarity in the stator poles which
return leads to a change in the direction of rotor rotation. The rotation of the rotor in a SM along with
the winding energization sequence is shown in Table 10.5. Depending on the number of teeth on the
stator & rotor, the stepper motor rotates a fixed number of steps per revolution. The commonly
available number of steps for one revolution are 500, 200, 180, 144, 72, 48, 24. The step angle, i.e.,
the movement of a single step of a stepper motor is calculated as
360◦

no. of steps per revolution . Say for 200 steps per revolution. The step angle is

360◦

## 200 =1.8◦ per step.

Similarly step angle for 72 steps per revolution is
360

72 = 5.

For the 4-step switching sequence shown above, after four steps the same two windings will be ‘ON’,
i.e., the sequence repeats after every 4 steps. After completing 4 steps, the rotor moves only one tooth
pitch. Hence if the rotor has 50 teeth (each teeth is one pole), the number of steps for one complete
revolution is 4 steps×50 rotor teeth = 200 steps/revolution. Hence for smaller step angles (i.e., more
steps/revolution), the rotor must have more teeth.

## Speed is generally measured by rpm—(revolutions per minute).

The relation ship is shown below

## (rpm/60 = rps = revolutions per second).

As rpm is increased, the steps per second also increases.

Procedure:
1) Make connection between FRC 9 and FPGA board to the stepper motor connector GPIO II.
2) Right click on generate programming file and select properties and configure the “JTAG clock”
in the startup options.
3) Select “automatically configure device using boundary scan (JTAG)”.
4) Select the .bit file.
5) Right click on the Xilinx device icon and select program to download on to the FPGA.

## RNSIT DIGITAL DESIGN AND HDL LAB

29
6) When reset (p102) is high the motor rotates either in clockwise or anticlockwise direction
depending on the dir pin (p102)
Verilog CODE:
module stepper(clk,dir,rst,dout);
input clk,dir,rst;
output[3:0] dout;
reg [15:0] clk_div;
reg[3:0] shift_reg;
assign dout = shift_reg;

initial
begin
clk_div = 16'b0000000000000000;
end

## always @ (posedge clk)

begin
clk_div = clk_div+1;
end

## always @(negedge rst or posedge clk_div[15])

begin
if (!rst)
shift_reg = 4'b1001;
else
begin
if(dir)
shift_reg = {shift_reg[0],shift_reg[3:1]};
else
shift_reg ={shift_reg[2:0],shift_reg[3]};

end
end
endmodule
HARDWARE CONNECTION

## #PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = "p74" ;
NET "dir" LOC = "p106" ;
NET "dout<0>" LOC = "p205" ;
NET "dout<1>" LOC = "p3" ;
NET "dout<2>" LOC = "p5" ;

## RNSIT DIGITAL DESIGN AND HDL LAB

29
NET "dout<3>" LOC = "p4" ;
NET "rst" LOC = "p102" ;

## #PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

RESULT: By varying the direction and speed the interfacing of the stepper motor is verified
INFERENCE: The speed of the Stepper motor can be controlled by varying the counter value, and
further it can be stopped for some period of nano seconds by inserting the delay. The direction can
also be changed.

Teachers sign_______________________

## RNSIT DIGITAL DESIGN AND HDL LAB

29
EXPERIMENT:-9
WAVEFORM GENERATION USING DAC

The DAC (digital to analog converter) is an interface unit that can translate digital information into
corresponding analog signal. It accepts a digital or binary word at its input and outputs an analog
voltage or current. The two commonly used DAC types are (1) Weighted Resistor DAC—where in a
binary-weighted resistor network with a set of switches and an opamp, converts the input digital word
into an equivalent current at the output of an opamp. (2) A R-2R ladder DAC which uses a precision
current-splitting R-2R resistor network. Apart from a higher degree of precision, this type of DAC has
smaller settling time. Hence IC versions of DAC use this circuit.
An important parameter used in the selection of the DAC is its resolution. Resolution is defined
as the smallest step size of the output analog voltage generated by the DAC and depends on the
number of bits ‘n’ used at the input of the DAC. The commonly used DACs have 8, 10 and 12 data bit
inputs. (now 16-bit DACs are also available). DAC is commonly used in wave form generation

Procedure:
1) Make the connections between FRC5 of the FPGA board to the DAC connector of the GPIO II.
2) Make the connection between FRC1 of the FPGA board to the Dip switch of the GPIO II.
3) Right click on generate programming file and select properties and configure the “JTAG clock”
in the startup options.
4) Select “automatically configure device using boundary scan (JTAG)”.
5) Select the .bit file.
6) Right click on the Xilinx device icon and select program to download on to the FPGA.
7) Make the reset switch on.

HARDWARE CONNECTION

SQUARE WAVE:
A square wave is obtained by generating a high voltage (say 5V) for certain time and then a low
voltage (say 0V). This 5V and 0V are obtained by sending 00 & FFH to the input of the DAC. The on-
times and off-times are generated using delay loop. For 50% duty cycle: on.time = off time. For other
values of duty cycles, the on-time & off-time are varied

## RNSIT DIGITAL DESIGN AND HDL LAB

29
Verilog Code:
module square(clk,rst,dac);
input clk,rst;
output [7:0] dac;
reg [7:0] dac;
reg [6:0] temp;
reg [7:0] cnt;

initial
begin
temp = 7'b0000000;
end

begin
temp = temp+1;
end

## always @(negedge rst or posedge temp[6])

begin
if(!rst)
cnt= 8'b00000000;
else
begin
cnt= cnt+1;
if(cnt[7] ==1)
dac = 8'b11111111;
else
dac = 8'b00000000;
end
end
endmodule

TRIANGLE WAVE:
It is same as that of the ramp wave generation except that the output , at the input of the DAC
after being increased from 00 to FFH (in steps of 1) is brought down to 00, again in steps of 1

module triangle(clk,rst,dac);
input clk,rst;
output [0:7] dac;
reg [0:7] dac;
reg [3:0] temp;
reg [7:0] cnt;

## RNSIT DIGITAL DESIGN AND HDL LAB

29
initial
begin
temp = 4'b0000;
end
always @ (posedge clk)
begin
temp = temp+1;
end

## always @(negedge rst or posedge temp[3])

begin
if(!rst)
cnt= 8'b00000000;
else
begin
cnt= cnt+1;
if(cnt[7] ==1)
dac = cnt;
else
dac = ~cnt;
end
end
endmodule

RAMP WAVE:
A ramp waveform is shown in below figure. The voltage of the ramp increases from an initial
value (say 00V) to a final value (say 5V) smoothly. This increase in voltage can be obtained from the
output of the DAC by changing the values sent at the port from 00 to FFH continuously in steps of ‘1’.

module ramp(clk,rst,dac);
input clk,rst;
output [0:7] dac;
reg [0:7] dac;
reg [3:0] temp;
reg [7:0] cnt;

initial
begin
temp = 4'b0000;
end

begin
temp = temp+1;
end

## RNSIT DIGITAL DESIGN AND HDL LAB

29
begin
if(!rst)
cnt= 8'b00000000;
else
begin
cnt= cnt+1;
dac = cnt;
end
end
endmodule

STAIR CASE:

module stair(clk,rst,dac);
input clk,rst;
output [0:7] dac;
reg [0:7] dac;
reg [13:0] temp;
reg [7:0] cnt;

initial
begin
temp = 14'b00000000000000;
end
always @ (posedge clk)
begin
temp = temp+1;
end

## always @(negedge rst or posedge temp[13])

begin
if(!rst)
cnt= 8'b00000000;
else
begin
cnt= cnt+33;
dac = cnt;
end
end
endmodule
NET "clk" LOC = "p74" ;
NET "dac<0>" LOC = "p40" ;
NET "dac<1>" LOC = "p36" ;
NET "dac<2>" LOC = "p33" ;
NET "dac<3>" LOC = "p34" ;
NET "dac<4>" LOC = "p18" ;
NET "dac<5>" LOC = "p19" ;
NET "dac<6>" LOC = "p15" ;
NET "dac<7>" LOC = "p2" ;
NET "rst" LOC = "p102"

## RNSIT DIGITAL DESIGN AND HDL LAB

29
RESULT: The waveform obtained Ramp, Staircase, Triangular and Square waves are as per the
graph.

INFERENCE: The output waveform is observed on CRO, by changing the values of the count ,
amplitude and frequency will change and it can be measured on CRO.

## RNSIT DIGITAL DESIGN AND HDL LAB

29
Teacher’s sign___________________________

29