No.

Designing a Class A Power Amplifier Using the Load-Pull Method

DC HARMONIC BALANCE PARAMETER SWEEP

DC HarmonicBalance ParamSweep
DC1 HB1 Sweep1
Freq[1]=RF_freq SweepVar="Theta"
Order[1]=Max_Harmonic SimInstanceName[1]="HB1"
SweepVar="R" SimInstanceName[2]= User variables declaration
Setting of source and load impedance at
Start=0 SimInstanceName[3]= various harmonics.
Stop=Max_R SimInstanceName[4]=
Lin=12 SimInstanceName[5]= Var
Eqn
VAR
SimInstanceName[6]= VAR5
V_DC Start=0 ZL_DC=100000
Stop=360 ZL_2=2 + j*0
SRC1
Vdc=3.0 V R Step=10 ZL_3=0 + j*0
Rb1 L ZL_4=0 + j*0
R=6.8 kOhm L1 ZL_5=0 + j*0
L=330.0 nH ZS_DC=Z0
R= ZS_1=Z0 + j*0
ZS_2=Z0 + j*0
ZS_3=Z0 + j*0
I_Probe ZS_4=Z0 + j*0
C ZS_5=Z0 + j*0
ILoad
Cc2
I_Probe C=1000 pF
pb_phl_BFR92A_19921214
Var
Eqn
VAR
ISource Q1 S1P_Eqn VAR3
C
R S1P1 RF_freq=410 MHz
Cc1
Rb2 S[1,1]=RhoL Rhoc=0
C=1000 pF
R=4.7 kOhm R C Z[1]=Z0 Max_R=0.98
P_1Tone Re Ce Max_Harmonic=5
PORT1 R=100 Ohm C=330 pF Z0=50
Num=1
Z=Zs
P=polar(dbmtow(-20),0)
Freq=RF_freq
P_1Tone source
will deliver the The function iload returns an integer depending on the valud of global
specified amount variable 'freq'. IIf freq=0 (dc) iload=0, if freq=RF_freq, iload=1, if freq=2xRF_freq,
of power into a iload=2 etc. A maximum of 5 is imposed, for a harmonic of 5.
load when it is
terminated with
the conjugate of
Var
Eqn
VAR
the source impedance VAR2
Z. Rho=Rhoc+R*exp(j*(Theta/180)*pi)
Theta=0
R=0.5
r(x)=(x - Z0)/(x + Z0)
Var
Eqn
VAR
VAR6
iload=int(min(abs(freq)/RF_freq+1.5,5))
RhoLArray=list(r(ZL_DC),Rho,r(ZL_2),r(ZL_3),r(ZL_4),r(ZL_5))
RhoL=RhoLArray[iload]
SrcArray=list(ZS_DC,ZS_1,ZS_2,ZS_3,ZS_4,ZS_5)
isrc=min(iload,length(SrcArray))
Zs=SrcArray[isrc]

 The transistor chosen for the job is BFR92A which comes in SOT-23 package. The maximum I C sustainable by
the transistor is 30.0mA, with transistion frequency fT = 5GHz, which is more than sufficient for the job.
 Since this is a large signal nonlinear circuit, substantial harmonics will be generated, therefore the chosen
simulation method is the Harmonic Balance Method.
 Common emitter configuration is used and the schematic for performing DC simulation and large signal load-
pull test is shown in Figure 1.
 The amplifier is driven by a source with impedance of 50Ohms at the fundamental frequency. We assume the
source impedance also maintains at 50Ohms at the other higher harmonics. If this assumption is not true,
then we just assign new values to the impedance at higher harmonics.
In performing this simulation we merely deactivate the Harmonic Balance and Parameter Sweep control. The DC
simulation results are:

VC VE VB IC

3.0V 0.338V 1.12V 3.34mA

The result is reasonable, as VCC = 3.0V, VE of 0.1VCC or higher will ensure adequate bias stability and prevent thermal
runnaway. The dissipated DC power is:

PDC = (23.0)0.00334 = 20.04mW

The RF output power will not be higher than this level. The ideal efficiency of this Class-A circuit is 50%, assuming a
realistic value of 33%, the RF output power will be no more than 6.61mW for linear operation.

Load-pull test result:

Source power = -5dbm

Maximum output power = +8.304dbm

Contour step = 0.5dbm.

Optimum Load impedance at

fundamental frequency (410MHz)

ZL(opt) = 438.05 + j0