2017 29th International Conference on Microelectronics (ICM)

A 28 GHz Four-Channel Phased-Array Transceiver in 65-nm

CMOS Technology For 5G Applications
Hesham A. Ameen1 , Kareem Abdelmonem2 , Mohamed A. Elgamal3 , Mohamed A. Mousa4 ,
Omaira Hamada5 , Yahia Zakaria6 and Mohamed A. Y. Abdalla7
Electronics and Communications Engineering Department, Cairo University, Giza, Egypt
Email: 1 Hesham.beshary@gmail.com, 2 Kareem.men3em@gmail.com,
3
Mohamed.alaa.elgamal@gmail.com, 4 Mohammedmousa3620@gmail.com,
5
Omaira.hamada@gmail.com, 6 Yahiazaakaria@gmail.com, 7 Youssef@ieee.org

Abstract— A Fully integrated 4-element symmetrical

TX/RX RF integrated circuit for 26-30 GHz 5G beam-
forming system is implemented in 65-nm CMOS technology.
Each array element is digitally controlled with 5.625◦ step
and 2 dB gain step. The system employs a heterodyne
architecture with 6 GHz intermediate frequency (IF). The
up-conversion and down-conversion mixers are integrated on
the same chip with a shared LO driver chain. The phased-
array power combining/splitting is done using Wilkinson
combiner/divider. The RFIC features 3.4 to 3.9 dB noise
figure and -5 to -3.5 dBm IIP3 in RX mode, 18 dB maximum Fig. 1. 4-element phased-array receiver architecture.
power gain and OP1dB of 14.7 dBm per chain in TX mode.
The maximum root mean square amplitude and phase error
of each array element is 0.25 dB and 1.5◦ , respectively. The
RFIC area is 18 mm2 including pads and it consumes 240
mW per TX chain, 120 mW per RX chain and 174 mW for
the LO amplifier with total power of 1.58 W from a 1.2 V
supply.
Index Terms— 5G, 28GHz, phased-array, beamforming,
wireless-communications, transceiver, phase-shifter, CMOS.

Fig. 2. 4-element phased-array transmitter architecture.

I. I NTRODUCTION
Next-generation mobile technology (5G) targets to sus-
tain the evolution of mobile communications in terms
of connectivity, throughput and spectral efficiency while
enhancing the user experience by 2020 [1]. While the
spectral band to be adopted is not yet determined, recent
advances make the 28 GHz band particularly interesting for
5G mobile standardization. The 28 GHz bands is currently
available with spectrum allocations of over 1 GHz of
bandwidth [2]. Also, to counter heavy propagation losses,
directive antenna arrays were integrated into base station
and user equipment (UE) form factors in commercial grade
technologies [3]. A common myth in the wireless engineer-
ing community is that rain and atmosphere make mm-wave
spectrum useless for mobile communications. However,
when one considers the fact that today’s cell sizes in urban
environments are on the order of 200 m, it becomes clear
that mm-wave cellular systems can overcome these issues.
Work by many researchers has confirmed that for small
distances (less than 1 km), rain attenuation will present
a minimal effect on the propagation of mm-waves at 28
GHz to 38 GHz for small cells [4].
Besides wave propagation, cost reduction of UE de-
vices is another critical 5G challenge. Low cost, higher
yields and a high level of integration for UE phased
arrays make CMOS the technology of choice. Moreover,
the performance of CMOS technologies is continuously
improving. Decreasing minimum feature size with every
new generation leads to higher speed devices making it
suitable for mm-wave design.
This paper is organized as follows. Section II describes
the transceiver architecture. A circuit realization that im-
plements the chosen architecture is expanded upon Section
III. Simulation results are reported and compared with the
current 5G state-of-the-art in Section IV.
II. T HE TRANSCEIVER SYSTEM ARCHITECTURE
A. Receiver architecture
In this work, a heterodyne receiver is considered with
lower side injection. The receiver is based on Hartley ar-
chitecture for image rejection. The intermediate frequency
(IF) is chosen to be 6 GHz, and can operate up to 10 GHz.

978-1-5386-4049-4/17/$31.00 ©2017 IEEE

 2017 29th International Conference on Microelectronics (ICM)
Fig. 1 briefly describes the phased array receiver system
proposed for this work. The LNA is directly followed by
the VGA of the vector modulator, as the best compro-
mise for the system linearity and noise performance, then
followed by the phase shifter, power combiner and the
mixer. In this work, the receiver has a simulated optimum
operation for the input power range from -45 dBm to -25
dBm and constant output power of -19 dBm.
B. Transmitter architecture
A heterodyne transmitter with lower side rejection is
considered for this work. The performance of the trans-
mitter is limited by the linearity of the PA, which is
mainly determined by the technology and the used supply.
The OP1dB of the PA is approximately 15 dBm, so the
maximum rated average output power of the transmitter
is 5 dBm (10 dB backed-off), while the input IF power
is around -13 dBm. The lineup starts with the mixer then
followed by a highly linear gain stage to compensate the
power divider loss and limit the system noise, while each
channel consists of a phase shifter, VGA and PA. The
transmitter lineup is described briefly in Fig. 2.
III. C IRCUIT DESIGN
A. LNA
The two-stage cascode LNA with active balun topology
proposed in [5] is used. It is based on an inductive
degenerated common-source amplifier in combination with
a gate inductor. The first stage is biased at the optimum
current density to get the minimum noise figure, while
the second stage is implemented as a common-gate -
common-source topology to realize the balun functionality.
This topology provides noise figure < 2.1 dB, good input
matching, high reverse isolation and high OIP3 of 15 dBm.
B. 4-way combiner/splitter
Due to array architecture and low power consumption
requirement, a passive power combiner was implemented.
To improve isolation between chains to be above 15
dB, a Wilkinson type combiner/splitter was selected. The
traditional transmission line design was converted to an LC
topology to minimize the area [6]. Wilkinson simulations
show 0.8-1.8 dB insertion loss, good matching for all ports
and 16-19 dB isolation.
C. Mixer
Double balanced complementary passive ring mixer is
used, the complementary topology is used to improve
switching at low Vthreshold , while the differential design
reduces the leakage between the LO and the RF ports. The
mixer is driven by a poly-phase filter followed by an LO
driver amplifier that delivers a high voltage swing to drive
the mixer and achieve proper switching. Mixer conversion
loss is around 8 dB and its IIP3 is +19 dBm. The simulated
LO to RF leakage is -35 dB and side-band rejection (SBR)
/ image rejection ratio (IRR) > 36 dB.
Fig. 3. The chip layout including the four-element TX/RX array,
the up-conversion mixer, the down-conversion mixer and the LO
driver chain.
D. Phase shifter
Active phase shifter topology is picked up for this
work. A typical active phase shifter starts with an I/Q
generation network, an analog adder, and control circuits
which set the different amplitude weightings of I- and Q-
inputs in the analog adder to achieve the required phase
steps [7]. A 2-stage poly-phase filter is chosen for the
I/Q generation as it achieves the best compromise between
loss, layout complexity and wide-band response. A folded
Gilbert-cell topology is used as a differential current adder
with variable gain instead of the traditional one to reduce
number of transistors in the stack. At 28 GHz, the phase
shifter rms phase error is < 0.5◦ , rms gain error < 0.13
dB, while the OIP3 equals to 17±1 dBm.
E. VGA
A two stage phase invariant variable gain amplifier is
used, the first stage is a digital step attenuator (DSA)
[8] with 2 dB step and 20 dB attenuation range. Each
attenuator cell consists of two stages, the first stage is
a π-model and the second one is a phase compensation
varactor. The second VGA stage is a high gain amplifier to
achieve the required output power. This topology achieves
a highly linear response with very low gain error and very
low phase error < 2.5◦ .
F. Power Amplifier
A three transformer-coupled pseudo-differential stage
PA design is used. Each stage is a common source neu-
tralized amplifier to insure stability and increase reverse
isolation and gain. Inductive degeneration is used in the
output stage to increase the linear output power. The
integrated output balun has an insertion loss of < 0.7 dB in
the frequency range of interest. The PA achieves 14.8 dBm
P1dB, 17.7 dBm Psat, 26.2 dBm OIP3, 21% PAEM AX and
25.3 dB small signal gain. The PA consumes 160 mA from
the 1.2 V supply.
 2017 29th International Conference on Microelectronics (ICM)
(a)
(b)
Fig. 4. (a) Receiver SNDR vs input power, (b) Receiver NF for
minimum input power vs frequency.
(a) (b)
(c) (d)
Fig. 5. Receiver (a) gain response and gain error across gain
steps, (b) gain response and gain error across phase steps, (c)
phase response and phase error across phase steps, (d) phase
response and phase error across gain steps.
IV. R ESULTS
All transmission lines, inductors, baluns, pads have
been modeled using a 2.5-D electromagnetic solver (Son-
net). The chip layout of the four-element array, the up-
conversion mixer, the down-conversion mixer and the LO
amplifier is shown in Fig. 3. The channel bandwidth used
for the SNDR calculations is 1 GHz. The chip size is 18
(a)
(b)
Fig. 6. (a) Transmitter SNDR vs single element output power,
(b) The transmitter output 1dB compression point vs frequency.
(a) (b)
(c) (d)
Fig. 7. Transmitter (a) gain response and gain error across
gain steps, (b) gain response and gain error across phase steps,
(c) phase response and phase error across phase steps, (d) phase
response and phase error across gain steps.
mm2 including pads. The chip consumes 1.58 W (240 mW
per chain in TX mode, 120 mW per chain in RX mode
and 174 mW for the LO amplifier) from a 1.2 V supply.
A. Four-Channel Receiver Array Characterization
Increasing modulation scheme requires higher SNDR
levels to achieve a certain bit error rate. Fig.4(a) shows
an SNDR level greater than 40 dB for the receiver input
 2017 29th International Conference on Microelectronics (ICM)

TABLE I
power range from -45 dB to -25 dB. Fig.4(b) shows that the
C OMPARISON O F RF P HASED -A RRAY TRX F RONT-E NDS .
receiver NF ranges from 3.4 to 3.9 dB for the minimum
input power. The gain response with different gain and Reference This [9] [10] [11]
phase steps is shown in Fig.5(a) and (b) respectively with Work
RMS gain error < 0.26 dB across all gain steps and
Technology 65-nm — 130-nm 130-nm
< 0.3 dB across all phase steps. The phase response with
CMOS SiGe SiGe
different phase and gain steps is shown in Fig.5(c) and (d)
respectively with RMS phase error < 1.4◦ across all phase Frequency (GHz) 26-30 26.5-29.5 28-32 24-28
steps and < 3.7◦ across all gain steps. The receiver has a No. of TX/RX 4/4 4/4 32/32 4/4
maximum gain of 27 dB and IIP3 range from -5 to -3.5 Elements
dBm. Phase Resolution 5.625 11.25 4.9 5.625
(deg)
B. Four-Channel Transmitter Array Characterization
TRX Phase Error <1.4 5 <1 < 4.2
Fig.6(a) shows an SNDR level greater than 40 dB in the RMS (deg)
transmit mode for the output channel power range from - TRX Gain Error ±0.6 0.5 ±0.7 < 0.5
15 to 5 dB. Fig.6(b) shows that the transmitter OP1dB per
(dB) (RMS)
channel ranges from 14 to 14.7 dBm. The gain response
RX Gain 26 + 28 35 8.7 to
with different gain and phase steps is shown in Fig.7(a)
(dB) 11.5
and (b) respectively, with the RMS gain error < 0.2 dB
across all gain steps and < 0.28 dB across all phase steps. RX NF <3.9 5 6 4.5 to
The phase response with different phase and gain steps is (dB) 6.9
shown in Fig.7(c) and (d) respectively, with RMS phase RX iP1dB -5 to — -22 -25.4 to
error < 1.4◦ for all phase steps, and < 2.4◦ for all gain (dBm) -3.5 -18.4
steps. TX Gain 18 + 26 34 9.4 to
(dB) 14.3
V. C ONCLUSION
TX OP1dB 14 to +9 13.5 5.5 to
This paper has demonstrated a 28 GHz TX/RX fully (dBm) 14.7 10.6
integrated 4-element phased-array for 5G application in
TX DC Power 0.96 0.8 5.1 0.1215
65-nm CMOS technology. Integrated up-conversion and
(W)
down-conversion mixers with a shared LO driver chain
RX DC Power 0.48 0.5 3.3 0.218
are also included. A digital control with 5.6 degrees step
(W)
and 2 dB gain step is used for each array element. The
post-layout simulated results are summarized and com- Area (mm2 ) 16.62 — 165.4 0.2 (Rx)
pared with other work in Table.I. Compared to the other Exluding pads (TRX) (TRX) 0.15 (Tx)
references, this work achieves both high linearity and low
noise figure with low power consumption and area.
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