ICSP2008 Proceedings
The Hardware Platform Design for DRFM System
Zongbo Wang Meiguo Gao Yunjie Li Haiqing Jiang Sunguo Ying
Department of Electronic Engineering, Beijing Institute of Technology
Beijing 10081 P. R. China
E-mail: borry@bit.edu.cn
Abstract
The hardware platform design for Digital Radio
Frequency Memory (DRFM) is the analogue-digital
combined circuit with high speed data transfer speed,
and the design quantities of the hardware platform
significantly affect the overall performance of the
whole system. The hardware requirement for general
purpose DRFM system is analyzed and the hardware
architecture based on FPGA and DSP techniques is
proposed. The general principle for high-performance
hardware design is withdrawn based on the
engineering implementation experience. The entire
design example with high speed data sample rate and
real-time modulation ability is illustrated, and several
important circuits example is given. The ideal
performance of the example board guarantee the
correctness of the design idea, and the concept stated
in the article is valuable for implementation reference.
1. Introduction
Digital Radio Frequency Memories (DRFMs)
form the significant building block in radar
countermeasure systems, the basic idea of the DRFM
can be found in reference[1],and the modern
application example in radar countermeasure systems
and radar signal simulator is widely stated as in [2-
4],with the development of the integrated circuits(IC)
technique, especially the participating of the field
programmable gate array(FPGA), the hardware
platform architecture has been greatly changed
compared with the former states in [5, 6]. Besides the
development of the capacity of the hardware platform,
the new design idea motivated by the concept of
Software Radio (SOW) are stated as in [7].
The general idea of the DRFM system is
introduced and the basic hardware requirement is
stated in section 2, the detailed design issues of the
hardware platform and the effect of the overall system
performance is stated in section 3, section 4 illustrate
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the implementation example with broadband coverage
ability and conclusion is drawn in section 5.
2. The concept of DRFM system and the
basic hardware platform requirement
A basic block diagram of DRFM system is shown
in Fig.1[1]. The baseband process model (in the
dotted line) is consists of a high-speed analogue-to-
digital (A/D) converter, high-speed random access
memory (RAM), a programmable microcontroller,
and a digital-to-analogue (D/A) converter.
Reproducted Signal Output
Original Signal Input
LPF A/D Memory D/A LPF
Controller
Local Oscillator
Fig 1 The basic block diagram of DRFM system

There are also several alternative DRFM models,
i.e. double sideband model, and phase sampling
model, all these architectures are designed to carry out
the same basic task: to convert the input RF signal to
a frequency low enough to be sampled by a A/D
converter and to convert the output of the D/A
converter back to the original RF frequency.
The novel DRFM integrated in radar
countermeasure system, different from the original
simple re-transmit architecture shown in Fig.1, the
modulate process should be taken for false-target
jamming purpose, besides the transmitted delay, the
modulation should be also done in amplitude, phase,
and frequency dimension according to the real-
target’s RCS ,phase shift and Doppler frequency shift
respectively.
The human communication interface should also
be add for the radar countermeasure system to control
the delay time, modulate parameter, jamming style
and display the feedback information from the
hardware through desktop application software. To
meet requirement stated above, the extended diagram
for DRFM system is drawn in Fig.2. 3.1.2. Special circuit design for the sampling
Local Oscillator clock. The quality of the sampling clock will affect
directly on performances and stability of A/D
LPF A/D Memory Modulator D/A LPF
converters. The sampling clock is as vulnerable to
Reproducted Signal Output
noise as any analog signal, but is as liable to cause
Original Signal Input

Controller
noise as any digital signal, so it must be kept isolated
from both analog and digital systems.
There are several ways to create high quality
Desktop Software
sampling clock, in reference [8], a method of sending
Fig 2 The extend block diagram of DRFM system pure sinusoidal wave to high speed comparator is
introduced, another example of transfer the single-end
As shown in Fig.2, the hardware design discussed sinusoidal single into PECL signal will be introduced
in this paper is placed in the dotted block. The circuit in section 4.
with real-time digital signal process ability should be
add to perform the modulate process and the 3.1.3 Adjustment for the analogue input
communication protocol between hardware and signals. The pre-shape of the analogue signal should
human should be take into account. Besides, the be designed to meet the requirement of the A/D
hardware platform should be build to offer cost and converter in amplitude and frequency range. When
performance advantages, and with the ability to using amplifier to act as the driver, AC performances
absorb design changes, ease of feature insertion for include bandwidth, construction time, harmonic
product evolution and differentiability. distortion, total harmonic distortion should be taken
into account first, and the DC performances include
3. Design issues in hardware platform gain, detuning, temperature drift and liner error of the
gain, should also be considered. When using the RF
3.1 The ADC design issues transformers, the transfer radio, the frequency range
The A/D converter play an important role in the and the insertion loss should be properly selected.
DRFM system, the circuit of A/D and its periphery
are analogue-digital combined, and with high transfer 3.2 Using FPGA to undertake signal processing
speed, so special consideration should be taken in the The FPGA consists of a vast array of configurable
aspect of quality of sampling clock, quality of the logic tiles, multipliers, and memory resources. This
input signal, driver amplifier, power supply, technology provides the signal-processing engineer
grounding, thermal management, etc.[8] The with the ability to construct a custom data path that is
following steps can lead to finish the A/D converter tailored to the application at hand. The integration of
circuit design to achieve ideal performance. FPGA into DRFM system greatly changes the design
of the hardware platform. Take the new generation of
3.1.1 Selecting suitable A/D converter. The A/D FPGA chips from Xilinx as the example,
converter in DRFM system determines the bandwidth Firstly, the new generation of FPGA has
coverage of the system, so in order to achieve configurable high-performance IO resources,
broadband coverage, the A/D converter should have a supporting a wide variety of standard interfaces, and
sufficiently sample rate to capture both the full on-chip termination can be used to maintain signal
instantaneous bandwidth of the radar pulse and the integrity with fast transfer speed. This make it easy to
bandwidth over which frequency hopping may occur. transfer the A/D sampled data direct into chip for next
Typically, sampling rates in the order of 1 GHz or step’s process. It also makes the FPGA easy to
higher are used for this purpose, and even fanning the exchange data with other processor, like DSPs.
data out in parallel ways, that also put a heavy burden Secondly, there are abundant of Block RAM
on the circuit to keep up.The quantization of the resources inside of the FPGA chip, the two ports of
sampled values can cause harmonics in the DRFM the Block RAMs are symmetrical and totally
system, the harmonics could be used by victim Radar independent, sharing only the stored data. That Block
to detect the jamming signal, and the magnitude of the RAM can be configured as the Memory in Fig.2
harmonics is mainly determined by the numbers of according to the pulse width of Radar signal and the
quantization levels (bits) in the ADC.[9]So the sample sample rate.
rates and the resolution level are two main aspects to Thirdly, the hardware multipliers are integrated
choose the suitable A/D converter. inside of the chip, that makes it possible to program

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the FPGA to performance the modulate process
(shown in Fig.2) in real-time.
3.3 Using DSP to performance as the controller
and communicate with desktop
In the previous generation of DRFM hardware
platform, DSP chips play the most important role in
the modulation process and Memory chips for the
storage of sampled radar signal are configured as the
periphery around DSP. Even the main process tasks
are distributed in FPGA, the DSP still take the
advantage of easy program and debug, and can be
used to undertake certain parameter calculation task,
to act as the co-processor around FPGA.
In certain series of DSP, like TMS320C6416 from
Texas Instrument, there are integrated PCI protocol,
that is perfect to use as the interface to communicate
with desktop application software to achieve flexible
system.
3.4 The DAC design issues
In traditional DRFM module, the D/A converter
share the same clock with the A/D converter to keep
the coherence of the reproduced signal with the
original one, the DRFM model also has alterative
architecture with unbalanced A/D converter rate and
the D/A converter rate, as in reference[7].
The circuit design around D/A converter also
should follow the rules stated in A/D converter,
because both circuits are analogue-digital mixed, and
the additional circuit after the chip of D/A converter
should be designed to meet the requirement for the
model of up-converter in driving ability and signal
standard.
3.5 The printed circuit board design issues
From the above statement, the hardware platform
for DRFM system is analogue-digital combined and
with high speed data transfer rate, so special rules
should be followed in the consideration of signal
integrity. That is the topic so called “black magic”,
the detailed background knowledge can be found
from reference [10, 11], the following simplified
golden lines are given according our engineering
experience.
3.5.1 System level layout It is evident that noise
can be minimized by paying attention to the system
layout and preventing different signals from
interfering with each other[8]. The principle is:
separating low frequency circuit from high frequency
circuit, separating low speed circuit from digital
circuit, separating more calorific component from less
calorific component.
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For DRFM hardware platform, the A/D converter
and D/A converter are cross-domain components;
they have to be isolated from the pure digital circuit.
The data transfer bus between A/D converter and
FPGA chips is high clock rate, and the command
information and parameter transfer between FPGA
and DSP are low clock rate, so these two part circuit
should be separated.
3.5.2 Data reflection The interfaces between
output data of A/D converter and FPGA, the input
data of D/A converter and FPGA, data reflection
exists and affects the quality of other signals.
Especially for the signal wires longer than 8cm,
terminal matching resistance must be applied to
eliminate data reflection. Value of matching
resistance is decided by output driver current and
dead resistance.
3.5.3 Grounding Multi-layer circuit should be
adopted and the PCB should have at least one
complete layer dedicated to the ground plane. In high
speed A/D converter and D/A converter with large
amounts of digital circuit, it is highly desirable to
physically separate sensitive analog signals from
noisy digital signals. It is usually desirable to use
separate ground plane for the analog and the digital
circuit.
4. The design example of the broadband
DRFM system
From the analyses in section III, the ideal chip-
level components of the ideal DRFM system is: A/D
converter, FPGA, DSP, D/A converter. Based the idea
and the design principles above, a general purpose
hardware platform with broadband coverage is
designed to undertake the jamming function in certain
radar countermeasure system, the platform is a single
6U board compatible with standard Compact PCI
(CPCI) standard. The diagram of the board is shown
in Fig.3
OUT_Q OUT_I BIN AIN TRIG CLK
system level interface
clk
D/A A/D
circuit
FPGA
Virtex 4 SX35
TI
DSP
TM S320C6416
[J1£¬ J2] cPCI [J4£¬J5] Self-defined IO
Fig 3 The diagram of the hardware platform for
DRFM system
 The board is mainly composed by one chip of A/D
converter, one chip of FPGA, one chip of DSP and
one chip of D/A converter. The A/D converter is
designed with the maximum sampled rate at 1.2GHz,
the DRFM system based this board has the bandwidth
coverage from 40KHZ to 600MHz, the sampled data
transfer into FPGA for the temporary storage after
demux, the modulation process in finished in real-
time inside of FPGA, and the modulate parameters are
get from DSP per PRT. The DSP also build the
interface between the board and desktop application
software through PCI protocol. The modulated signal
is send to D/A converter and transmitted to up-
converter.
4.1 The A/D selection and circuit design
The A/D converter (AT84AD001B) is selected
from ATMEL. The AT84AD001B is a monolithic
dual 8-bit A/D converter with low power consumption
and excellent digitizing accuracy. There are two A/D
converter core inside one chip, and the two core can
work stand alone, and they can also be configured to
work at interleave mode to achieve doubled sample
rate from the input clock rate. That also means we can
sample two channels to form the double sideband
DRFM or we can sample one channel input to form
single sideband DRFM with doubled sample rate. It
has integrated demultiplexer to slow down the
sampled data rate. The work mode and additional
parameter can be configured through 3-wire Serial
Interface.
The analog input must be changed into differential
mode according to the requirement of the
AT84AD001B, so the RF transformer is selected to
transfer the signal-end analog signal into differential
mode; the front end circuit design for the analog input
implementation is shown in Fig.4.
Fig 3 The adjustment circuit for A/D input
The clock for the AT84AD001B is differential or
single-end 50 Ω PECL/LVDS compatible and the
clock path must be AC coupled with 100 nF capacitor,
the circuit of transferring single-end pure sinusoidal
clock signal into PECL signal is designed to generate
high quantity clock, this part of circuit with PECL
termination is shown in Fig.5.
Fig 4 The clock transfer circuit
The sampled 8-bit data output from the chip in
LVDS differential mode, the termination with 100 Ω
resistors should be done in the receiver side, which is
finished inside of the FPGA chip using digitally
controlled impedance (DCI) technique.
The effective number of bits (ENOB) in the whole
bandwidth at the sampling frequency of 1.2GHz is
drawn in Fig.6.
ENOB Versus Input Frequency,(Fs = 1.2GHz)
8
6
ENOB(Bit)
4
2
0
0 200 400 600
Fin(MHz)
Fig 5 The ENOB plot of the A/D performance
4.2 The FPGA selection and special features
The Virtex4sx35 from Xilinx is selected as the
main processor in the center of the board, take the
advantage of its high-performance IO compatible with
different IO standard, it can connected with all other
chips without complex transfer circuit. The FPGA
also connected with the J4/J5 and connecter at the
front edge of the board to make the system flexible
with the function extension. The total block ram
inside of the Virtex4sx35 is 3456Kb, with the sample
rate of 1.2GHz, resolution of 8-bit, the maximum
radar pulse length that can stored inside of the FPGA
is 360us without decimation. The Virtex4sx35 also
contain 192 XtremeDSP slices and abundant logic
slices, which make it possible to program the
Virtex4sx35 to undertake the modulation in
amplitude, phase and Doppler frequency.
4.3 The DSP selection and special features
The TMS320C6416 from Texas Instrument is
chosen to performance the parameter calculation
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updated per PRT, the FPGA chip is connected in the
EMIFA of the DSP chip, the communication between
DSP and FPGA is established with the maximum data
transfer rate at 100 Mhz .
The PCI port supports the connection of the DSP
to a PCI host via the integrated PCI master/slave bus
interface inside of the TMS320C6416.So the desktop
application software can interrupt the loop of DSP
program to transfer the command and parameter to
control of the whole system.
4.4 The D/A selection and circuits design.
The AD9776 from Analog Devices is selected as
the D/A converter of the system, The AD9776 are
dual 12-bit, high dynamic range DACs with the
maximum sample rate at 1GHz, thus permitting
multicarrier generation up to its Nyquist frequency.
The clock of the AD9776 is provided by
Virtex4sx35 with LVDS standard, so the clock
transfer circuit is designed to meet the requirement of
the chip, as shown in Fig.7.
Fig 6 The LVDS transfer circuit to provide the
clock for D/A
The board described above takes the advantages
of the modern ADC, DAC, FPGA, DSP techniques
and has been used as the core part for certain radar
countermeasure system, with the serious board level
design discipline the ideal performance is achieved.
5. Conclusions
The hardware design requirement for the DRFM
system is analyzed and the board-level design
disciplines are stated, the engineering example is
given with the detailed circuit explanation. The
participating of the FPGA greatly changes the
architecture design for DRFM system, the hardware
platform is greatly simplified due to features of FPGA
technique. With the development of the IC technique,
integrate the whole DRFM system on one single chip
become possible in the near future.
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6. References
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[3] Q. Cheng, Z. Shi, P. Dong, and B. He. “Application of
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[4] M. Soumekh. “SAR-ECCM using phase-perturbed LFM
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