Analog and RF Design, 1st sem M.

Tech (DEAC & Micro)

Assignment 1
Q1(a) Show that the transconductance of the MOSFET, operated in
saturation, (i) increases with the overdrive potential for a given aspect
ratio; (ii) decreases with the overdrive potential if 𝐼𝑑𝑠 is constant.

Q1(b) Determine the output resistance of an n-channel MOSFET with L =

W = 20 µm. Given that Vthn = 0.83 V (neglecting bulk effect), K n =
50 µA/V 2 , λ = 0.06 V −1 , VDS = VGS = 2 V. What is the value of overdrive
potential?

Q1(c) For a NMOS transistor with a channel aspect ratio W/L =

10, μn Cox = 100 uA/V , Vthn = 0.83 V, λ=0.06 V-1. Given the terminal
2

voltages Vgs = 1.33 V, (Vds- Vsat) =2V. Find the value of Ids of the device
considering the channel length effect.

Q1(d) Compare the output impedance in the below given cases:

Q1(e) For a NMOS transistor with a channel aspect ratio W/L = 10, 𝐾𝑛 =
100 𝑢𝐴/𝑉 2 , Vthn = 0.83 V, λ = 0.06 V-1. Given the terminal voltages Vgs =
1.2 V, Vds = 2V. Find the value of Ids and transconductance of the
device considering the channel length effect.

Q1(f) Define the following MOS model parameters:

[i] λ
[ii] Early voltage VA

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 Q1(g) Why long-channel devices are preferred in analog design?

Q1(h) Calculate the input resistance of the circuit shown in FIG. Q1(h).
V
DD

V M
B 1

Z
in X

FIG. Q1(h)

Q2. Design a 10 μA n-channel current sink. Using this current

reference, design the following:
(i) current sink with value of 50 μA.
(ii) current source with value of 100 μA.
Give the plot of Io versus Vo for case (ii) showing the value of Rout and
the Vout,min . Given that µn≈ 2.5µp, Kp= 20 μA/V2, η=0.1, λ= 0.06 V-1, Vthn=
0.83 V, Vthp=-0.91 V, Vgs= 1.2 V, VDD= 2.5 V, VSS = -2.5V.

Q3. Design a double cascode current mirror to sink a current of 10 μA.

Find the minimum voltage across the current sink and the output
resistance. Given that Kn = 50 μA/V2 , Vgs = 1.2 V, Vthn = 0.83 V, Vthp =-0.91
V, λ = 0.06 V-1, VDD = 2.5 V, VSS = -2.5V

Q4. Using the 10 μA n-channel current reference, design two current sinks
with values of 50, 100 μA. Assume Vdd = 2.5 V, Vss = -2.5V. What is the
minimum voltage across each current sink? What is the value of small-
signal output resistance of the current sink? Given that µn. Cox = 50 μA/V2,
µp. Cox = 17 μA/V2, λ = 0.06 V-1, Vthn = 0.83 V, Vthp = 0.91 V, Vgs = 1.2 V.
Assume L = 5 μm.

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Q5. [i] Among following which one affects the performance of current
mirror and why? (oxide encroachment, lateral diffusion)

[ii] What do you mean by ‘width correction’?

Q6. Explain how the performance of current mirror is affected by oxide

encroachment and lateral diffusion. With a Layout diagram, explain the
‘width correction’ as applied to simple current mirror shown below:

20 um
5 um
M M
1 2 5 um
5 um

V
ss

Q7. Derive an expression for sensitivity of output current Io with respect

to VDD in a cascode current sink circuit. Explain the significance of this
sensitivity expression.

Q8. With a circuit diagram, obtain an expression for Sensitivity of Io wrt

R in a cascode current mirror. Given that Vgs = 1.2 V, Vdd = 5 V, Vss = 0
V. Give your comments.

Q.9 Estimate the variation in Io for the basic current mirror for Vdd
changing from 2.4 V to 2.6 V. Find the sensitivity of Io wrt Vdd.

Q10. Compare the performance of simple current sink with that of

cascode current sink and Wilson current mirror.

Q.11. Design a 3 V voltage reference using the MOS-only voltage divider

assuming Vdd = + 5 V and Vss = 0 V. Given that Kn= 50 uA/V2, Kp= 17 uA/V2
Vthn = 0.8 V and I Vthp I = 0.9 V.

(Ans: L1 = L2 = W1 = 5 μm, W2 = 60 μm)

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Q12. Design a 2 V and 3.5 V voltage reference using the three-MOSFET
voltage divider assuming Vdd = + 5 V and Vss = 0 V. The drain currents of
the MOSFETs is 10 μA. Given that Kn= 50 uA/V2, Kp= 17 uA/V2 Vthn = 0.8 V
and I Vthp I = 0.9 V, L1 = L2 = L3 = 20 μm

(Ans: W1 = 5 μm, W2 = W3 = 65 μm)

Q13. Explain how a 3-MOSFET voltage divider circuit can be used to bias
cascode current sink.
Q14. Derive an expression for following in a cascode current sink circuit:
[i] Rout [ii] Sensitivity of Io wrt VDD
Q15. Given that Vthp = -0.6 V, K p = 250 μA/V 2 ,W⁄L = 5/1, Gamma γ = 0.1
( γ is body effect coefficient), PHI = 2ϕF = 0.7 V. Calculate ID

VTH = VTH0 + γ(√|2ϕF + VSB | − √|2ϕF |)

where γ is bulk effect coefficient [unit : √V ] [γ = √2qƐSi Nsub ⁄Cox ]
PHI = 2ϕF is surface inversion potential [unit : volt]
(Ans: VTHP = −0.6895 V ; ID = 60.0625 μA)
Q16. Find the voltage V at the source of the upper transistor in the NMOS circuit
x
2
given. Given that µ C = 100 µA/V , V = 1 V.
n ox th

***

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 Assignment 2
Q1. Calculate the small-signal voltage gain Av for NMOS (M1) CS stage
with diode-connected PMOS load (M2). Given that (W/L)1 = 50/0.5, (W/L)2
= 10/0.5, µn = 2.5 µp and Ids1 = Ids2 = 0.5 mA. Assume λ = 0.
Q2. Calculate the small-signal voltage gain of the circuit shown below.
V
dd

M
M 3
2

V
o
M
V 1
i R
L

0 0

Q3. Find the expression for small-signal voltage gain for the below given
amplifier.

Q5. Give the schematic circuit of NMOS common source amplifier with a
current mirror active load. Assume all transistors have W⁄L =
100 µm⁄1.8 µm and K n = 90 µA/V , K P = 30 µA/V , Ib = 100 µA, λn =
2 2

0.06 V −1 , λp = 0.05 V −1 . Find the voltage gain and output resistance.

Q6. Draw the circuit of PMOS based common-source amplifier circuit with
current mirror active load. Derive the expression for voltage gain using
small-signal ac model