Volume 6, Issue 3, March 2016 ISSN: 2277 128X

International Journal of Advanced Research in

Computer Science and Software Engineering
Research Paper
Available online at: www.ijarcsse.com
Special Issue on 3rd International Conference on Electronics & Computing Technologies-2016
Conference Held at K.C. College of Engineering & Management Studies & Research, Maharashtra, India
Power Optimization for Low Power VLSI Circuits
Sumita Gupta Sukanya Padave
Department of ETRX, KCCEMSR, Department of EXTC, KCCEMSR,
Thane, Maharashtra, India Thane, Maharashtra, India

Abstract- This paper, presents a concept of the power optimization theory approach , the estimation techniques and
optimization circuits used for low power VLSI circuits. In newer technologies, power is a primary design constraint.
Power dissipation has skyrocketed due to transistor scaling, chip transistor counts and clock frequencies. Successful
chip design requires low power consideration, and determination of the locations (spots) on the die where power
dissipation occurs. The need for low power design is also becoming a major issue in high performance digital system
such as microprocessor and digital integrated circuits. The methodologies which we use for low power circuits spans a
wide range from device or process level to algorithm level.

Keywords- optimization, VLSI, switching power, short circuit, leakagepower, voltagescaling, subthresholdleakage,
pipeliningapproach, parallel processing approach, switched capacitance, clock gating

I. INTRODUCTION
In earlier design area, performance ,cost & reliability was the major problem & power consideration was of only
secondary importance.[7]The development of competitive market sectors such as wireless applications, laptops, and
portable medical devices, depends on the power dissipation as the most important parameter because the growth rate of
the battery technologies is not so promising. According to morre „s law semiconductor technology will double in every
18 months.& simultaneously device count & clock frequency are increasing exponentially [8] hence Power dissipation is
recognized as a critical parameter in modern VLSI design field due to high chip density & high frequency.

Figure 1.Morre‟s Law

The average power consumption in CMOS circuits consists of I) Dynamic or switching power consumption II) Short
circuit Power consumption III) Leakage power consumption IV) static power consumption.

A. Dynamic(switching) Power Dissipation

Dynamic power dissipation can be further subdivided into three mechanisms: switched, short-circuit, and glitch
power dissipation. All of them more or less depend on the activity, timing, output capacitance, and supply voltage of the
circuit. The repeated charging and discharging of the output capacitance is necessary to transmit information in CMOS
circuits. This charging and discharging of the node capacitances causes for the switched power dissipation. The power
consumption of a CMOS digital circuit can be represented as

Figure 2 .A NOR gate driving two NAND gate through interconnection lines[5]
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 Gupta et al., International Journal of Advanced Research in Computer Science and Software Engineering 6 (3),
March- 2016, pp. 96-99
B. Short Circuit Power Dissipation
In real circuits signals have non-zero rise and fall times which causes both the P net and the N net of the CMOS gate
to conduct current simultaneously that means both nmos and pmos transistors may conduct simultaneously for short
amount of time during switching .This current does not contribute to the charging of capacitance in the circuit ,it is called
short circuit current consumption, This component is especially prevalent if the output load capacitance is small and /or
if the input signal rise time and fall times are large.

C. Leakage Power Dissipation

In VLSI CMOS circuits leakage current is mainly determined by processing parameters. Generally we use CMOS
logic gates in our IC but if the system or chip includes other circuits that have continuous current path between power
supply and ground then this static component of power is considered. It consists of reverse bias current &sub threshold
current[4]. Dynamic power is only when there is switching but leakage power is permanent but it can be small with
proper choice of device technology.Subthreshold leakage is the major component in all leakage at technology greater
than 130 nm.[9]

D. Static Power dissipation

The static power components become important when the circuits are at rest, i.e. when there is no activity in the
circuits and they are all biased to a specific state. The static power dissipation includes sub threshold and reversed-biased
diode leakage currents. Due to the necessary but harmful (in a leakage-power sense) down-scaling of threshold voltages,
the sub threshold leakage is becoming more and more pronounced. Below the threshold voltage, in weak inversion, the
transistors are not completely off. The sub threshold current has a strong dependence on the threshold voltage.

Figure 3.Various power consumption

P = α f CL VDD2 + VDDIshort-circuit+ VDDIleakage +VDDIstatic [5]

Where f is the clock frequency , C is the average switched Capacitance per clock cycle, V DD is the supply voltage ,
Ishort-circuit is the short circuit current and Ileakageis the leakage current. In a well optimized low power VLSI circuits, the Ist
term of this equation is by far the dominant. The standby power consumption is accounted for by the 3rd term[1]. Using a
lower VDD is an effective way to reduce the dynamic power consumption since Ist term is proportional to the square of
VDD.It should also be noted that the short circuit and leakage power dissipation are also strongly dependent on
VDD.However, using a lower VDD degrades performance.

II. OPTIMIZATION AT VARIOUS LEVEL OF ABSTRACTION

An integrated low power methodology requires optimization at all design abstraction layers as mentioned below.
1. System: Partitioning, Power down
2. Algorithm: Complexity, Concurrency, Regularity
3. Architecture: Parallelism, Pipelining, Redundancy, Data Encoding
4. Circuit Logic: Logic Styles, Energy Recovery, Transistor Sizing
5. Technology: Threshold Reduction, Multithreshold Devices.

Figure 4. Different level of Abstraction

A. System level
Accurate power analysis tools are available at circuit or gate level but not for system level.[1]

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 Gupta et al., International Journal of Advanced Research in Computer Science and Software Engineering 6 (3),
March- 2016, pp. 96-99
Partitionning
Traditionally, the objective functions for partitioning have been the cut-size and/or the circuit delay while the
constraints have been I/O pin count per block and block size. Partitioning for low power has recently become an
important problem.

B. Algorithm level
Here behavioral modeling is included It refers to the process of mapping a high level specification of a problem into
register transfer level design.[1]

C. Architecture level
Pipelining
In this approach both input &output vectors are sampled through register array & driven by a clock signal. By using
pipeline structure the supply voltage will be reduced but while trading off area for lower power, this approach also
increases the latency but latency is not a significant concern
Parallel Processing approach (Hardware Replication) Parallism is also used for trading off area for low power
dissipation.

D. Circuit level
Transistor sizing
Transistor sizing in a combinational gate circuit can have significant impact on circuit delay and power dissipation.
If the transistors in a given gate are increased in size, then the delay of the gate decreases,. Further, the delay of the fanin
gates increases because of increased load capacitance[1] .

E. Technology level
Multiple Threshold
Modern processes can build transistors with different thresholds. Power can be saved by using a mixture of CMOS
transistors with two or more different threshold voltages. In the simplest form there are two different thresholds
available, common called High-Vt and Low-Vtwhere Vt stands for threshold voltage. High threshold transistors are
slower but leak less, and can be used in non-critical circuits.

III. OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI

There is no universal technique to cut tradeoffs between power consumption, delay and area and so, designers are
required to select suitable and efficient techniques that satisfy application and product needs[10].
Reduction of switching capacity,
clock gating
Reduction of switched capacitance
Voltage Scaling

A. Reduction of switched capacitance

Reducing the switched capacitance is similar power efficient as reducing the clock frequency of circuit. Many
advanced techniques have been proposed to reduce the switched capacitance.[3] The selection of logic style can
significantly affect the critical capacitances. Whenever alow-power solution is searched for, conventional static CMOS is
often a safe and efficient and Multiplexers and OR gates are an exception since they can be implemented in pass-
transistor logic styles using fewer transistors. In flip-flops and registers, the capacitance of the clock nodes is important
since the clock signal has a high activity. So, he flip-flops with a small number of clocked transistors have been
proposed[3]

B. Clock gating
It is known as clock frequency reduction & mostly used as a conjunction with other low power techniques.[3]

C. Voltage scaling
It is more beneficial than clock gating .Pipelining & Hardware replication approach is used for voltage scaling[3]
.Power dissipation of all the four components depend on supply voltage ,Hence voltage scaling is the attractive solution
for reducing it but sub threshold leakage will increase exponentially.

IV. OPTIMIZATION CIRCUITS USED IN VLSI

Adiabetic logic circuit
The term adiabetic is typically used to describe thermodynamic processes that have no energy exchange with the
environment hence no energy loss in the form of heat .Hence adiabetic logic provides the possibility of recycling or
reusing ,some of the energy drawn from the power supply Adiabatic logic works with the concept of switching activities
which reduces the power by giving stored energy back to the supply. Thus, the term adiabatic logic is used in low-power
VLSI circuits which implements reversible logic. In this, the main design changes are focused in power clock which
plays the vital role in the principle of operation. Diodes are not used inthe design of Adiabatic Logic because of

© 2016, IJARCSSE All Rights Reserved Page | 98

 Gupta et al., International Journal of Advanced Research in Computer Science and Software Engineering 6 (3),
March- 2016, pp. 96-99
thermodynamically irreversible nature Each phase of the power clock gives user to achieve the two major design rules for
the adiabatic circuit design.
Ex SZ Never turn on a transistor if there is a voltage across it (V DS> 0)
Never turn off a transistor if there is a current through it (I DS ≠ 0)
Never pass current through a diode
If these conditions with regard to the inputs, in all the four phases of power clock, recovery phase will restore the
energy to the power clock, resulting considerable energy saving On valid input, the pass gate is turned on by gradually
swinging P and /P. Rails f and /f"split", gradually swinging to threshold voltage (Vdd) and Gnd. Pass gate is turned off as
soon as output is sampled,. Internal node is restored by gradually swinging f and Vdd/2.Once the electronic device is
turned on energy transfer takes place in a controlled manner so that there is no potential drop across the device[3]

Figure 5 Charge Recovery Logic

A. Sleep transistor
The static power can be reduced by using sleep transistors.]3] Sleep Transistors are High Vt transistors connected in
series with low Vt logic as shown below .When the main circuit consisting of Low Vt devices are ON the sleep
transistors are also ON resulting in normal operation of the circuit. Since High threshold (Vt )is connected in series with
Low threshold (Vt) circuit the leakage current power loss is measured by High threshold (Vt) devices and is quiet
low.Therefore, the resultant static power dissipation is reduced[6].

Figure 6. Sleep transistor

V. CONCLUSION
Here we have discussed the concept of power optimization, its techniques & the circuits we used for this. Lowering
power dissipation at all abstraction levels is a focus of intense academic and industrial research.. A reduction of any
parameters like input rise time, source leakage current, Gate current, Switching power, short-circuit power, power-
dissipation capacitance, and output loading affect is beneficial for us and, provides low cost product to the consumer

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