Bipolar-Junction (BJT) transistors

References: Hayes & Horowitz (pp 84-141),

Rizzoni (chapters 8 & 9)
A bipolar junction transistor is formed by joining three sections of semiconductors with
alternatively different dopings. The middle section (base) is narrow and one of the other two
regions (emitter) is heavily doped. Two variants of BJT are possible: NPN and PNP.
C NPN Transistor C PNP Transistor
C C C C
n p
B B B B B B
p n

n+ p+
E E E E

E Circuit Symbols E Circuit Symbols

Behavior of NPN BJT is discussed below. Operation of a PNP transistor is analogous to

that of a NPN transistor except that the role of charge carries reversed. In NPN transistors,
electron flow is dominant while PNP transistors rely mostly on the flow of “holes.” Therefore,
to zeroth order, NPN and PNP transistors behave similarly except the sign of current and
voltages are reversed. i.e., PNP = − NPN ! In practice, NPN transistors are much more
popular than PNP transistors because electrons move faster in a semiconductor. As a results,
a NPN transistor has a faster response time compared to a PNP transistor.

At the first glance, a BJT looks like 2 diodes placed back to back.
Indeed this is the case if we apply voltage to only two of the three
terminals, letting the third terminal float. This is also the way that
we check if a transistor is working: use an ohm-meter to ensure both
diodes are in working conditions. (One should also check the resistance
between CE terminals and read a vary high resistance as one may have
a burn through the base connecting collector and emitter.)
The behavior of the BJT is different, however, when voltage sources are
attached to both BE and CE terminals. The BE junction acts like a
diode. When this junction is forward biased, electrons flow from emitter
to the base (and a small current of holes from base to emitter). The
base region is narrow and when a voltage is applied between collector
and emitter, most of the electrons that were flowing from emitter to
base, cross the narrow base region and are collected at the collector
region. So while the BC junction is reversed biased, a large current can
flow through that region and BC junction does not act as a diode.
The amount of the current that crosses from emitter to collector region depends strongly
on the voltage applied to the BE junction, vBE . (It also depends weakly on voltage applied

ECE60L Lecture Notes, Winter 2002 45

between collector and emitter, vCE .) As such, small changes in vBE or iB controls a much
larger collector current iC . Note that the transistor does not generate iC . It acts as a valve
controlling the current that can flow through it. The source of current (and power) is the
power supply that feeds the CE terminals.
iC
A BJT has three terminals. Six parameters; iC , iB , iE , vCE , vBE , and
vCB +
vCB ; define the state of the transistor. However, because BJT has three iB
_
+
vCE
terminals, KVL and KCL should hold for these terminals, i.e., +
vBE _ _
iE = i C + i B vBC = vBE − vCE iE

Thus, only four of these 6 parameters are independent parameters. The relationship among
these four parameters represents the “iv” characteristics of the BJT, usually shown as i B vs
vBE and iC vs vCE graphs.

The above graphs show several characteristics of BJT. First, the BE junction acts likes
a diode. Secondly, BJT has three main states: cut-off, active-linear, and saturation. A
description of these regions are given below. Lastly, The transistor can be damaged if (1) a
large positive voltage is applied across the CE junction (breakdown region), or (2) product
of iC vCE exceed power handling of the transistor, or (3) a large reverse voltage is applied
between any two terminals.
Several “models” available for a BJT. These are typically divided into two general categories:
“large-signal” models that apply to the entire range of values of current and voltages, and
“small-signal” models that apply to AC signals with small amplitudes. “Low-frequency” and
“high-frequency” models also exist (high-frequency models account for capacitance of each
junction). Obviously, the simpler the model, the easier the circuit calculations are. More
complex models describe the behavior of a BJT more accurately but analytical calculations
become difficult. PSpice program uses a high-frequency, Eber-Mos large-signal model which
is a quite accurate representation of BJT. For analytical calculations here, we will discuss a
simple low-frequency, large-signal model (below) and a low-frequency, small-signal model in
the context of BJT amplifiers later.

ECE60L Lecture Notes, Winter 2002 46

A Simple, Low-frequency, Large Signal Model for BJT:
As the BE junction acts like a diode, a simple piece-wise linear model can be used :

BE Junction ON: vBE = vγ , and iB > 0

BE Junction OFF: vBE < vγ , and iB = 0

where vγ is the forward bias voltage (vγ ≈ 0.7 V for Si semiconductors).

When the BE junction is reversed-biased, transistor is OFF as no charge carriers enter the
base and move to the collector. The voltage applied between collector and emitter has not
effect. This region is called the cut-off region:

Cut-Off: vBE < vγ , iB = 0, i C ≈ iE ≈ 0

Since the collector and emitter currents are very small for any vCE , the effective resistance
between collector and emitter is very large (100’s of MΩ) making the transistor behave as
an open circuit in the cut-off region.
When the BE junction is forward-biased, transistor is ON. The behavior of the transistor,
however, depends on how much voltage is applied between collector and emitter. If vCE > vγ ,
the BE junction is forward biased while BC junction is reversed-biased and transistor is in
active-linear region. In this region, iC scales linearly with iB and transistor acts as an
amplifier.

iC
Active-Linear: vBE = vγ , iB > 0, = β ≈ constant, vCE ≥ vγ
iB

If vCE < vγ , both BE and BC junctions are forward biased. This region is called the
saturation region. As vCE is small while iC can be substantial, the effective resistance
between collector and emitter in saturation region is small and the BJT acts as a closed-
circuit.

iC
Saturation: vBE = vγ , iB > 0, < β, vCE ≈ vsat
iB

Our model specifies vCE ≈ vsat , the saturation voltage. In reality in the saturation region
0 < vCE < vγ . As we are mainly interested in the value of the collector current in this region,
vCE is set to a value in the middle of its range in our simple model: vCE ≈ vsat ∼ 0.5vγ .
Typically a value of vsat ≈ 0.2 − 0.3 V is used for Si semiconductors.

ECE60L Lecture Notes, Winter 2002 47

The above simple, large-signal model is shown below. A comparison of this simple model
with the real BJT characteristics demonstrates the degree of approximation used.
Saturation
iB iC

BJT ON Active Linear

BJT OFF

vγ vBE vsat vCE

Cut Off

How to Solve BJT Circuits:

The state of a BJT is not known before we solve the circuit, so we do not know which model
to use: cut-off, active-linear, or saturation. To solve BJT circuits, we need assume that
BJT is in a particular state, use BJT model for that state to solve the circuit and check
the validity of our assumptions by checking the inequalities in the model for that state. A
formal procedure will be:
1) Write down a KVL including the BE junction (call it BE-KVL).
2) Write down a KVL including CE terminals (call it CE-KVL).
3) Assume BJT is in cut-off (this is the simplest case). Set iB = 0. Calculate vBE from
BE-KVL.
3a) If vBE < vγ , then BJT is in cut-off, iB = 0 and vBE is what you just calculated. Set
iC = iE = 0, and calculate vCE from CE-KVL. You are done.
3b) If vBE > vγ , then BJT is not in cut-off. Set vBE = vγ . Solve above KVL to find iB . You
should get iB > 0.
4) Assume that BJT is in active linear region. Let iE ≈ iC = βiB . Calculate vCE from
CE-KVL.
4a) If vCE > vγ , then BJT is in active-linear region. You are done.
4b) If vCE < vγ , then BJT is not in active-linear region. It is in saturation. Let vCE = vsat
and compute iC from CE-KVL. You should find that iC < βiB . You are done.

ECE60L Lecture Notes, Winter 2002 48

Example 1: Compute the parameters of this circuit (β = 100). 12 V

Following the procedure above: 1 kΩ

iC
BE-KVL: 4 = 40 × 103 iB + vBE +
40 kΩ iB
CE-KVL: 3
12 = 10 iC + vCE , vCE
+
+ 4V vBE _ _
-
Assume BJT is in cut-off. Set iB = 0 in BE-KVL: iE

BE-KVL: 4 = 40 × 103 iB + vBE → vBE = 4 > vγ = 0.7 V

So BJT is not in cut off and BJT is ON. Set vBE = 0.7 V and use BE-KVL to find iB .

4 − 0.7
BE-KVL: 4 = 40 × 103 iB + vBE → iB = = 82.5 µA
40, 000

Assume BJT is in active linear, Find iC = βiB and use CE-KVL to find vCE :

iC = βiB = 100iB = 8.25 mA

CE-KVL: 12 = 1, 000iC + vCE , → vCE = 12 − 8.25 = 3.75 V

As vCE = 3.75 > vγ , the BJT is indeed in active-linear and we have: vBE = 0.7 V, iB =
82.5 µA, iE ≈ iC = 8.25 mA, and vCE = 3.75 V.

Example 2: Compute the parameters of this circuit (β = 100). 12 V

Following the procedure above:

1 kΩ

BE-KVL: 4 = 40 × 103 iB + vBE + 103 iE iC

40 kΩ iB +
CE-KVL: 12 = 1, 000iC + vCE + 1, 000iE vCE
+
+ 4V vBE _ _
Assume BJT is in cut-off. -
iE
Set iB = 0 and iE = iC = 0 in BE-KVL:
1 kΩ

BE-KVL: 4 = 40 × 103 iB + vBE + 103 iE → vBE = 4 > 0.7 V

So BJT is not in cut off and vBE = 0.7 V and iB > 0. Here, we cannot find iB right away
from BE-KVL as it also contains iE .

ECE60L Lecture Notes, Winter 2002 49

Assume BJT is in active linear, iE ≈ iC = βiB :

BE-KVL: 4 = 40 × 103 iB + vBE + 103 βiB

4 − 0.7 = (40 × 103 + 103 × 102 )iB
iB = 24 µA → iE ≈ iC = βiB = 2.4 mA
CE-KVL: 12 = 1, 000iC + vCE + 1, 000iE , → vCE = 12 − 4.8 = 7.2 V

As vCE = 7.2 > vγ , the BJT is indeed in active-linear and we have: vBE = 0.7 V, iB = 24 µA,
iE ≈ iC = 2.4 mA, and vCE = 7.2 V.

Load line

The operating point of a BJT can be found graphically using the concept of a load line. A
load line is the relationship between iC and vCE that is imposed on BJT by the external
circuit. For a given value of iB , the iC vCE characteristics curve of a BJT is the relationship
between iC and VCE as is set by BJT internals. The intersection of the load line with the
BJT characteristics represent a pair of iC and vCE values which satisfy both conditions and,
therefore, is the operating point of the BJT (often called the Q point for Quiescent point)
The equation of a load line for a BJT should include only iC and vCE (no other unknowns).
This equation is usually found by writing a KVL around a loop containing vCE . For the
example above, we have (using iE ≈ iC ):

KVL: 12 = 1, 000iC + vCE + 1, 000iE → 2, 000iC + vCE = 12

An example of a load line, iC vCE characteristics of a BJT, and the Q-point is shown below.

BJT as an amplifier

Consider the circuit below. The operating point of the BJT is shown in the iC vCE space.

iC

RB iB + RC
vCE
+
vBE _ _
VCC
iE
VBB

ECE60L Lecture Notes, Winter 2002 50

Let us add a sinusoidal source with an amplitude of ∆VBB in series with VBB . In response to
this additional source, the base current will become iB + ∆iB leading to the collector current
of iC + ∆iC and CE voltage of vCE + ∆vCE .

i C +∆ i C

RB i B +∆ i B + RC
vCE +∆ vCE
+
+ vBE +∆ vBE _ _
~
− ∆ VBB VCC

VBB

For example, without the sinusoidal source, the base current is 150 µA, iC = 22 mA, and
vCE = 7 V (the Q point). If the amplitude of ∆iB is 40 µA, then with the addition of the
sinusoidal source iB + ∆iB = 150 + 40 cos(ωt) and varies from 110 to 190 µA. The BJT
operating point should remain on the load line and collector current and CE voltage change
with changing base current while remaining on the load line. For example when base current
is 190 µA, the collector current is 28.6 mA and CE voltage is about 4.5 V. As can be seen
from the figure above, the collector current will approximately be iC +∆iC = 22+6.6 cos(ωt)
and CE voltage is vCE + ∆vCE = 7 − 2.5 cos(ωt).
The above example shows that the signal from the sinusoidal source ∆VBB is greatly amplified
and appears as changes either in collector current or CE voltage. It is clear from the figure
that this happens as long as the BJT stays in the active-linear region. As the amplitude of
∆iB is increased, the swings of BJT operating point along the load line become larger and
larger and, at some value of ∆iB , BJT will enter either the cut-off or saturation region and
the output signals will not be a sinusoidal function.
Note: An important observation is that one should locate the Q point in the middle of the
load line in order to have the largest output signal. For this reason, in design problems, vCE
of the Q point is usually chosen to be half of the bias voltage VCC : vCE,Q = 0.5 ∗ VCC .
The above circuit, however, has two major problems: 1) The input signal, ∆VBB , is in series
with the VBB biasing voltage making design of previous two-port network difficult, and 2)
The output signal is usually taken across RC as RC × iC . This output voltage has a DC
component which is of no interest and can cause problems in the design of the next-stage,
two-port network.
The DC voltage needed to “bias” the BJT (establish the Q point) and the AC signal of
interest can be added together or separated using capacitor coupling as discussed below.

ECE60L Lecture Notes, Winter 2002 51

Capacitive Coupling
For DC voltages (ω = 0), the capacitor is an open circuit (infinite impedance). For AC
voltages, the impedance of a capacitor, Z = −j/(ωC), can be made sufficiently small by
choosing an appropriately large value for C (the higher the frequency, the lower C that one
needs). This property of capacitors can be used to add and separate AC and DC signals.
Example below highlights this effect.
Consider the circuit below which includes a DC source of +15 V
15 V and an AC source of vi = Vi cos(ωt). We are inter-
ested to calculate voltages vA and vB . The best method R2

to solve this circuit is superposition. The circuit is bro- A C1

B
ken into two circuits. In circuit 1, we “kill” the AC source vi
and keep the DC source. In circuit 2, we “kill” the DC + R1
−
source and keep the AC source. Superposition principle
states that vA = vA1 + vA2 and vB = vB1 + vB2 .

+15 V +15 V
R2 + R2 + R2
C1 − C1 − C1
vA vA1 vA2
v v v
B B1 B2
vi + vi
+ R1 R + R
1 1
− −

Consider the first circuit. It is driven by a DC source and, therefore, the capacitor will act
as open circuit. The voltage vA1 = 0 as it is connected to ground and vB1 can be found by
voltage divider formula: vB1 = 15R1 /(R1 + R2 ). As can be seen both vA1 and vB1 are DC
voltages.
In the second circuit, resistors R1 and R2 are in parallel. Let Rb = R1 k R2 . The circuit
is a high-pass filter: VA2 = Vi and VB2 = Vi (Rb )/(Rb + 1/jωC). If we operate the circuit
at frequency above the cut-off frequency of the filter, i.e., Rb  1/ωC, we will have VB2 ≈
VA2 = Vi and vB2 ≈ vA2 = Vi cos(ωt). Therefore,

vA = vA1 + vA2 = Vi cos(ωt)

R1
vB = vB1 + vB2 = × 15 + Vi cos(ωt)
R1 + R 2

Obviously, the capacitor is preventing the DC voltage to appear at point A, while the voltage
at point B is the sum of DC signal from 15-V supply and the AC signal.

ECE60L Lecture Notes, Winter 2002 52

Using capacitive coupling, we can reconfigure our previous amplifier circuit as is shown in
the figure below. Capacitive coupling is used extensively in transistor amplifiers.
vCE +∆ vCE ∆ vCE

i C +∆ i C

RB i B +∆ i B + RC
∆ VBB vCE +∆ vCE
+
+ vBE +∆ vBE _ _
~
− VCC

VBB

BJT amplifier circuits are analyzed using superposition principle, similar to example above:
1) DC Biasing: Input signal is set to zero and capacitors act as open circuit. This analysis
establishes the Q point in the active linear region.
2) AC analysis: DC bias voltages are set to zero. The response of the circuit to an AC input
signal is calculated and transfer function, input and output impedances, etc. are found.
The break up of the problem into these two parts have an additional advantage as the
requirement for accuracy are different in the two cases. For DC biasing, we are interested
in locating the Q point roughly in the middle of active linear region. The exact location of
the Q point is not important. Thus, a simple model, such as large-signal model of page 49 is
quite adequate. We are, however, interested to compute the transfer function for AC signals
quite accurately. Our large-signal model is not good for the desired accuracy and we will
develop a model which is accurate for small AC signals below.
To avoid confusion, we follow the following convention: We use capital letters to denote DC
component (e.g., IC ) and small letters to denote AC components(e.g., vCE )
VCC
DC Biasing
A simple bias circuit is shown. As we like to have only one power
RB RC
supply, the base circuit is also powered by VCC . Assuming that
iC
BJT is in active-linear state, we have:
iB +
vCE
VCC − VBE +
BE-KVL: VCC = IB RB + VBE → IB = vBE _ _
RB
VCC − VBE
IC = βIB = β
RB
CE-KVL: VCC = IC RC + VCE → VCE = VCC − IC RC
RC
VCE = VCC − β (VCC − VBE )
RB

ECE60L Lecture Notes, Winter 2002 53

For a given circuit (known RC , RB , VCC , and BJT β) the above equations can be solved to
find the Q-point (IB , IC , and VCE ). Alternatively, one can use the above equation to design
a BJT circuit (known β) to operate at a certain Q point. (Note: Do not memorize the above
equations or use them as formulas, they can be easily derived from simple KVLs).
Example 1: Find values of RC , RB in the above circuit with β = 100 and VCC = 15 V so
that the Q-point is IC = 25 mA and VCE = 7.5 V.
Since the BJT is in active-linear region (VCE = 7.5 > Vγ ), IB = IC /β = 0.25 mA. Writing
the KVLs that include VBE and VCE we get:

15 − 0.7
BE-KVL: VCC + RB IB + VBE = 0 → RB = = 57.2 kΩ
0.250
CE-KVL: VCC = IC RC + VCE → 15 = 25 × 10−3 RC + 7.5 → RC = 300 Ω

Example 2: Consider the circuit designed in example 1. What is the Q point if β = 200.
We have RB = 57.2 kΩ, RC = 300 Ω, and VCC = 15 V but IB , IC , and VCE are unknown.
They can be found by writing KVLs that include VBE and VCE :

VCC − VBE
BE-KVL: VCC + RB IB + VBE = 0 → IB = = 0.25 mA
RB
IC = β IB = 50 mA
CE-KVL: VCC = IC RC + VCE → VCE = 15 − 300 × 50 × 10−3 = 0

As VCE < vγ the BJT is not in active-linear region and the above equations are not valid.
Values of IC and VCE should be calculated using the BJT model for saturation region.
The above examples show the problem with our simple biasing circuit as the β of a com-
mercial BJT can depart by a factor of 2 from its average value given in the manufacturers’
spec sheet. Environmental conditions can also play an important role. In a given BJT,
IC increases by 9% per ◦ C for a fixed VBE . Consider a circuit which is tested to operate
perfectly at 25◦ C. At a temperature of 35◦ C, IC will be roughly doubled and the BJT will
be in saturation!
The problem is that our biasing circuit fixes the value of IB (independent of BJT parameters)
and, as a result, both IC and VCE are directly proportional to BJT β (see formulas in the
previous page). A biasing scheme should be found that make the Q-point (IC and VCE )
independent of transistor β and insensitive to the above problems → Use negative feedback!

ECE60L Lecture Notes, Winter 2002 54

 VCC
Stable biasing schemes
This biasing scheme can be best analyzed and understood if we
R1 RC
replace R1 and R2 voltage divider with its Thevenin equivalent:
iC
R2 +
VBB = VCC and RB = R1 k R2 iB
R1 + R 2 +
vCE

vBE _ _

The emitter resistor, RE is a sneaky feedback. Suppose IC R2 RE

becomes larger than the designed value (larger β, increase in
temperature, etc.). Then, VE = RE IE will increase. Since
VBB and RB do not change, KVL in the BE loop shows that VCC
Thevenin
IB should decrease which will reduce IC back to its design Equivalent

value. If IC becomes smaller than its design value opposite

{
RC

happens, IB has to increase and will increase and stabilize IC . iC

Analysis below also shows that the Q point is independent of RB iB +

vCE
+
BJT parameters: vBE _ _
+
IE ≈ IC = βIB − RE
VBB
VBB − VBE
BE-KVL: VBB = RB IB + VBE + IE RE → IB =
RB + βRE
CE-KVL: VCC = RC IC + VCE + IE RE → VCE = VCC − IC (RC + RE )

Choose RB such that RB  βRE (this is the condition for the feedback to be effective):

VBB − VBE
IB ≈
βRE
VBB − VBE
IC ≈
RE
RC + R E
VCE = VCC − IC (RC + RE ) ≈ VCC − (VBB − VBE )
RE

Note that now both IC and VCE are independent of β!

One can appreciate the working of this biasing scheme by comparing it to the poor biasing
circuit of page 55. In that circuit, IB was set by the values of VCC and RB . As a result,
IC = βIB was directly proportional to β. In this circuit, KVL in BE loop gives VBB =
RB IB + VBE + IE RE . If we choose RB IB  IE RE or RB  (IE /IB )RE ≈ βRE (feedback
condition above), the KVL reduces to VBB ≈ VBE +IE RE , forcing a constant IE independent
of BJT parameters. As IC ≈ IE this will also fixes the Q point of BJT. If BJT parameters
change (different β, change in temperature), the circuit forces IE to remain fixed and changes
IB !

ECE60L Lecture Notes, Winter 2002 55

Another important point follows from VBB ≈ VBE + IE RE . As VBE is not a constant and
can change slightly (can drop to 0.6 or increase to 0.8 V), we need to ensure that I E RE is
much larger than possible changes in VBE . As changes in VBE is about 0.1 V, we need to
ensure that VE = IE RE  0.1 or VE > 10 × 0.1 = 1 V.
Example: Design a stable bias circuit with a Q point of IC = 25 mA and VCE = 7.5 V.
Transistor β ranges from 50 to 200.
Step 1: Find VCC : As we like to have the Q-point to be located in the middle of the load
line, we set VCC = 2VCE = 2 × 7.5 = 15 V.
Step 2: Find RC and RE :

7.5
VCE = VCC − IC (RC + RE ) → RC + RE = = 3 kΩ
2.5 × 10−3

We are free to choose RC and RE (choice is usually set by the AC behavior which we will
see later). We have to ensure, however, that VE = IE RE > 1 V or RE > 1/IE = 400 Ω.
Let’s choose RE = 1 kΩ and RC = 2 kΩ for this example.
Step 3: Find RB and VBB : We need to set RB  βRE . As any commercial BJT has a range
of β values and we want to ensure that the above inequality is always satisfied, we should
use the minimum β value:

RB  βmin RE → RB = 0.1 ∗ 50 ∗ 1 = 5 kΩ
VBB ≈ VBE + IE RE = 0.7 + 2.5 × 10−3 × 103 = 3.2 V

Step 4: Find R1 and R2

R1 R2
RB = R 1 k R 2 = = 5 kΩ
R1 + R 2
VBB R2 3.2
= = = 0.21
VCC R1 + R 2 15

The above are two equations in two unknowns (R1 and R2 ). The easiest way to solve these
equations are to divide the two equations to find R1 and use that in the equation for VBB :

5 kΩ
R1 = = 24 kΩ
0.21
R2
= 0.21 → 0.79R2 = 0.21R1 → R2 = 6.4 kΩ
R1 + R 2

Reasonable commercial values for R1 and R2 are and 24 kΩ and 6.2 kΩ, respectively.

ECE60L Lecture Notes, Winter 2002 56