Baya - SoC Platform Assembly

Solution

EDA Utils,
Kanai Ghosh
Capabilities- Schematic Diagram
 Baya- Use Model Schematic
System VHDL IP-XACT Sub-
Verilog System
Baya Tcl
Cmd File

Baya Engine(80+ Powerful Tcl commands)

Click here to • Instance  instance pin connection – full or Click here to
watch the partial download complete
• Top module  instance connection
online demo of • Interface  Interface connection
list of Baya Tcl
this tool • Empty/Constant connection commands
• Auto connection – rule/pattern based
• Auto port creation
• Power Port connection – keeps inside `ifdef
• Conditional port connection – useful to integrate
multiple versions of an IP/SS
Click here to • Design hierarchy navigation & manipulation
download example • Importer/Exporter
• Helper utilities
Tcl commands to
build Leon
SubSystem
SoC/SubSystem RTL, SW
Integration Doc, Reports and
other Design Collaterals
 Baya-Steps in Tcl Comand mode
1. Import SoC/SubSystem Entity/Empty-Module
definition
 This is the top module where sub-modules will get
 This top module can be created on-the-fly through Tcl
commands
2. Import Components/Sub-modules
 VHDL Entities
 Verilog/System Verilog Module(s)
 IP-XACT Component
 Source Baya Tcl command file of sub-module
Click here to download Tcl commands used to build Leon
SubSystem
Click here to download the complete list of Baya Tcl
Commands
 Baya-Steps in Tcl Comand mode
3. Instantiate components
4. Specify connections(Add connection command)
 Instance  instance
 SoC/SubSystem  instance
 Constant Value => inst input port
 Constant Value => SoC output port
 Empty connection ( Open Port )
 Can select bit/range of a vector port
 User specified net names
5. Connections specified through CSV files
 Skip step 3 & 4 if CSV is used
Baya-Steps in Tcl Comand mode
6. Elaborate SoC/Sub-System
 Report design maturity( % of unconnected ports )
7. Generate SoC/SubSystem
 Top level VHDL / Verilog files
 Also, creates component modules with empty bodies
o Used to check correctness of the generated RTL
 Simulator/Spyglass compile+elaboration
 Encrypt the output ( AES dual key encryption )
o To make the design/IP secured
 Baya-Steps in Tcl Comand mode
8. Misc
 Document generation
Baya-Steps in Tcl Comand mode
8. Misc( contd. )
 For new release of an instantiated IP/SS, use the
module/entity comparator to check if there is any change
in port/parameters
o Update connectivity commands accordingly
 Generate document for the S/W integration team
 Click here to download Tcl commands used
to build the Leon SubSystem
 Click here to download the complete list of
Baya Tcl Commands
 Click here to watch the online demo of this
tool
 Baya-Steps in GUI mode
1. Double click the DesignPlayer executable
 Click Perspective -> Switch Perspective or Baya on the
Top-Right side
 It will open the GUI
2. Import the empty top module or the top entity
definition
 File->Import Design HDL Files
o This will open a new Wizard – follow self explanatory instructions

3. Import components
 As described above for the top module import
4. Select the top module from the module list in the
left
Baya-Steps in GUI mode
 Baya-Steps in GUI mode
5. Click View -> View Design Schematics
 This will show existing connections if the imported top
has those
6. Create instance(s)
 Through ToolBox
 Click on the Pallete in the Right-Top of the GUI if the Tool Box is not
visible
 Click on the “Instance” in the Right-side and click then mouse in the
Schematic Editor area
 Through Drag-n-Drop
 Select the component/module from the module list in the left
 Drag-n-drop it in the Schematic Editor in the Right ( the main area of the
GUI )
 Select module and Provide the Instance name in the
popped up Wizard
 Baya-Steps in GUI mode
7. Create Connections
 Through Connection Wizard
o Click on the Connection Wizard(Baya) Menu
o This will open up the Connection Wizard
 Through ToolBox
o Click on the “Connection” in the Right-side and then click the mouse in the
Schematic Editor area
o Click the mouse on the source instance and then release the mouse on the
destination instance
o The click the left mouse button
o This will open up the connection wizard

8. Zoom-In/Zoom-Out the design

 Click on the Schematic Editor area
o This will enable the Zoom feature available on the Top-Right
 Select “+” or “-” to make the design visible as required
 Baya-Steps in GUI mode
9. Save & Restore a GUI session
 File -> Save Session
 File-> Open And Existing Session
10.Schematic Viewer
 Select the top module from the component
11.Save RTL
 Make that the top module is opened in the editor
 File -> “Save Database Into Verilog”
12.Baya Shell – Bottom-Right window in the GUI
 The Baya Tcl commands can be executed here
 Execute the ‘refresh’ command to refresh the design
schematic
 Baya-Steps in GUI mode
13.Misc
 Click on VHDL/Verilog/IP-XACT Menu(s) in the GUI
o Run the available generator(s) as per your requirement
 Save / Restore current working session(Needs improvement)
 Switch into the Brigid perspective
o Will be able to browse the design hierarchy like Windows
File Browser
 Double Click on a module or instance see it’s de
 …
Baya- GUIs
 User Feedbacks
“The collection of tools and utilities fills a real void in EDA. The baya
tool is exactly what we had been looking for to assemble large top-
level modules in Verilog. The GUI and high-level TCL commands
are intuitive, allowing designers to get started immediately and feel
right at home. It was straightforward to quickly reproduce a module
previously done with a Perl-to-Verilog utility that was hard to use
and maintain. The support from Kanai is excellent. He responds
quickly and is a pleasure to deal with. Nice work, Kanai!”
- Michael Trocino, IC Design Manager, Coherent Logix

"Baya is a mature production quality tool with features and

capabilities beyond those of tools provided by large EDA vendors.
It's flexibility is a key reason we have chosen it for use in our
Cloud-based platform." - David Fritz, CEO, Social Silicon
 User Feedbacks
"Kanai produced an excellent tool set, which is very useful for a
complex system-on-chip integration flows. We were skeptical in
the beginning, but later got really impressed by a high quality and
ease of use. Bridgit IPXACT creator helps us to pack register, bus
and module interfaces into a IEEE standard *.xml SPIRIT format to
ensure high reusability in the future and protect our investments. I
high recommend using Kanai’s products for every system-on-chip
manufacturer and invest Venture Capital to support further
improvement and commercialization."
- Boris V. Kuznetsov Processorpreneur, CEO @ SOCC