EEET2386 – Switched Mode Power Supplies

Lab Experiment 2 – Design of a Flyback Converter

Prepared By:
s3593736 Syed Ashfaqur Rahman
s3607346 Siyuan Han

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 We initially calculate the load at 100% and then
1. INTRODUCTION calculate the load at 80%.
The main aim of this laboratory experiment is to design 15𝑉 5𝑉
𝑅𝐿,15𝑉 = = 5Ω 𝑅𝐿,5𝑉 = = 50Ω
a flyback converter. Once designed, PSIM simulation 1𝐴 0.1𝐴
15𝑉 5𝑉
will used to confirm the operation of the converter 𝑅𝐿,0.8 = , = 18.75Ω, 62.5Ω
0.8 0.8
meets a required specification. We are also going to The magnetising inductance to just achieve
observe the second order effects such as transformer discontinuous conduction at a 50% duty cycle with an
leakage inductance, semiconductor device losses and 80% load. 𝑅𝑙𝑜𝑎𝑑 is therefore taken to be 18.75 Ω as
semiconductor OFF state capacitance. After that a calculated above.
simple closed loop voltage regulation controller will
implemented for the converter and explore the effect on 𝑉𝑂 1 𝑅𝑙𝑜𝑎𝑑
= 𝐷√
the operation of the conductor under various operating 𝑉𝑖𝑛 2 𝐿𝑚 𝑓𝑆𝑊
conditions and gains.
𝑅𝑙𝑜𝑎𝑑 18.75
𝐿𝑚 = 𝑉𝑂 2 = 15 = 81.67𝑚𝐻
( ) +2𝑓𝑆𝑊 ( )2 +(2×100𝑘𝐻𝑧)
Task 1.1 Establish the Simulation Circuit 𝐷𝑉𝑖𝑛 0.5×28

Task 1.3 Simulation Check

Figure 1 Idealised Dual Output Flyback Converter Figure 2. Required Output voltages of 5V and 15V
Circuit
To observe the simulation, the circuit in figure 1 has Simulations above shows that the we were successful in
been made in PSIM. It consists of a three-winding obtaining the voltage results as required at both of the
transformer, two half-wave rectifiers connected outputs and with the voltage ripples of less than 50mV.
separately to the output windings to produce the
required DC voltages. It also consists of a single switch
SW1 which is driven by square wave generator D along
with a closed loop voltage feedback controller, multiple
capacitors such as Cfet, Cd1, Cd2 and a snubber Rs with
capacitor Cs across the main FET switch. A Zener diode
is added as well across the switch to clamp the residual
energy of the primary winding leakage inductance.
Figure 3. Current across the Rload and Rmin
2. RESULTS AND DISCUSSION Figure 2. Output Currents
Task 1.2 Theoretical Calculation
The following parameters of the converter are given to
us:
Parameters Value
Input Voltage Range 20V-32V (28V nominal)
Output Voltages 15V, 1A and 5V,100mA
Switching Frequency 100kHz
Duty 50%
Turns Ratio (Pri-Sec-Ter) 28:15:5
Figure 4. Voltage across the FET

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During the ON period, the voltage across the FET will
be zero. In OFF period, the voltage across it can be
found by:
𝑁 28×15
𝑉𝑆𝑊 = 𝑉𝑑𝑐 + 𝑁𝑃 𝑉𝑂 = 28 + 15
= 56𝑉
𝑆

This is accurate to our simulation result as shown in

figure 4.

Task 1.4 Idealised Converter Performance

In this task, we observed the ideal converter operation Figure 8. Output Current at 10% Loads
under number of different load conditions.

Case 1: Full Load resistances for both windings

Figure 9. Voltage across FET at 10% loads

The FET voltage is showing three levels in figure 9

Figure 5. Output voltages of 5V and 15V at full load
Once the simulation is ran, we could see there is not
much of a difference from figure 2 in previous case.
However, the current across the load increases as shown
in figure 6. By changing to full load, the converter is
made to be operate more in continuous conduction
mode.
where the voltage is zero during the ON period, voltage
is at maximum at OFF period. There is another state
where the voltage is approximately 29V before going to
zero. This is where the magnetising inductor current is
zero and that is being showed here.
As the load is decreased to 10%, the ripple current has
made its way to the discontinuous region. Hence, we
had to recalculate the duty cycle:

𝑉 2𝐿𝑚 𝑓𝑆𝑊 15 2×81.67×10−6 ×100×103

𝐷 = 𝑉𝑂 √ 𝑅𝑙𝑜𝑎𝑑
= 28 √ 150
=0.177
𝑖𝑛

The voltage obtained in the simulation is less than the

expected output voltage as shown in figure 7.

Case 3: 100% Rload and 10% Rmin

𝑉 2𝐿𝑚 𝑓𝑆𝑊 15 2×81.67×10−6 ×100×103
𝐷 = 𝑉𝑂 √ 𝑅𝑙𝑜𝑎𝑑
= 28 √ 15
=0.56
𝑖𝑛

Figure 6. Output Current at full load The duty cycle calculated above is greater than 0.5.
Hence, the converter is operating in continuous
Case 2: 10% light load resistances conduction mode.

Figure 10. Output Voltages at 100% Rload and 10%

Figure 7. Output Voltages at 10% load Rmin
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Figure 11. FET voltage drop at 100% Rload and 10%
Rmin
On the other hand, the voltages are maintained at 15V
and 5V as shown in figure 9.
We can also observe that the FET voltage drop has two
state levels (during the ON period, voltage is zero and
the OFF period where the voltage goes to maximum).
Figure 12. Output Currents at 100% Rload and 10%
Rmin
Case 4: 10% Rload and 100% Rmin
From figure 13, the FET voltage is again showing three
state, proving that the converter is operating at
discontinuous conduction mode.
Figure 13. FET voltage at 10% Rload and 100%Rmin
Figure 14. Output voltages at 10% Rload and 100%
Rmin
As the input voltage is increased, the output voltages
also increase. But for every voltage rise, if we do not
recalculate the duty cycle then the converter is still
operating in discontinuous mode.
Task 2.1 Converter Performances with
Second Order Effects
Case 1: FWD Diode Voltage and FET ON Resistance
From this section onwards, the FET ON resistance is
and a 1V diode forward voltage drop is introduced. It is
observed that the output voltage decreased by 1V as
shown in figure 15. The voltage drop across FET has is
similar to the one obtained in previous section. The
simulation for this is shown in figure 15. The current
across the loads were kept the same as the previous case.
By increasing the number of turns of the secondary and
the tertiary by 1 turn, we were able to fix this.
Figure 15. Decreased Output Voltages
Figure 16. FET voltage
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Figure 17. Output Currents across Rload and Rmin
Case 2 Transformer Leakage Inductance
The converter is not ideal since we have leakage
inductances. When the switch is open, it is not fully an
open circuit without anything in between the two
terminals. In a switch, there is a drain and a sink
terminal. They can be thought of as the plates of a
capacitor. When the switch is open, there is a capacitor
present in there.
When we have command to turn the switch ON, the
voltage across it is zero. The input voltage is applied the
magnetising inductance and the current ramps up. When
we remove the command from the switch, the voltage
across the magnetising inductor is the -ve output voltage
reflected to the primary. Hence, voltage across the
switch will be the input voltage plus the output voltage
reflected to the primary
Figure 18. Voltage across the FET with increasing the
leakage inductance.
Case 3 Transformer Leakage Inductance + FET
Capacitance
If we now bring the capacitance Cfet that the switch has
when it’s open, then there is a huge change. There are
now oscillations happening across the switch and the
magnetising inductor.
Figure 19. FET voltage with the inclusion of
Transformer Leakage Inductance + FET Capacitance
This oscillation will not damage the circuit because the
voltage is within the range the switch can operate.
However, at high frequency, voltage finds it easier to
couple to other circuits that are close to the power
supply. The oscillations can cause the power electronic
circuits near power supply to misbehave. The reason we
have oscillations is due to resonance. A resonance
between the capacitance Cfet (intrinsic to the switch)
and the magnetising inductance at high frequency.
Case 4 Snubber Circuit
To remove the oscillations observed in case 3, we added
a capacitor Csn parallel to the switch. A resistor is then
added in series to the Csn. We make the capacitor large
enough so that it has more dominance in the resonance.
The resonance is then dumped across the resistor and
removed. This R and Csn is the snubber and the solution
to dampening resonance.
Figure 20. FET voltage after adding the snubber circuit
All the ringing that appeared in figure 19 is gone. This
is shown in the simulation in figure 20 (just a little bit
present). This proves that the snubber designed is
working correctly. What triggers the resonance is the
step in voltage, when the magnetising current reaches
zero and the voltage across the switch changes from
input plus the output reflected on the primary to simply
the input voltage. So there is a voltage step and when
this voltage step is applied to LC circuit, a resonance is
triggered.
If we operate in continuous conduction mode by making
Rload smaller, we don’t have that voltage step anymore
since current doesn’t reach zero prior to the end of
switching period. As a result, no resonance occurs, and
no snubber is needed.
CONCLUSIONS
In this lab, we have looked into flyback converters and
its operation in details. The flyback converter is an
isolated power converter. Whose schematic is
equivalent to a buck-boost converter with the inductor
split to form a transformer. We observed the effect on
output voltages as we varied resistances, Rload and
Rmin. We also observed the effect of leakage
inductances and the FET capacitance and how
resonance in the circuit is removed using the snubber
circuit, Rs and Csn.
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