數位邏輯
Chapter 5
Synchronous Sequential Logic
吳俊興
國立高雄大學 資訊工程學系
December 2005
Chapter 5 Synchronous Sequential
Logic
5-1 Sequential Circuits
5-2 Latches
5-3 Flip-Flops
5-4 Analysis of Clocked Sequential Circuits
5-5 HDL for Sequential Circuits
5-6 State Reduction and Assignment
5-7 Design Procedure
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5-1 Sequential Circuits
Combinational circuits
z The outputs are entirely dependent on the current inputs
z Contains no storage elements, no feedback
Sequential circuits
z Consists of a combinational circuit to which storage elements
are connected to form a feedback path
z Outputs are a function of both the current inputs and the
present state of the storage elements
Storage/memory elements
z capable of storing binary information
z defining the state of the sequential circuit
z Next state is a function of external inputs and current state
(inputs, current state) ⇒ (outputs, next state)
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Types of Sequential Circuits
Two major types: depending on timing of their signals
Asynchronous sequential circuits (see Chapter 9)
z The transition happens at any instant of time
z Do not use clock pulses. Change of internal state occurs
pulse
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Synchronous Clocked Sequential Circuits
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The outputs can come either from the combinational circuit or
from the flip-flops or both
The flip-flops receive their inputs from the combinational
circuit and also from a clock signal with pulse that occurs at
fixed intervals of time
z The flip-flop outputs cannot change and the feedback loop is broken
when a clock pulse is not active 6
5-2 Latches
Latches: basic circuits to construct flip-flops
z capable of storing binary information, impractical for use in
synchronous sequential circuits
more complicated types can be built upon it
SR Latch
z Two states: Set and Reset states
z an asynchronous sequential circuit with two cross-coupled
NOR gates
S’-R’ Latch
z SR latch with two cross-coupled NAND gates
0 signal to change its state
SR latch with control input
z Determines when the state of the latch can be changed
D Latch
z eliminate undesirable condition of indeterminate state in
SR latch 7
SR Latch
Two inputs labeled S for set and R for reset
(S,R)=(1,0): set (Q=1, the set state)
(S,R)=(0,1): reset (Q=0, the reset/clear state)
(S,R)=(0,0): normal condition
z no operation, in either the set or the reset state
z depending on which input was most recently at 1
(S,R)=(1,1): indeterminate state (Q=Q'=0)
z consider (S,R) = (1,1) ⇒ (0,0)
unpredictable next state when both inputs return to 0
(depend on which input returns to 0 first)
Q = [R+(S+Q)’]’ = R’(S+Q)
Q’ = [S+(R+Q’)’]’ = S’(R+Q’)
(S+Q)’
(R+Q’)’
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S’-R’ Latch – SR Latch with NAND Gates
0 signal to change its state
(S,R)=(0,1): set (Q=1, the set state)
(S,R)=(1,0): reset (Q=0, the reset/clear state)
(S,R)=(1,1): normal condition
(S,R)=(0,0): indeterminate state (Q=Q’=1)
unpredictable next state
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SR Latch with Control Input
An additional input as an enable signal
C=0 ⇒ quiescent condition, no change
C=1 ⇒ S or R is allowed to affect the SR latch
(1 signal to change its state)
S_ 1/S'
0/1
R_ 1/R'
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D Latch
S=D and R=D’
z Ensure S and R are never equal to 1 at the same time
z Eliminate the undesirable conditions of the indeterminate
S_ 1/D'
0/1
R_ 1/D
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Graphic Symbols for Latches
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5-3 Flip-Flops
A trigger: the momentary change to switch the state
of a latch or flip-flop
z The transition it causes is said to trigger the flip-flop
Types of triggers
z Level triggered – latches
D latch is triggered every time the pulse stays at logic 1 level.
Be used as a temporary storage between a unit and its environment
z Edge triggered – flip-flops
If level-triggered flip-flops are used, the feedback path may cause
instability problem as long as the clock pulse stays in the active level
triggered only during a signal transition (0⇒1 or 1⇒0)
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Edge-triggered
D flip-flop
Store binary info during transition
Method 1: Master-slave D flip-flop
z two separate flip-flops
a master flip-flop (positive-level triggered)
a slave flip-flop (negative-level triggered)
z change only during negative edge of clock
longer propagation delay
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Edge-triggered D flip-flop (cont.)
Method 2: D-type positive-edge-triggered flip-flop
z The most efficient flip-flop constructed with 3 SR latches
CLK=0 ⇒ S=R=1, no change
CLK=positive transition ↑⇒ Q=D (state changes once)
D=0 when CLK becomes 1 ⇒ R=1 to 0 ⇒ D changes further, no effect
D=1 when CLK becomes 1 ⇒ R=stay 1 ⇒ D changes further, no effect
CLK=negative transition or 1 ⇒ quiescent condition (state holds)
(RD)’
[S(RD)’]’=S’+RD
S
S=CLK’+S(RD)’
[S(RD)’]’ Q=R ⇒ Q=D
S
(RD)’
R=CLK’+S’+RD
R
(RD)’
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(RD)’ D=0 D=1
[S(RD)’]’=S’+RD S=CLK’+S S=CLK’+SR’
S
R=CLK’+S’ R=CLK’+(SR’)’
S=CLK’+S(RD)’
[S(RD)’]’ CLK=0 CLK=1
S=R=1 S=S
D=0
S Q=Q R=S’
S=R=1 S=SR’
(RD)’ D=1
R=CLK’+S’+RD Q=Q R=(SR’)’=S’
=CLK’+[S(RD)’]’
R
(RD)’
Q --________--------________-----
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Setup Time and Hold Time
Setup time
a minimum time for which the D input must be
maintained at a constant value (or be ready)
prior to the occurrence of the clock transition
data to the internal latch
Hold time
a minimum time for which the D input must not
changes after the application of the positive
transition of the clock
clock to the internal latch
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Graphic Symbols
> dynamic
indicator
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JK Flip-Flop
Edge-triggered D flip-flop
z Store binary information during edge trigger
z Require the smallest number of gates
z Other types of flip-flops can be constructed using it
JK Flip-Flop: D=JQ'+K'Q
J=0, K=0: D=Q ⇒ Q no change
J=0, K=1: D=0 ⇒ Q =0 reset to 0
J=1, K=0: D=1 ⇒ Q =1 set to 1
J=1, K=1: D=Q’ ⇒ Q =Q’ complement output
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T Flip-Flop
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Characteristic Tables and Equations
Characteristic Tables
Characteristic equations
D flip-flop Q(t+1) = D
JK flip-flop Q(t+1) = JQ’+K’Q
T flop-flop Q(t+1) = T⊕Q = TQ’ + T’Q 21
Direct Inputs
preset/direct set: the inputs that sets the flip-flop to 1
clear/direct reset: the inputs that clears the flip-flop to 0
z to a known starting state
asynchronous reset
reset=0 ⇒ force Q=0, resetting
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5-4 Analysis of Clocked Sequential Circuits
State equation (transition equation)
A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) = A’(t)x(t)
y(t)=[A(t)+B(t)]x’(t)
or
A(t+1)=Ax+Bx
B(t+1)=A’x
y=(A+B)x’
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State Table or Transition Table
state table ⇐ state equation ⇐ CSC diagram
Four sections: present state, input, next state and output
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Second Form of State Table
input/output
x/y
state diagram
A(t+1)=Ax+Bx ⇔ state table
B(t+1)=A’x ⇔ state equation
y=(A+B)x’ ⇔ logic diagram 26
Input/Output Equations
logic diagram of a sequential circuit consists of flip-flops + gates
z output equations: the circuit that generates external outputs
z input equations: the circuit that generates inputs to flip-flops
output equations
input
equations state
characteristic
(or excitation equations) equations equations
Symbol convention: DQ = x + y x
y
an OR gate with inputs x and y
connected to the D input of a
flip-flop whose output is
labeled with the symbol Q
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Flip-Flop Input Equations
FF Input
State Equations Equations
A(t+1)=Ax+Bx DA=Ax+Bx
B(t+1)=A’x ⇒ DB=A’x
Output Equation
y=(A+B)x’ y=(A+B)x’
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Analysis with D Flip-Flops
Given: Find:
input function: DA=A⊕x⊕y ⇔ logic diagram
state equation: A(t+1)=A⊕x⊕y ⇔ state table
one flip-flop and 2 inputs ⇔ state diagram
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Given logic circuit, Analysis with
find the others
JK Flip-Flops
(1) Flip-flop input equations
(3)
(4)
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Analysis with T Flip-Flops
Characteristic equation: Q(t+1)=T⊕Q=T’Q+TQ’
Input equations and output equation:
TA=Bx; TB=x; y=AB
State equations
A(t+1)=(Bx)’A+(Bx)A’=AB’+Ax’+A’Bx
B(t+1)=x⊕B
Given logic
circuit, find
the others
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Mealy and Moore Models
Mealy model
The output is a function of both the present state and input
— The outputs may change if the inputs change during the clock cycle
— The outputs may have momentary false values due to delay
— To synchronize, the outputs must be sampled only during the clock edge
Mealy finite state machine (FSM, machine): the Mealy model of
a sequential circuit
example: Fig. 5-15 (D)
Moore model
The output is a function of the present state only
— The outputs are synchronized with the clock
Moore finite state machine (FSM, machine): the Moore model
of a sequential circuit
example: Figure 5-19 (JK), 5-20 (T)
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5-6 State Reduction and Assignment
Sequential circuit analysis:
z starts from a circuit diagram and
z culminates in a state table or state diagram
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State Reduction
Example: Figure 5-22 (7 states)
z Given a state table or state diagram
z Find ways of reducing the number of states
Test sequence
•Initial state: a
•Input sequence: 01010110100
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State Equivalence
State equivalence: Two states are equivalent if, for
each member of the set of inputs, they
give exactly the same output and
send the circuit either to the same state or to an equivalent state
Algorithm:
1.Look for two present states that
go to the same next state and
have the same output for both input combinations
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State Assignment
State assignment: assign coded binary values to the state
z In order to design a sequential circuit with physical components
z A circuit with m states need n bits where 2n >= m
Transition table: a state table with a binary assignment
z To distinguish it from a stable table with symbolic names for states
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5-7 Design Procedure
Design of a clocked sequential circuit
z starts from a set of specifications
z obtains a state table/diagram (or equivalences) first
z culminates in a logic diagram (or a list of Boolean functions)
Tasks
z Choosing the flip-flops
Determined from the number of states needed
z Finding a combinational gate structure
Derived from the state table by evaluating the flip-flop input
equations and output equations
Summarized procedure
most challenging
Synthesis
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Example: Sequence Detector
Specification: Design a circuit that detects three or more
consecutive 1’s in a string of bits combining through an input line
0
1
2
3
4
5
6
7
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Synthesis Using D Flip-Flops (cont.)
Step 7 – Draw the logic diagram (using simplified functions)
Excitation table: a
table that lists
required inputs
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Analysis and Design
output
equations ?
present input
states equations state
equations ?
characteristic
equations
(1) Input/output equations (2) state equations (3) State table (4) State diagram
? output
equations
present input
states equations next states
Excitation
Table
(1) State diagram/table (2) Input/output equations (3) Circuit diagram 42
Excitation Tables
The input equations for the circuit using flip-flops other
than the D type, i.e. JK and T types, must be derived
indirectly from the state table
Excitation table: list the required inputs for a given
change of state
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Synthesis Using JK Flip-Flops
The input equations must be evaluated
from the present-state to next-state
transition derived from the excitation table
(1)
(2)
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Logic Diagram for Sequential Circuit with JK Flip-Flops
(3)
(2)
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Logic Diagram of 3-Bit Binary Counter
(3)
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Summary
Chapter 5 Synchronous Sequential Logic
5-1 Sequential Circuits
5-2 Latches
— SR latch, S’R’ latch, D latch
5-3 Flip-Flops
— edge-triggered D, JK, T flip-flops
5-4 Analysis of Clocked Sequential Circuits
5-5 HDL for Sequential Circuits
5-6 State Reduction and Assignment
5-7 Design Procedure
circuit diagram⇔input equation⇔state equation⇔state table⇔state diagram
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