Anda di halaman 1dari 5


9, SEPTEMBER 2003 627

Transactions Briefs__________________________________________________________________
Chopper-Stabilized High-Pass Sigma Delta Modulator
Utilizing a Resonator Structure
Koichi Ishida and Minoru Fujishima

Abstract—A chopper-stabilized high-pass sigma delta modulator (SDM)

utilizing a resonator structure for the reduction of low-frequency noise,
such as dc offset, thermal drift, and 1 noise, is presented. The high-pass
SDM has a zero of a noise transfer function at half of the sampling fre- (a)
quency and is stabilized by chopper modulation. Since the first integrator
of the proposed modulator has a large closed-loop gain, no pre-amplifier is
required even when the input signal is small, which is suitable for low-power
applications. The signal-to-noise ratios (SNRs) and power dissipations of a
high-pass modulator and a conventional modulator have been numerically
Index Terms—1 noise, chopper stabilization, dc offset, high-pass
sigma delta modulator (SDM), thermal drift.

Sigma delta modulators (SDMs) are well suited for high-resolution Fig. 1. (a) The Block diagram of the second-order SDM utilizing a resonator
medium-to-low-frequency applications such as instrumentation structure. (b) The location of zeros of the NTF in the z -plane. Three cases of
systems and audio equipments. A preamplifier is usually required to SDMs are shown.
increase the SDM input to the maximum swing independently of the
noise performance of the SDM. For small low-frequency signals, in
particular, the SDM requires a low noise preamplifier since the first
integrator of the original low-pass SDM cannot distinguish between
its input and the noise generated by the integrator itself. On the other
hand, a chopper-stabilized amplifier was presented in order to achieve
a reduction of low-frequency noise such as dc offset, thermal drift, and
1=f noise [1]. This scheme consists of a pair of choppers, an amplifier,
and a high-Q bandpass filter that eliminates high-order tones. For
dc-to-low-frequency signal conversion, although a chopper-stabilized
amplifier can be directly applied to the preamplifier for the SDM,
the additional amplifier increases the power considerably. Although
several methods for merging SDM into the chopper-stabilized scheme
have been presented in order to suppress the increase of power [2]–[4], Fig. 2. Principle and schematic block diagram of the chopper-stabilized
these methods require a special integrator containing extra switches, high-pass SDM.
which make it difficult for the circuit to operate at a low supply
An SDM having a zero of a noise transfer function (NTF) at half of the NTF at fs =2 and to merge the SDM into the chopper-stabilized
the sampling frequency (fs =2) was presented by Chang et al. [5]. The scheme.
SDM reported in [5] requires local feedback at each integrator. On the The proposed SDM, namely, the high-pass SDM, is a resonator-
other hand, a resonator-structured bandpass SDM, which requires local structured bandpass SDM, as shown in Fig. 1(a). The transfer func-
feedback per pair of integrators, was developed for modulated signal tion of this second-order SDM is derived as
conversion such as that in digital radios [6]. The resonator-structured
a0 a1 x + (z 2 + (a1 r 2)z + 1)e
0 0 0
bandpass SDM has the advantages that the circuit is simpler and the = (1)
z + (a1 r b1 2)z + (b1 a1 b0 + 1)
total effective capacitive load is lower than that in [5]. Therefore, we
improved the resonator-structured bandpass SDM to obtain a zero of
where is e quantization noise.
For a1 r = 4, b1 = 2, and a1 b0 = 3, the NTF is derived as
Manuscript received March 26, 2002; revised April 15, 2003. This paper was
y = (1 + z
01 )2 e: (2)
recommended by Associate Editor A. Petraglia.
K. Ishida is with the Department of Electronic Engineering, School of Engi-
neering, The University of Tokyo, Meguro-Ku, Tokyo 153-8505, Japan (e-mail: Since the NTF has a zero at 01 as a repeated root in the z -plane, that is, the NTF has a zero at fs =2, the SDM has a second-order-shaped noise.
M. Fujishima is with the Department of Frontier Informatics, School of Fron-
tier Sciences, The University of Tokyo, Bunkyo-Ku, Tokyo 113-8656, Japan
The location of zeros of the NTF in the z -plane is shown in Fig. 1(b).
(e-mail: Fig. 2 shows the block diagram of the chopper-stabilized high-pass
Digital Object Identifier 10.1109/TCSII.2003.816932 SDM that operates at fs =2. The operation principle is as follows.

1057-7130/03$17.00 © 2003 IEEE




Fig. 3. Measured output spectra of the chopper-stabilized high-pass SDM

and a conventional low-pass SDM without chopping. The chopper-stabilized
high-pass SDM suppresses low-frequency noise well.

First, the input signal is chopped by the frequency (fc ) set at half of the
sampling frequency (fs ). Namely, the input signal is up-converted to
around fs =2. Second, the up-converted signal is directly modulated by
the high-pass SDM, where the low-frequency noise generated by the
first integrator in the SDM is separated from the up-converted signal
and is masked by the quantization noise centered at DC. Finally, the Fig. 4. Block diagram of the second-order SDM reported in [5].
signal is down-converted into the original signal band by the digital
chopper circuit. Simultaneously, the low-frequency noise generated by TABLE III
the SDM is up-converted to fs =2 and is easily eliminated by the digital
It is noted that although the bandpass SDM with the chopper-stabi-
lized scheme may also reduce low-frequency noise, the second-order
structure SDM achieves only the first-order-shaped noise. The second-
order high-pass SDM with the chopper-stabilized scheme, on the other input-referred thermal noise power of the proposed high-pass SDM
hand, achieves second-order-shaped noise. Measured output spectra shown in Fig. 1(a), PN 1 , is derived as
of a second-order high-pass modulator and a second-order low-pass 2 2
r b0
modulator using a field programmable analog array (FPAA) are shown PN 1 = vnr
2 + v2 +
na0 vnb
a0 a0
in Fig. 3. The second-order high-pass SDM inherently suppresses the 2
low-frequency noise observed in the output spectrum of the low-pass 1
+ 2 (1
0 z01)vna
2 +
(a0 a1 )2
01 2 :
(1 0 z )vnb1 (4)
SDM and yields second-order shaped quantization noise.
The input signal power PS1 is derived as
The signal-to-noise ratios (SNRs) and the power dissipations of where A is an amplitude of the input signal. By substituting the
the proposed high-pass SDM and the SDM reported in [5] have been z = 01,that is, fs =2 for the worst-case analysis and topology
numerically analyzed in the same manner as those of an analog-to- parameters shown in Table II into (3) to (5), the SNR of the proposed
digital converter for a low-frequency small-signal application such SDM, SN 1 , is derived as
SN1 = S1
as an electrocardiograph. The calculation conditions for SNRs and
power dissipations of SDMs that will be implemented in 0.35-m PN 1
CMOS technology are shown in Table I. The thermal noise power
A2 r2 2 2 2 01
v v 2 + b0 v 2 + 2 v 2 + 8b0 v 2
within the baseband of the SDM having two clock phases is inversely =
2 a20 nr + na 0
a20 nb0 a20 na1
9a02 nb1
proportional to the input capacitance of integrators as expressed in 01
(3) [7]. A 1 OSR 1 Ca0
(r + b0 )Cf 0 1 4b0
2 2
2Cf 0
= 1+ + +
4kT Ca0 a1 9b1 Ca0 Cf 1
vn2 =
A 1 OSR 1 Ca0
Cf 0 Cf20 01
OSR 1 CS (3) =
Ca0 Cf 1

where OSR is oversampling ratio, k is the Boltzmann constant, where Ca0 is sampling capacitor, Cf 0 is feedback capacitor of first
T is absolute temperature, and CS is sampling capacitor. The integrator, and Cf 1 is feedback capacitor of second integrator.


Fig. 5. Calculated SNR for: (a) high-pass SDM and (b) SDM reported in [5].
Fig. 6. Calculated power dissipation for: (a) high-pass SDM and (b) SDM
reported in [5].
Although (6) can also be expressed with functions other than feed-
back capacitors, it is expressed with the function of the feedback ca-
pacitors Cf 0 and Cf 1 and the input sampling capacitor Ca0 because under the same condition because the slew is inversely proportional
all of the gains of the integrators are greater than one and Cf 0 and Cf 1 to Ce 1 , in the same way as the GBW. The GBW is designed to be
determine the minimum of the capacitance used in the circuit. It is noted three times higher than the sampling frequency and the bias current of
that Ca0 is fixed to 12 pF, as shown in Table I, in consideration of the the input-stage MOSFET is one-tenth of its transconductance for OTAs
maximum value determined by the operation speed which depends on that can complete charging Ce 1 during half the sampling cycle.
the output impedance of a sensor and the minimum value determined On the SDM reported in [5], the circuit block diagram of which is
by the required number of bits. The power dissipation of the proposed shown in Fig. 4, and for each topology parameter chosen as shown in
SDM is estimated from the total effective capacitive load of integrators Table III, the SNR depending on thermal noise generated by capacitors
Ce 1 which is derived as expressed in (7) [8] is derived similarly to (6) as

Ca1 (Cr + Ca0 + Cb0) A2 1 OSR 1 Ca0 Cf 0 Cf20 01

Ce 1 = Cr + Ca0 + Cb0 + Ca1 + SN2 = 1+3 + 10 : (8)
Cf 0 4kT Ca0 Ca0 Cf 1
Cr (Ca1 + Cb1 ) The total effective capacitive load is derived similarly to (7) as
+ Ca1 + Cb1 + Cr +
Cf 1 Cf 1
= fr (2+ a1 + b1 )+ b0 g Cf 0 + fa1 (2+ r + b0 )+ b1 g Cf 1 Ce = 11Cf 0 + 21Cf 1 + C :
Cf 0 a0
3+ (9)
Cf 1
+ 1 + a1 C
Cf 0 a0 The SNRs and power dissipations are calculated using (6)–(9).
Fig. 5(a) shows the SNR of the high-pass SDM, and Fig. 5(b) shows
Cf 1
=11:6Cf 0 + 14Cf 1 + 1 + 2:5 C : the SNR of the SDM reported in [5]. The proposed high-pass SDM
Cf 0 a0
realizes a higher SNR in a wide area than the SDM reported in [5]
The power dissipation is also proportional to the sampling frequency, although both SDMs achieve the peak SNR of 49.6 dB.
which specifies the gain bandwidth (GBW) and slew rate of operational Fig. 6(a) shows the power dissipation of the high-pass SDM, and
transconductance amplifiers (OTAs) charging Ce 1 . In this study, al- Fig. 6(b) shows the power dissipation of the SDM reported in [5]. The
though the power dissipation is analyzed using only the GBW for sim- high-pass SDM consumes lower power (e.g., for Cf 0 = 500 fF and
plification, the result still has generality with respect to the comparison Cf 1 = 50 fF, 26.3 W at 47.3 dB) than the SDM reported in [5] (e.g.,
between two SDMs, that proposed and that reported in [5], operating for Cf 0 = 300 fF and Cf 1 = 100 fF, 55.5 W at 47.1 dB).

Fig. 8. Monte Carlo simulations to compare the sensitivity of the systems to
capacitor mismatch at  = 0 05%
: .

A chopper-stabilized high-pass SDM has been proposed for the re-
duction of low-frequency noise. The scheme has the following advan-
tages: an analog switch that alternately changes the sampling capacitor
polarity for the first-stage integrator functions as an analog chopper and
a simple exclusive-or gate acts as a digital chopper. Since the number
of switches on the signal path in the analog circuit does not increase,
the additional switches add no extra noise. Furthermore, no extra cir-
cuit is required in the integrators for the high-pass SDM. Consequently,
the same techniques as that for the low-voltage operation in the con-
ventional SDM are applicable. Since the up-converted signal is directly
modulated by the high-pass SDM, neither the low-noise preamplifier
(b) nor the high-Q bandpass filter that causes large power dissipation is
required, even in the case that the input signal is small.
Fig. 7. Calculated figure of merit for: (a) high-pass SDM and (b) SDM
reported in [5].
We have clarified the advantages of the resonator-structured
high-pass SDM from the viewpoint of SNR, power dissipation and
figure of merit, compared with the conventional SDM reported in
TABLE IV [5]. It is considered that the chopper-stabilized high-pass SDM is
well suited for use in the micro power analog-to-digital converter for
low-frequency small-signal applications.

The authors thank Prof. W. Sansen for fruitful discussion and Omron
Fig. 7(a) and (b) show the figure of merit FM defined as Corporation for their technical support on the FPAA.

4kT 1 DR 1 BW
FM = (10)
where DR is dynamic range, BW is bandwidth, and P is power dissi- [1] C. C. Enz, E. A. Vittoz, and F. Krummenacher, “A CMOS chopper am-
pation [7], except that SNRs are applied to dynamic ranges to compare plifier,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 335–341, June
the trade-offs between SNRs and power dissipations. The proposed [2] J. E. Johnston, “A 24-Bit delta-sigma ADC with an ultra-low noise
high-pass SDM obtains a higher figure of merit than the SDM reported chopper-stabilized programmable gain instrumentation amplifier,” in
in [5] under the optimum operating condition. Proc. 3rd Int. Conf. on Advanced A/D and D/A Conversion Techniques
and Their Applications, July 27–28, 1999, pp. 179–182.
Monte Carlo simulations to compare the sensitivity of the systems
to capacitor mismatch are performed under the conditions listed in [3] W. Lee, “A 4-channel, 18 b 16 modulator IC with chopped-offset sta-
bilization,” 42nd ISSCC Dig. Tech. Papers, vol. 453, pp. 238–239, 1996.
Table IV. The simulated result is shown in Fig. 8. Since the proposed [4] C. B. Wang, “A 20 bit 25 kHz delta sigma A/D converter utilizing a fre-
SDM has a resonator structure, its zero of the NTF is as sensitive to ca- quency-shaped chopper stabilization scheme,” IEEE J. Solid-State Cir-
pacitor mismatch as the bandpass SDMs zeros are. However, the feasi- cuits, vol. 36, pp. 566–569, Mar. 2001.
bility of the proposed SDM is verified by the experimental result using [5] Y.-H. Chang, C.-Y. Wu, and T.-C. Yu, “Chopper-stabilized sigma-delta
modulator,” in Proc. ISCAS, vol. 2, May 1993, pp. 1286–1289.
the FPAA, as shown in Fig. 3, and the SNR of the proposed SDM is [6] S. A. Jantzi, R. Schreier, and M. Snelgrove, “Bandpass sigma-delta
higher than that of the SDM reported in [5] when the standard devia- analog-to-digital conversion,” IEEE Trans. Circuits Syst., vol. 38, pp.
tion ( ) of the unit capacitor is controlled to within 0.05%. 1406–1409, Nov. 1991.

[7] S. Rabii and B. Wooley, “A 1.8-V digital-audio sigma-delta modulator gain of this amplifier causes nonlinearity of the overall A/D conversion
in 0.8- m CMOS,” IEEE J. Solid-State Circuits, vol. 32, pp. 783–796, which cannot be corrected by the digital error correction.
June 1997. For illustration purposes, without loss of generality, we will assume
[8] V. Peluso, P. Vancorenland, A. Marques, M. Steyaert, and W. Sansen,
“A 900-mV low-power 16 A/D converter with 77-dB dynamic range,” in our discussions a 1.5-bit/stage pipeline [1]. A typical implementation
IEEE J. Solid-State Circuits, vol. 33, pp. 1887–1897, Dec. 1998. of such a pipeline stage is shown in Fig. 2. Denoting the open-loop dc
gain of the operational amplifier (opamp) as A, the output of the ith
stage is given by

o (i 0 1)
(C 1 + C 2)=C 2
vo (i) = 1 + (C 1 + C 2)=[(C 2)A]

Background Calibration of Operational Amplifier 01 + ( C1

(C 1=C 2)
+ C 2)=[(C 2)A]
DV R (1)
Gain Error in Pipelined A/D Converters
Ahmed M. Abdelatty Ali and K. Nagaraj
where VR is the reference voltage and D could be 1, 01, or 0, de-
pending on the sub-A/D-converter decision.
If C 1 = C 2 and A is infinite, we have

o (i) = 2vo (i 0 1) 0
Abstract—New techniques for the calibration of interstage amplifier
gain errors due to the finite gain of the operational amplifiers in pipelined v DV R: (2)
analog-to-digital (A/D) converters are described. The techniques work by
deriving an error signal from the summing node voltage of an operational In practice, the actual value of the residue deviates from this ideal value
amplifier to be calibrated and adding the processed error signal to the due to capacitor mismatch and the finite opamp gain. This error causes a
original signal in the analog or digital domain. The calibration is done nonlinearity in the overall A/D converter, and therefore needs to be cal-
entirely in the background, without interrupting the operation of the
ibrated. The same argument applies to pipelined A/D converters with
converter. Behavioral and transistor-level simulation results demonstrate
the effectiveness of the proposed techniques in correcting the gain error an arbitrary number of bits per stage, where interstage amplifiers with
and improving the accuracy and linearity of pipelined amplifiers and A/D larger values of mi can be implemented by using larger ratios of C 1
converters. and C 2, or as a cascade (pipeline) of mi stages each having a gain of
Index Terms—Analog-to-digital (A/D) converters, background calibra- 2 [2].
tion, pipelined A/D converters, self-calibration. Several previous calibration techniques are described in the literature
[3]–[6]. These techniques generally lead to complex implementations,
especially if it is needed to perform the calibration in the background. In
I. INTRODUCTION most of these, the emphasis is on capacitor mismatch error. However,
A pipelined analog-to-digital (A/D) converter is an attractive choice with the current trend toward even higher speeds, opamp finite gain
for high-speed high-resolution telecommunication applications such as and nonlinearity are increasingly becoming the major limiting factor
cable modems and digital subscriber lines. By breaking down the total even at medium resolutions where capacitor mismatch is not a problem.
number of desired bits into a cascade (pipeline) of low-resolution A/D This emphasizes the need for more economical techniques specifically
converters, it is possible to implement high-resolution A/D converters oriented to the correction of the opamp gain error. In the following
at high sampling speeds that would otherwise be difficult, if not impos- sections, several new techniques for the correction of the opamp gain
sible, to implement. error in pipelined A/D converter stages are described.
A block schematic of a typical n-stage pipelined A/D converter is
shown in Fig. 1. In stage i, the input is digitized using an mi -bit A/D II. PROPOSED TECHNIQUES
converter. The digital code is then converted back to an analog signal,
Setting C 1 = C 2 in (2), the error due to just the finite opamp gain
and the difference (residue) between the stage’s analog input and the
in a 1.5-bit pipeline stage can be represented as follows:
quantized signal is obtained. This residue is amplified by the interstage
amplifier and then passed to the next stage. The gain Gi of the ith-stage
o (i) = 1 + 2=A [vo (i 0 1) 0 DVR =2]
amplifier should be equal to 2m if there is no redundancy. In most im-

plementations, redundancy is utilized to allow for digital error correc-

tion of the A/D subconverter errors in each stage. Thus, the gain Gi of
 [2 v o (i 0 1) 0 DVR ] 0 [2=A]vo (i): (3)
the ith-stage amplifier is designed to be 2m 0k . This will result in a Thus, the output of each stage consists of an ideal term and an error
correction range of 6k=2 least significant bits (LSB); that is, errors in term. Equation (3) shows that in order to cancel the gain error, we
the ith stage A/D subconverter that are within 6k=2 LSB are corrected simply need to add the quantity [2=A]vo to the actual output. Now the
by the digital error correction. For example, setting the interstage gain voltage at the summing node of the opamp is itself equal to 0vo =A.
to be equal to 2m 01 means that decision errors within 60.5 LSB can Thus, all that is needed is to add a scaled version of the summing node
be corrected. The value of the gain has to be precise. An error in the voltage to the output. It is important to note that this would calibrate
even the signal dependence of the opamp gain. This is the underlying
principle of the calibration schemes discussed below.
Manuscript received January 15, 2003; revised March 31, 2003. This paper
was recommended by Associate Editor M. Flynn.
A. Analog Calibration of Gain Error
A. M. A. Ali was with Texas Instruments, Inc., Warren, NJ 07059 USA. A straightforward analog scheme for canceling the opamp gain error
He is now with Analog Devices, Inc., Greensboro, NC 27409 USA (e-mail: is shown in Fig. 3. During the clock phase in which stage i generates
its residue, the voltage at the summing node of the opamp is buffered,
inverted, and passed on to stage i + 1 where it is multiplied by 2 and
K. Nagaraj is with Texas Instruments, Inc., Warren, NJ 07059 USA (e-mail:
Digital Object Identifier 10.1109/TCSII.2003.815024 added to the main residue from stage i. The capacitor C 3 in stage i+1 is

1057-7130/03$17.00 © 2003 IEEE