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The document describes designing a combinational multi-bit left-shifting circuit using divide-and-conquer. It involves:
(1) Breaking the problem of shifting an n-bit number X by a log2 n bit shift amount m into subproblems by dividing the bits of m.
(2) Describing any stitch-up functions or subproblem dependencies. Basic blocks at the leaf level should have inputs less than 4 bits.
(3) Providing a schematic for an (8,3) shifter identifying basic blocks, leaf functions, stitch-up functions, and critical path.
The document describes designing a combinational multi-bit left-shifting circuit using divide-and-conquer. It involves:
(1) Breaking the problem of shifting an n-bit number X by a log2 n bit shift amount m into subproblems by dividing the bits of m.
(2) Describing any stitch-up functions or subproblem dependencies. Basic blocks at the leaf level should have inputs less than 4 bits.
(3) Providing a schematic for an (8,3) shifter identifying basic blocks, leaf functions, stitch-up functions, and critical path.
The document describes designing a combinational multi-bit left-shifting circuit using divide-and-conquer. It involves:
(1) Breaking the problem of shifting an n-bit number X by a log2 n bit shift amount m into subproblems by dividing the bits of m.
(2) Describing any stitch-up functions or subproblem dependencies. Basic blocks at the leaf level should have inputs less than 4 bits.
(3) Providing a schematic for an (8,3) shifter identifying basic blocks, leaf functions, stitch-up functions, and critical path.
Use the divide-and-conquer (D&C) approach to design a combinational multi-bit left-shifting circuit with inputs that are an n-bit number X (the shiftee) and a log2 n bit # m (the shift amount), and which outputs a (2n 1)-bit number Z that is X shifted m times. E.g., if X = 11000111, and m = 110 = 6, then X needs to be shifted by 6 bits and Z = 011000111000000. Such a shifter is called an (n; log2 n), shifter—an (n; k) shifter shifts n bits of some inputX by the shift value encoded in k bits. As part of your design derivation, you need to clearly show the following aspects of your D&C approach. (a) The breakup of the root problem (i.e., the first level breakup) for an n-bit X into two or more subproblems, including a clear description of what those subproblems are. 50 (b) Stitch-up Issues: – If there is a stitch-up function for this problem derive the design. If the stitch-up function is a well-known or at least well-defined mathematical or logical function that you can describe mathematically and/or logically, then you need not derive the truth table (TT) or exact logic expressions and gate-level implementation of this function. Otherwise, you can just give the TT or logic expressions of the function. Note also, that in the former case, the stitch-up function can either be one well-defined function or a composition of two or more welldefined functions. – If there is subproblem dependency for your breakup, specify what it is, and if so, discuss if it makes sense to use the Wait or the DAC strategy to resolve the dependency, and do accordingly in your design. 25 (c) The leaf function, which is the function that is needed at the bottom of the D&C tree. Again, the leaf function should be described in a similar way as specified for the stitch-up function. Note that the level of the D&C tree at which the leaf function’s realization is appropriate is dependent on the design problem, and can typically range from a problem of size 1 to 4 bits. In this case, you need to judiciously determine this level so that it makes sense for the current problem. 50 (d) The schematic of the final design for an (8, 3) shifter, clearly identifying whichever of the following are there in your design: the leaf function, the stitch-up functions, the subproblem dependencies. The schematic should also show the smallest basic blocks of input size _ 4 (see 5 the next item for the definition) that the stitch-up and leaf blocks may be composed of. The structure of the circuit should be complete and clearly understandable. Show the critical path of your design in the schematic. 75 (e) Determine the delay of this circuit as a function of n, assuming that the delay of some welldefined basic function(s)/block(s) with a small constant number of inputs (i.e., whose number of inputs is not a function of n) that you use is 1 unit. Identify all your basic blocks. 50 (f) Analyze the hardware cost of your designs in terms of the number of the aforementioned welldefined basic function blocks (each with a constant number of, say, _ 4, inputs), i.e., assuming the cost of each such basic block is 1 unit. 50 Total 300 Hint: Perform the D&C of the design by breaking up the bits representing the shift amount m.