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  • University Institute of Engineering: Introduction To Microprocessor Architecture

    Diunggah oleh

    Abhishek Gaur
    15 tayangan12 halaman
    The document discusses the architecture of the 8085 microprocessor. It describes the three main buses - the address bus, data bus, and control bus. It explains that the lower order address/data lines AD0-AD7 are multiplexed and can serve as both the address lines and data lines depending on the ALE signal. Interrupt signals for the 8085 are also summarized in a table, listing the interrupt name and corresponding subroutine address for TRAP, RST 5.5, RST 6.5, RST 7.5, and INTR interrupts.

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    mp

    Judul Asli

    MP_unit_1_ppt2

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    The document discusses the architecture of the 8085 microprocessor. It describes the three main buses - the address bus, data bus, and control bus. It explains that the lower order address/data lines AD0-AD7 are multiplexed and can serve as both the address lines and data lines depending on the ALE signal. Interrupt signals for the 8085 are also summarized in a table, listing the interrupt name and corresponding subroutine address for TRAP, RST 5.5, RST 6.5, RST 7.5, and INTR interrupts.

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    © All Rights Reserved
    Unduh sebagai PDF, TXT atau baca online dari Scribd
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    15 tayangan12 halaman

    University Institute of Engineering: Introduction To Microprocessor Architecture

    Diunggah oleh

    Abhishek Gaur
    The document discusses the architecture of the 8085 microprocessor. It describes the three main buses - the address bus, data bus, and control bus. It explains that the lower order address/data lines AD0-AD7 are multiplexed and can serve as both the address lines and data lines depending on the ALE signal. Interrupt signals for the 8085 are also summarized in a table, listing the interrupt name and corresponding subroutine address for TRAP, RST 5.5, RST 6.5, RST 7.5, and INTR interrupts.

    Hak Cipta:

    © All Rights Reserved
    Unduh sebagai PDF, TXT atau baca online dari Scribd
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    dari 12

    University Institute of Engineering

    Department of Electronics & Communication Engineering

    Introduction to Microprocessor
    Architecture

    Prepared By:
    Sukhpreet Singh
    E1474
    Three Buses in 8085

    Address bus

    Data bus

    Control bus

    UIE, ECE Deptt.


    Figure-Bus structure of 8085 MPU
    UIE, ECE Deptt.
    Buses Name

    Address Bus *AD0-AD7 Bidirectional

    A8-A15 Unidirectional

    Data Bus *AD0-AD7 Bidirectional

    • *AD0-AD7 is multiplexed bus that can serve as


    both lower order address bus and data bus(D0-
    D7) depend upon the status of ALE signal

    UIE, ECE Deptt.


    Chip Selection
    A15- A10 Circuit

    8085
    CS
    A15-A8

    ALE
    A9 - A0 1K Byte
    Latch Memory
    AD7-AD0 A7 - A0 Chip

    WR RD IO/M D7 - D0
    RD WR

    Figure-Connection of different units through buses

    UIE, ECE Deptt.


    UIE, ECE Deptt.
    6
    UIE, ECE Deptt.
    7
    Figure-Signals and I/O Pins[1]
    UIE, ECE Deptt.
    8
    Table- Control and status signals[1]
    UIE, ECE Deptt.
     8085 μp has several interrupt signals as shown in the following table.

    UIE, ECE Deptt.


    Table- Interrupt signals[1]
    Interrupt Subroutine address
    TRAP 0024
    RST 5.5 002C
    RST 6.5 0034
    RST 7.5 003C
    INTR Address is determined by external
    hardware

    UIE, ECE Deptt.


    1. 8085 Microprocessor hardware and interfacing, R. Goenkar 5th
    edition,2008 Penram International Publishing house
    2. http://www.nptel.ac.in/courses/Webcourse-contents/IISc-
    BANG/Microprocessors%20and%20Microcontrollers/pdf/Lectur
    e_Notes/LNm1.pdf
    3. Barry B. Brey, “The 8085A Microprocessors: Architecture,
    Programming & Interfacing” PHI, 6th Edition, 2003

    UIE, ECE Deptt.

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