BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, PILANI

I SEMESTER 2004-05
EEE/INSTR/CS C391 DIGITAL ELECTRONICS AND COMPUTER
ORGANIZATION
COMPREHENSIVE EXAMINATION (OPEN BOOK)

Part B MM: 75

Note: Attempt all parts of a question in continuation.

Q1. For the Boolean expression given below
F(A,B,C,D) =  (0,2,3,4,6,11,12,13,15)
(i) Plot the k-Map
(ii) Identify the Prime Implicants
(iii) Identify the essential Prime Implicants
(iv) Obtain the minimal SOP for F
(v) Draw the two level NAND – NAND implementation for the function F
(vi) How many different minimal SOPs are possible for F
(1+3+2+3+3+3)
Q2. (i) Design a 4:1 MUX using only 2:1 MUXs.

(ii) Using required number of 2:1 MUXs and NOT gates design a logic circuit
to implement the function Z = ( a+b+c) mod 2 where a,b,c are 1 bit numbers
( i.e., Z is the remainder of the operation (a plus b plus c) / 2)
(iii) A 4-bit serial in Parallel out right shift register with asynchronous preset has
its initial value loaded as (y3 y2 y1y0= 1101). It is required to generate an out
put sequence at y3.The desired output sequence at y3 is 110111001000 and it
repeats after these twelve bits. Design the combinational logic(ref figure) as
a minimal circuit.
(3+6+6)
Q3. A 4-bit sequential odd parity checker is to be designed. The input to the circuit is
a string of bits. The circuit should check parity of 4 consecutive bits and set the
output bit to 1 if the parity is odd. The circuit is in initial state ( S 0) when the first
bit arrives. The circuit goes back to the initial state after the 4 th bit has arrived and
start checking the parity for the next 4 bits and the process repeats.
(i) Draw the state diagram ( having not more than eight states)
(ii) Draw the State table
(iii) Design the logic circuit using required number of DFFs and gates
(8+3+4)

Q4.(i) A logic circuit takes input as an 8-bit number (D7-D0) and rotates it through
left by n- bits where n is the position of leading one in the input number.

Ex: Input number - 00010110

Output number – 01100001.

Assume that the number is preloaded in an 8-bit shift register and the final
rotated output should be in the shift register itself.

Design the circuit using the components chosen from the list given below:
(8:3 priority encoder, 3bit binary counter with parallel load and count enable
signal, Basic gates, 3:8 decoder)

(ii) Draw the ASM Chart for the controller of a system that has an 8-bit register A and a
3-bit register N. When a signal 1 appears on input line s, the register A is shifted right
the number of places (0 to 7) as specified by N ( with 1’s put in the left bits). The
register A can be shifted only one place at a time. The register N can be decremented
(decreased by 1). When shifting is complete, a 0 is to appear on output line d for two
clock pulses.
(8+7)
Q5. (a) For the Boolean Expression given below
Y = AB + AC
(8+7)
(i) Design the function using CMOS logic
(ii) Design the function using transmission gate

(b) Using the Execution unit given in the text as a reference write the RTL
statements and control sequence for the implementation of the following
instruction.

Adds a data from memory with the contents of internal register R2 and puts
the result the same memory location. The address of memory location is
provided by the internal register R1.

.
 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, PILANI
I SEMESTER 2004-05
EEE/INSTR/CS C391 DIGITAL ELECTRONICS AND COMPUTER
ORGANIZATION
COMPREHENSIVE EXAMINATION (OPEN BOOK)
MM: 110 Time: 3Hrs 14-12-2004

Note: The question paper consist of two parts PART A and PART B. PARTA to be
answered in the question paper itself and PART B in a separate answer sheet
provided. The expected time for completion of PART A is 1 Hr, however you
can collect Part B question paper once you submit Part A. You can use last
two pages of Part B answer book for rough work.

Part A MM: 35

Name: Sec No:

IDNO:
Marks Obtained:

Recheck request if any:

Q1. The gray code equivalent of a binary number is given as 10110. Write down its
excess-3 code.

(1)
Q2. Write down the sum of minterms and product of maxterms for the function F
given below.
F ( x,y,z) = x’ + x(x’y + y’z)’

(2)
Q3. How many 7400 ICs would be required to construct a 3-bit even parity checker.

(1)

Q4. Determine the propagation delays for a NOR gate whose input and output
waveforms are as given below.
 (2)
Q5. A digital circuit with three inputs and two outputs are described by the following
Boolean expressions. Identify the minimum size of PLA required to implement
the circuit.
F1(A,B,C) = (0,1,3,5,6)
F2(A,B,C) = (0,3,5,7)

(2)

Q6. Specify the size of the ROM required to design a circuit for converting 7bit
ASCII code into 18 segment display code.

(1)
Q7.Given a 100 MHz clock signal, derive a circuit using only DFFs to generate a 50
MHz and 25 MHz clock signals.

(2)
Q8. Design a sequential circuit using only T FFs which will count in the following
Sequence. 000,100,010,111,000….

(3)

Q9. Implement a D Latch ( Positive level triggered) using only a 2:1 MUX.

(2)

Q10. Which out of SRAM and DRAM is

(a) offers higher density Ans:
(b) used for cache memories Ans:
(c) volatile Ans:
(d) requires refresh circuitry. Ans:
(2)
Q11. Modify a 4-bit switch tail ring counter such that it skips the 1111 state. Draw the
modified circuit.

(4)

Q12. Write down the verilog code for a 1:4 DeMUX using behavioral modelling.

(3)
Q13. Can a 7493 IC be made to work as a mod-10 counter? If yes, then how?

(2)

Q14. Show how is IC74155 is made to work like a DEMUX?

(2)

Q15. Consider a machine with byte addressable main memory of 2 20 bytes and
block (line) size of 16 bytes. Assume that the a direct mapped cache
consisting of 32 lines is used. (3)
(i) How is the 20 bit memory address divided into tag, line number and byte
number

(ii) Into what line is the byte with following address is stored.
00111011010011100110

(iii) How is the 20 bit memory address divided into tag, set number and
byte number if the cache used is 4 way associative.

Q16. An asynchronous sequential circuit has two internal states. The excitation
functions describing the circuit are
Y1 = x1x2+x1 y2’+x2’y1
Y2 = x2+x1y1’y2+x1’y1 (3)
(i) Draw the logic diagram of the circuit

(ii) Derive its transition table