1.

GENERAL DESCRIPTION

1.1 ES66x8

The ES66x8 Vibratto II processor is a highly integrated single-chip DVD solution that integrates read
channel, ECC, Servo DSP, MCU, and MPEG-2/MPEG-4/DivX decoder that has a state-of-the-art 480p/576p
progressive-scan video feature to provide brilliant and sharp, flicker-free video output to the display, and with
built-in gamma correction and S/PDIF input and output support. The 66x8 performs audio/video stream data
processing, TV encoding, Macrovision copy protection, DVD system navigation, system control, and
housekeeping functions.

The Vibratto II DVD processor is built on the ESS proprietary dual CPU Programmable Multimedia
Processor (PMP) core consisting of 32-bit RISC and 64-bit DSP processors and offers the best DVD feature set.

These features can be listed as follows:

General Features:

-Single-chip DVD processor incorporating all front-end and back-end functions.

-Unified memory architecture.

-Built -in ADCs and DACs for servo control signals .

-DVD-Video, DVD-VR, VCD 1.1 and 2.0 and SVCD

-Proven ECC, EFM/EFM+ demodulation, and EDC circuit.

-Direct interface of 16-bit DRAM up to 128-Mb capacity.

-Direct interface of 8- or 16-bit SDRAM up to 128-Mb capacity.

-Direct interface for up to 4 banks of 8-bit EPROM or Flash EPROM for up to 4 MB per bank.

-Direct interface to the ES6603 servo AFE chip.

Video Related Features:

-Integrated NTSC/PAL encoder with pixel-adaptive de-interlacer and five 10-bit 54 MHz v ideo DACs .

-DivX and MPEG-4 Advanced Simple Profile at full screen.

-Media playback with CD-ROM, CD-R/RW, DVD-R/RW and DVD+R/RW.

-Macrovision 7.1 for NTSC/PAL interlaced video.

-Macrovision NTSC/PAL (480p/576p) progressive scan video.

-Simultaneous composite, S-video and YUV outputs.

-CCIR656/601 YUV 4:2:2 output.

-OSD controller supports 256 colors in 8 degrees of transparency.

-JPEG digital photo CD support ( Kodak Picture CD and Fujifilm FujiColor CD ).

2
Audio Related Features:

-Full DVD-Audio support including MLP and LPCM decode, CPPM decryption, and watermark detection.

-Up to 7.1 channel audio outputs .

-Bass management.

-Dolby Digital ( AC-3 ), Dolby Pro Logic, and Pro Logic II.

-DTS surround ( ES6698 only ).

-S/PDIF digital audio input and output.

-SRS TruSurround.

-Professional karaoke with full scoring scheme.

1.2 M EMORY

1.2.1 System SRAM Interface

The system SRAM interface controls access to optional external SRAM, which can be used for RISC
code, stack, and data. The SRAM bus supports four independent address spaces, each having programmable bus
width and wait states. The interface can support not only SRAM, but also
ROM/EPROM and memory-mapped I/O ports for standalone applications are supported.

1.2.2 DRAM Memory Interface

The Vibratto II provides a glueless 16-bit interface to DRAM memory devices used as video memory
for a DVD player. The maximum amount of memory supported is 16 MB of Synchronous DRAM (SDRAM).
The memory interface is configurable in depth to support 128-Mb addressing. The memory interface controls
access to both external SDRAM or EDO memories, which can be the sole unified external read/write memory
acting as program and data memory as well as various decoding and display buffers.

1.3 FRONT PANEL

The front panel is based around an Futaba VFD and a common front panel controller chip, (uPT6311).
The ES66x8 controls the uPT6311 using several control signals, (clock, data, chip select). The infrared remote
control signal is passed directly to the ES66x8 for decoding.

1.4 REAR PANEL

A typical rear panel is included in the reference design. This rear panel supports:

- six channel and two channel audio outputs

- Optical and coax S/PDIF outputs.

- Composite, S-Video, and SCART outputs

The six-video signals used to provide CVBS, S-Video, and RGB are generated by the ES66x8’s internal video
DAC. The video signals are buffered by external circuitry.

Six channel audio output by the ES66x8 in the form of three I2 S (or similar) data streams. The S/PDIF serial
stream is also generated by the ES66x8 output by the rear panel. A six channel audio DAC are used for six
channel audio output with ES66x8, and similarly one Audio DAC is used for two channel audio output with
ES66x8.

3
 2. System Block Diagram and ES66x8 Pin Description

2.1 ES66x8 Pin Description

4
5
6
7
8
9
 2.2 SYSTEM BLOCK DIAGRAM

A sample system block diagram for the ES66x8 Vibratto II DVD player board design is shown in the
following figure:

3. AUDIO OUTPUT

The ES66x8 supports two-channel analog audio output while ES66x8 supports six-channel analog audio
output. In a system configuration with six analog outputs, the front left and right channels can be configured to
provide the stereo (2 channel) outputs and Dolby Surround, or the left and right front channels for a 5.1 channel
surround system.

The ES66x8 also provides digital output in S/PDIF format. The board supports both optical and coaxial S/PDIF
outputs.

4.AUDIO DACS

The ES66x8 supports several variations of an I2 S type bus, varying the order of the data bits (leading or
no leading zero bit, left or right alignment within frame, and MSB or LSB first) is possible using the ES66x8
internal configuration registers. The I2 S format uses four stereo data lines and three clock lines. The I2 S data and
clock lines can be connected directly to one or more audio DAC to generate analog audio output.

The two-channel DAC is an CS4392. The DACs support up to 192kHz sampling rate.

The outputs of the DACs are differential, not single ended so a buffering circuit is required. The buffer circuits
use National LM833 op-amps to perform the low-pass filtering and the buffering.

10
5 VIDEO INTERFACE
5.1 Video Display Output
The video output section controls the transfer of video frames stored in memory to the internal TV encoder
of the Vibratto II. The output section consists of a programmable CRT controller capable of operating either in
Master or Slave mode.

The video output section features internal line buffers which allow the outgoing luminance and
chrominance data to match the internal clock rates with external pixel clock rates, easily facilitating YUV4:2:2 to
YUV4:2:0 component and sample conversion. A polyphase filter achieves arbitrary horizontal decimation and
interpolation.

Video Bus
The video bus has 8 YUV data pins that transfer luminance and chrominance (YUV) pixels in CCIR1656
pixel format (4:2:2). In this format, there are half as many chrominance (U or V) pixels per line as luminance (Y)
pixels; there are as many chrominance lines as luminance.

Video Post-Processing
The Vibratto II video post-processing circuitry provides support for the color conversion, scaling, and
filtering functions through a combination of special hardware and software. Horizontal up-sampling and filtering
is done with a programmable, 7-tap polyphase filter bank for accurate
non-integer interpolations. Vertical scaling is achieved by repeating and dropping lines in accordance with the
applicable scaling ratio.

Video Timing
The video bus can be clocked either by double pixel clock and clock qualifier or by a single pixel clock.
The double clock typically is used for TV displays, the single for computer displays.

6 SDRAM MEMORY
The memory bus interface generates all the control signals to interface with external memory. The
Vibratto II supports different configurations using the memory configuration bits SDCFG[1:0] (bits 12:11), the
SD8BIT bit (bit 14), and SD64M bit (bit 15) in the BUSCON_DRAM_CONTROL register. Configurations can
be implemented in many ways. The following table lists the typical SDRAM configurations used by the Vibratto
II.

11
Typical SDRAM Configurations:

The memory interface controls access to both external SDRAM or EDO memories, which can be the sole
unified external read/write memory acting as program and data memory as well as various decoding and display
buffers. At high clock speeds, the Vibratto II memory bus interface
has sufficient bandwidth to support the decoding and displaying of CCIR1656/601 resolution images at full
frame rate.

7 FLASH MEMORY
The decoder board supports AMD class Flash memories. Currently 4 configurations are supported:

FLASH_512K_8b
FLASH_1024K_8b
FLASH_512Kx2_8b
FLASH_512Kx2_16b

The Vibratto II permits both 8- and 16-bit common memory I/O accesses with a removable storage card
via the host interface.

8 S ERIAL EEPROM MEMORY

An I2C serial EEPROM is used to store user configuration (i.e. language preferences, speaker setup,
etc.) and software configuration.. Industry standard EEPROM range in size from 1kbit to 256kbit and share the
same IC footprint and pinout. The default device is 2kbit, 256kx 8, SOIC8 SGS Thomson ST24C02M1 or
equivalent.

12
9 AUDIO INTERFACE AUDIO SAMPLING RATE AND PLL COMPONENT
CONFIGURATION
The ES66x8 Vibratto II audio mode configuration is selectable, allowing it to interface directly with
low-cost audio DACs and ADCs. The audio port provides a standard I2 S interface input and output and S/PDIF
(IEC958) audio output. Stereo mode is in I2 S format while six channels Dolby Digital (5.1 channel) audio output
can be channeled through the S/PDIF. The S/PDIF interface consists of a bi-phase mark encoder, which has low
skew. The transmit I2 S interface supports the 128, 192, 256, 384, and 512 sampling frequency formats, where
sampling frequency Fs is usually 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, or 192 kHz. The audio samples for the I2 S
transmit interface can be 16, 18, 20, 24, and 32-bit samples.

For Linear PCM audio stream format, the Vibratto II supports 48 kHz and 96 kHz. Dolby Digital audio
only supports 48 kHz. The ES66x8 Vibratto II incorporates a built-in programmable analog PLL in the device
architecture in order to generate a master audio clock. The MCLK pin is for the audio DAC clock and can either
be an output from or an input to the ES66x8 Vibratto II . Audio data out (TSD) and audio frame sync (TWS) are
clocked out of the Vibratto II based on the audio transmit bit clock (TBCK). Audio receive bit clock (RBCK) is
used to clock in audio data in (RSD) and audio receive frame sync (RWS).

10 FRONT PANEL

10.1 VFD CONTROLLER

The VFD controller is a PTC PT6311. This controller is not a processor, but does include a simple state
machine which scans the VFD and reads the front panel button matrix. The 6311 also includes RAM so it can
store the current state of all the VFD icons and segments. Therefore, the 6311 need only be accessed when the
VFD status changes and when the button status is read. The ES66x8 can control this chip directly using PIO pins
or can allow the front panel PIC to control the VFD.

11 MISCELLANEOUS FUNCTIONS
11.1 RESET CIRCUITRY
Two different chips are supported to provide the power-on-reset and pushbutton reset function:
AAT3521 or V6300.

12 CONNECTORS

12.1 SCART CONNECTORS

Pinout of the scart connector:

1 ? Audio Right Out

2 ? Audio Right In
3 ? Audio Left / Monu Out
4 ? Audio Gnd
5 ? Blue Gnd
6 ? Audio Left / Mono In
7 ? Blue
8 ? Control Voltage
9 ? Green Gnd
10 ? Comms Data 2
11 ? Green

13
12 ? Comms Data 1
13 ? Red Gnd
14 ? Comms Data Gnd
15 ? Red
16 ? Fast Blanking
17 ? Video Gnd
18 ? Fast Blanking Gnd
19 ? Composite Video In
20 ? Composite Video Out
21 ? Shield

Some cheaper SCART cables use unshielded wires, which is just about acceptable for short cable lengths.
For longer lengths, shielded coax cable become essential.

Scart Signals:

Audio signals
0.5V RMS, <1K output impedance, >10K input impedance.

Red, Green, Blue

0.7Vpp ? 2dB, 75R input and output impedance. Note that the Red connection (pin 20) can alternatively carry the

S-VHS Chrominance signal, which is 0.3V.

Composite Video / CSync

1Vpp including sync, ?2dB, 75R input and output impedance.Bandwidth = 25Hz to 4.8MHz for normal
TV Video de-emphasis to CCIR 405.1 (625-line TV)

Fast Blanking

75R input and output impedance. This control voltage allows devices to over-ride the composite video
input with RGB inputs, for example when inserting closed caption text. It is called fast because this can be done
at the same speeds as other video signals, which is why it requires the same 75R impedances.

0 to 0.4V: TV is driven by the composite video input signal (pin 19).

Left unconnected, it is pulled to 0V by its 75R termination.

1V to 3V: the TV is driven by the signals Red, Green, Blue and composite sync. The latter is sent to the
TV on pin 19. This signal is useful when using a TV to display the RGB output of devices such as home
computers with TV-compatible frame rates. Tying the signal to 5V via 100R forms a potential divider
with the 75R termination, holding the signal at around 2V. Alternatively, if a TTL level (0 to 5V)
negative sync pulse is available, this will be high during the display periods, so this can drive the
blanking signal via a suitable resistor.

Control Voltage

0 to 2V = TV, Normal.
5 to 8V = TV wide screen
9.5 to 12V = AV mode

14
12.2 CABLE DIAGRAM

ITEM: PART NO: DESCRIPTION: CODE:

A 9JB30017144 CONN ASSY 8P 30CM W/FERRRITE (TMM)ROHS
B 9JB30018384 CNAS 5P/150 SIS W/C+BRT UL1007AWG24
C 9JB30018953 POWER CORD SAFE ASSY.(1.8MT W/FTZ)-ROHS
D 9JB30016836 CNAS 6P/230 SIS W/C+BRT+FER UL1007AWG24
E 9JB30022665 CNAS 11P/150 DVD SIS W/DC UL1007#26 ROHS

13 CIRCUIT DESCRIPTION

13.1 POWER SUPPLY

-Socket PL2 is the 220VAC input.

-Socket PL3 is used for the power button on the front panel.
-3.15A fuse F1 is used to protect the device against short circuit.
-Voltage is rectified by using diodes D1, D2, D3 and D4. Using capacitor C33 (47?f) a DC voltage is
produced. (310- 320VDC).
- The current in the primary side of the transformer TR2 comes to the SMPS IC (TNY267P). It has a built-
in oscillator, over current and thermal protection circuitry and runs at 133kHz. It starts with the current from
the primary side of the transformer and follows the current from the feedback winding.
- Voltages on the secondary side are as fo llows: 12 Volts at pin11 at C42, 5 Volts at C40,3.3 Volts at C38,

-22Volts at C44,-12 Volts at D22.

-D14 TL431 is a constant current regulator. TL431 watches the 5 volts and supplies the required current to
IC2. There are a LED and a photo transistor in IC2. The LED inside the IC2 transmits the value of the
current from D25 to phototransistor. Depending on the current gain of the phototransistor IC3 keeps the
voltage on the 5-volt-winding constant.
-–22 Volts is used to feed the VFD (Vacuum Fluorescent Display) driver IC on the front panel.

15
Functional Block Diagram of Switcher

13.2 FRONT PANEL:

-All the functions on the front panel are controlled by U1 (ES66x8) on the mainboard.
-U1 sends the commands to IC2 PT6311 via socket J2 (pins 3,4 and 5).
-There are 48 keys scanning function, 5 LED outputs, 1 Stand-by output and VFD drivers on PT6311.
-Vacuum fluorescent display is specially designed for DVD.
-The scanned keys are transmitted via PT6311 to U1 on the mainboard.
-IR remote control receiver module sends the commands from the remote control directly to U1.

13.3 BACK PANEL:

-There are 1 SCART connector (con24), 2 pieces RCA audio jacks for audio output, 1 coaxial digital audio
output and 1 laser digital audio output on the back panel.
-MOFT3C2 is used for laser output.
-Left and right audio outputs are on RCA Conn 6.
-LUMA and CHROMA signals of S-Video are transmitted to P1 via transistors Q39 and Q37 respectively.

16
CD Update Procedure of DV-SV90
1. Download the update file from the convenient link according to your default language choice.

2. While there is no CD in the DVD (No Disc Mode) , press “Menu 1 3 5 7” buttons on the remote control
in order to reach the Service Menu of DVD Player:

2.1. Note the software version described as “b.xx “ to be able to compare the sw. Version after update
process.
3. Copy the update file to the desktop and rename it according to the update file name in the hidden menu of
the device.
For example If C2M1AS__ is written then rename it like C2M1AS__.rom
If P6M1AS__ is written then rename it like P6M1AS__.rom

(If you receive the update file already renamed (with addition of .rom) from the customer technical support
department by giving the SAP code of the product then burn the already renamed file with nero program as
it is shown below.)

4. Burn the renamed files by Nero program with below set up.

5. After burning process is completed, place the update CD into the DVD tray and press play button.

6. Wait to see the update process steps as shown below. When the sw. Update is completed unit will switch
itself to standby mode.

7. Finally, press the eject button and take out the update CD while DVD Player remains at stand by Mode.

8. Updating process has been completed. To check whether it is updated correctly or not, repeat the first step
for comparing software version

9. If the previous and letter names are different, CD is update has completed successfully. If the name remains
same than go through the steps from the beginning.

IMPORTANT NOTE: If the AC source breaks down while the updating the unit (main board) will be
totally out of order. This kind of units/boards is out of Warranty.

17
Brief Information of Naming the File
Software version differs from each other depending on front models. 23xx and 24xx are called Old VFD and
25xx and 26xx are called Mini VFD. Each character in the file name is an abbreviation of a description as
illustrated below.

C2M1AS _ _
Progressive Option (with progressive : P, without progressive: _ )
DMR option (with DMR:R, without DMR:_ )
Loader Type (S loader:s W loader:w)
Flash Type ( AMD:A, Intel:I )
Language group

VFD type
DAC channel (2, 6)
DAC Type

Pay attention the left side. Select CD and CD_ROM (ISO) on the upper left side of screen

18
Select No Multisession

19
Format is Mode 1

20
21
Leave the dates as it is

22
Leave it as it is

23
Click the “New” on the upper right corner of the screen

24
 Select your file from file browser then you will see your file in the “Name” section on the right side and
then copy the files to under “Name” section on the left side.(this is just an example you will see your file name
when you are doing this process)

25
Click the “Burns the current compilation”

26
Then you will see this screen and click the “Burn” on the right upper side of screen

27
You will see this screen and tray will open itself on computer ,then place the CD in CD-ROM
And it will start writing. At the end you will see “burn complated”

REPLACEMENT PART LIST

SV9C ITEMS: PART NO: DESCRIPTION: CODE:

1.DVD Main Board 9JB20202584 MAIN.4250.W.DCS.4392.2C.1X64+OO.F1.MAN
2.Power Board 9JB20183698 POWER.PI.SR.25/26.X.HYR0+V.E2.MAN.FS25
3.Display Board 9JB20151443 FRONT.DVD.2620+X+V.E1+EMC+PI.MAN
4.Scart Terminal Board 9JB20175901 SCART.DVD+X.12SCP06E2+PRO+EMC.MAN
5.Loader Unit 9JB30031946 DVD LOADER SAFE LN9815H2-B 1200 W
6.Front Panel 9JB40019909 FRONT PANEL ASSY DVD 2622
7.Top Kabinet 9JB35010811 TOP COVER 2600 M.SILVER (R03)(60002225)
8.Bottom Kabinet 9JB35010505 Bottom Cover DVD 26XX (HDG)
9.Rear Panel 9JB35011931 BACK COVER 2621 SV90 REG2 SHARP
10.Operation Manual 9JB50061018 KUL.KLV. SHARP DV-SV9C FRA/HOL
11.Remote Control Unit 9JB30036682 R/C 2531 DVD SHARP (SILVER)
12.Carton 9JB50061021 KARTON KUTU 2622 SHARP DV-SV9C/ENG

28
 5 4 3 2 1
4250H REV-A1 ES66x8 + DV34/502W/S71/SONY310 PICKUP + OUTPUT
Layout---------VESTEL-4250H REV-A1B1
D D
Background Revision History
This DVD design is based on ESS Vibratto-II ES66x8 single chip DVD mpeg and servo processor. The ES66x8 is built upon Rev-A1
ESS proven Programmable Multimedia Processor architecture with integrated servo DSP. A complete DVD design using 1. Base on HQ ES66x8 reference design and our previous ES60X8 reference design to form the schematic.
ES6603 RF-Amp can support all major popular optical pickup heads. With ES66x8 unify memory architecture, the whole
system memory is reduced to a minimum. ES66x8 provides the best price performance DVD solution in the industry.
andy_ho@esstech.com.hk
System Clock Requirement
ES66x8 require a 27MHz clock to operate. This 27MHz can either be generated externally and feed into pin 3 and pin 4 or
thru a 27MHz crystal attached to pin 2 and 3. This 27Mhz will be used for all video processing reference. In addition, internal
multiplier will generate a much higher operating frequency for the internal RISC+DSP code to operate. Audio clock is
generated from ES66x8 by its internal PLL circuitry.
SDRAM Usage
ES66x8 support the use of higher density 4Mx16 SDRAM. A sinlge of 4Mx16 SDRAM is sufficient for the whole system to
operate.
C C
System Configuration
CHIP FUNCTION
ES66x8 Single chip processor that handles all system control, DVD decoding and servo control.
64MBit SDRAM Data storage and frame buffer
8Mbit EPROM/FLASH Program storage
24C01 SERIAL EE System setup configuration storage
WM8706 2-Channel AudioDAC
WM8746 6-Channel AudioDAC
WM8739 2-Channel AudioADC
LCSx# FUNCTION
LCS0# SPARE
LCS1# 74HCT374 (U16) I/O EXPAND CONTROL
LCS2# ROM EMULATOR
LCS3# ROM/FLASH
B B
AUXx FUNCTION EAUXx FUNCTION
AUX0 I2C DATA EAXU00 AUDIODAC MD
AUX1 I2C CLOCK EAUX01 AUDIODAC MC
AUX2 MICMUTE / HSYNC EAUX02 AUDIODAC ML
AUX3 SCARTCTL / VSYNC EAUX03 AUDIOADC CSB#
AUX4 IR
AUX5 VFD DATA
AUX6 VFD CS
AUX7 VFD CLK
XGPIOx FUNCTION
XGPIO4 MOCTL / RS232 DET
XGPIO5 DRVSB
XGPIO6 OUTSW
XGPIO7 CLOSE
XGPIO8 HOMESW
A
XGPIO9 INSW A
Title
Index
Size Document Number Rev
C VESTEL-4250H-A1 A1
Date: Wednesday, March 03, 2004 Sheet 1 of 5
5 4 3 2 1
 VCC33 VCC33 VCC33 VCC33
XFLAG0 TP1 RR1 4.7K
XFLAG1 FLAG0 TP2 VCC33 MULTI Frequency
XFLAG2 TP3 FLAG1 RR2 4.7K PLL3 CLK SOURCE R1 R2 R3 R4 PLL2 PLL1 PLL0 DEFAULT S-CHIP DEFAULT S-CHIP
XFLAG3 FLAG2 TP4 TXD
JJ1
1 DCLK INPUT OPEN OPEN OPEN OPEN 0 0 0 4.25 4.5 114.75 121.5
VIDEO OUTPUT TABLE
RFO TP5 FLAG3 RS232_DET 1 SERVO MCU 0 CRSTAL OSC 0 0 1 reserved 5 NA 135 CVBS + S-VIDEO CVBS + YUV S-VIDEO + RGB CVBS + RGB
TESTAD RFO TP6 RXD 2 DEBUG 0 1 0 bypass bypass 27 NA or CVBS + YUV
DA TP7 TESTAD VCC 3 0 1 1 3.75 4 101.25 108 VDAC CVBS CVBS Y CVBS
RFRP DA TP8 4 HEADER 1 0 0 4.5 4.25 121.5 114.75 VCCV YDAC Y Y G G
5 SPDIF (5) 1 0 1 reserved 4.75 NA 128.25 CDAC V V R R
DIP TP9 RFRP
TBCK (4) 1 1 0 3.5 5.5 94.5 148.5 UDAC U U B B
DIN DIP TP10
MCLK (4)

1
TRACK TP11 DIN 1 1 1 4 6 108 162 D1 FDAC C CVBS C CVBS
FOCUS STRACK TP12 GND CC1
TSD2 (4)
SLEGP TP13 SFOCUS CC2 1000P
TSD1 (4)
SLEGN SSLEGP TP14 RS232 CONNECTOR 2.54MM 1000P CC3 1N6263 L1
TSD0 (4)
SPINDLE TP15 SSLEGN RFGND CC4 1000P 2.4UH
TWS (4) UDAC (5)

21
MIRR SSPINDLE TP16 1000P VCCV VCC VCCV D2
TEI TP17 MIRR SBAD RR3 3.3K R5 FB1 R6
(3) SBAD FERB
FEI TEI TP18 FEI RR4 3.3K R7 R8 R9 R10 4.7K C1 C2
(3) FEI

1
CEI TP19 FEI CEI RR5 3.3K 4.7K 4.7K 4.7K 4.7K D3 1N6263 75 OHM 470PF 470PF
(3) CEI
SPDON CEI TP20 TEI RR6 3.3K
(3) TEI
SFGIN TP21 XSPDON

2
FGIN CC5 1N6263 GNDV GNDV GNDV L2 GNDV
DIP CC58 0.1U GND GND GND GND GND 2.4UH
(3) DIP CDAC (5)

21
4700P RR7 10K UDAC1 D4
R51 0 RS232_DET RFO CC59 CDAC1 VCCV R11
(3) MOCTL (3) RFO YDAC1
C CC8 4.7U C3 C4

1
TP36

TP37

TP38

CC61 VDAC1 1N6263 D13 75 OHM 470PF 470PF

SVREF21 C CC46 FDAC1
(3) SVREF21 DIN CC55 1U

2
XS XS XS
SVREF15

(3) DIN
4700P CC12 GNDV 1N6263 GNDV GNDV GNDV
DEFCT 1U VCC33V L3 2.4UH
SDEFCT (3) YDAC (5)

21
SPDON VCCV D11
SLDC SPDON (3)
RR8 68K R63
SLDC (3)
R59 390 C5 C6

1
RR9 20K C7 0.1U VCC33V D12 1N6263 75 OHM 470PF 470PF
RF33V C8 0.1U
SVREF21
SVREF09

10x4 CC13 CC14 CC15 CC16 R50 0 OHM

2
1N6263 GNDV GNDV GNDV GNDV
8 1 EAUX40 0.1U 0.1U 0.1U C GNDV L4 2.4UH

VS33_PL2
VCC33V
VCC33 VDAC (5)

21
CDAC1
UDAC1

EAUX41 YDAC1

VDAC1
VCC20

FDAC1
CC17 D8 VCCV

COMP
RFRP

SPDIF
XFLAG3
XFLAG2
XFLAG1
XFLAG0

7 2 GND
MCLK
RXD

GNDV
TBCK

TSD2

TSD1
TSD0
TXD

RSET

VREF
TWS

EAUX42
TESTAD

6 3 6800P R62
5 4 EAUX43 C9 C10

1
RFGND 1N6263 D9 75 OHM 470PF 470PF
RFGND VCC33
RN4

2
RR10 0 RFRP GNDV 1N6263 GNDV GNDV GNDV
U1 L5 2.4UH
FDAC (5)

21
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109
108
107
106
105
RR15 33K TESTAD RR14 R CC18 PLL33V ES66x8 D10
(3) MIRR
C FB2 R61
RR12 R SVREF15 TR1 CC19 C11 C12

VS33_PL
XSWBL
XSIP1
XSIP2

TSD3
TSD2
VS33
VD33

VS33
TSD1/SEL_PLL1
TSD0/SEL_PLL0
TWS/SEL_PLL2
AVDD3_DS

AVDD3_AD

XSLG

VS33_DA
VD33_DA
SPDIF/SEL_PLL3
AVSS_AD

YUV0/UDAC
YUV2/CDAC
YUV5/YDAC

YUV6/VDAC

YUV3/COMP
XSRFIP
XSRFIN
XSIPIN

XSIREF

XSRFRP
XSTEI
XSCEI

XSFEI
XSSBAD

VDD

YUV7/FDAC
YUV4/RSET

YUV1/VREF
XSTESTAD
XSTEXI

VSS

SPDIFIN

TBCK
MCLK
XSWBLCLK
XSDSSLV

XSVREF[15]
XSVREF[09]
XSVREF[21]

XSFLAG[3]
XSFLAG[2]
XSFLAG[1]
XSFLAG[0]

(3) ATR_OP FERB

C 1N6263 75 OHM 470PF 470PF
CC20 RR16 1.2K CC21 CC22
1U 0.047U

2
TR2 CC23 0.1U GNDV GNDV GNDV GNDV
560P 157 104 VD33_PL1
RR87 0 AVSS_DS VD33_PLL
158 AVSS_PL RWS/TDMFS 103
159 XSPDOFTR1 RBCK/TDMCLK 102
160 101 R17 0
RR17 10K XSFDO RSD/TDMDR LD7 VCC R18 OPEN
161 XSFTROPI LD7 100 VCC33
CC24 CC25 CC26 RR18 5.1K 162 99 LD6
TR1 AVDD3_PL LD6 LD5
163 XSPLLFTR1 LD5 98
RFGND PLLGND 0.1U 47P 0.1U TR2 164 97 LD4 U2
XSPLLFTR2 LD4 LA16 LA17
165 XSVREF0 VD33 96 1 A15 A16 48
CC27 166 95 LA15 2 47
0.1U XSAWRC VS33 LD3 LA14 A14 BYTE
167 AVSS_DA LD3 94 3 A13 GND 46
SVREF15 168 93 LD2 LA13 4 45 LA0
RR96 0 XSRFRPCTR LD2 LD1 LA12 A12 DQ15/A_1 LD7
(3) OPEN 169 XSTRAY LD1 92 5 A11 DQ7 44
170 91 LD0 LA11 6 43
SPINDLE RR21 6.8K AVDD3_DA LD0 LOE# LA10 A10 DQ14 LD6
(3) SPINDLE 171 XSSPINDLE LOE 90 7 A9 DQ6 42
FOCUS RR22 6.8K 172 89 WRLL# LA9 8 41
(3) FOCUS SLEGP XSFOCUS LWRLL LCS3# LA20 A8 DQ13

TMS28F400Axy
SLEGN 173 88 9 40 LD5
(3) SLEGN XSSLEGP LCS3 NC DQ5
RR24 5.1K 174 87 10 39
TRACK RR25 6.8K XSSLEGN VDD VCC20 WRLL# NC DQ12 LD4
(3) TRACK 175 XSTRACK VSS 86 11 W DQ4 38
DA RR26 6.8K 176 85 LCS2# RESET# 12 37
CC28 CC30 SFGIN XSTESTDA LCS2 RP VCC
177 XSFGIN LCS1 84 13 VPP DQ11 36
CC31 178 83 14 35 LD3
XSPHOI LCS0 DU/WP DQ3
Vibratto-II
AM5868 BA5954 0.015U 560P 0.015U RR27 33 XSCSJ 179 82 LA0 15 34
CC32 CC33 RR28 33 XSDATA SXCSJ LA0 LA1 LA19 NC DQ10 LD2
180 XSDATA LA1 81 16 NC DQ2 33
CC28 7.5nF 0.015U RR29 33 XSCLK 181 80 LA2 LA18 17 32
0.015U 560P DEFCT XSCLK LA2 LA8 A17 DQ9 LD1
182 XSDFCT VD33 79 18 A7 DQ1 31
SVREF15 SLDC 183 78 LA7 19 30
(3) SVREF15 XSLDC VS33 LA3 LA6 A6 DQ8 LD0
SPDON 184 77 20 29
SCSJ XSSPDON LA3 LA4 LA5 A5 DQ0 LOE#
(3) SCSJ 185 VD33 LA4 76 21 A4 G 28
SDATA 186 75 LA5 LA4 22 27
(3) SDATA SCLK VS33 LA5 LA6 LA3 A3 GND
(3) SCLK (3) INSW 187 XGPIO[9] LA6 74 23 A2 E 26
188 73 LA7 LA2 24 25 LA1
VCC CC35 CC36 CC37 (3) HOMESW XGPIO[8] LA7 LA8 A1 A0
(3) CLOSE 189 XGPIO[7] LA8 72
(3) OUTSW 190 XGPIO[6] VDD 71
33P 33P 33P 191 70 LCS2# GND
R52 R53 (3) DRVSB RS232_DET XGPIO[5] VSS LA9
SERIAL EEPROM
U3 1K 1K
192 XGPIO[4] LA9 69
LA10 LCS3#
(4) EAUX43 193 EAUX03 LA10 68
1 8 194 67 LA11
S0 VCC RFGND (4) EAUX42 EAUX02 LA11 LA12 U4
2 S1 WC 7 (4) EAUX41 195 EAUX01 LA12 66
3 6 R23 33 196 65 LA13 LA0 12 13 LD0
S2 SCL R65 33 (4) EAUX40 EAUX00 LA13 LA14 LA1 A0 D0 LD1
4 5 197 64 11 14

1
2
3
GND SDA R64 33 VSS LA14 LA15 LA2 A1 D1 LD2
(5) NN 198 VDD LA15 63 10 A2 D2 15
24C01A 199 62 LA3 9 17 LD3
AUX0 VD33 JP1 LA4 A3 D3 LD4
GND GND (5) SCART-ON R26 33 200 61 8 18
AUX1 VS33 LA16 LA5 A4 D4 LD5
201 AUX2/ HSYNC LA16 60 7 A5 D5 19
202 59 LA17 LA6 6 20 LD6
U5 VCC33 AUX3/ VSYNC LA17 LA18 LA7 A6 D6 LD7
203 AUX4 LA18 58 5 A7 D7 21
204 57 LA19 LA8 27
MA0 DB0 AUX5 LA19 LA20 LA9 A8
23 A0 DQ0 2 205 AUX6 LA20 56 26 A9

DCKE/DOE/TDMTSC
MA1 24 4 DB1 206 55 LA21 LA10 23
MA2 A1 DQ1 DB2 RESET# AUX7 LA21 DQM LA11 A10
25 5 207 54 25

DBANK0/ DRAS1

DBANK1/ DRAS2
MA3 A2 DQ2 DB3 RESET DQM LA12 A11
26 A3 DQ3 7 208 VS33 VD33 53 4 A12
MA4 29 8 DB4 LA13 28 VCC
MA5 A4 DQ4 DB5 LA14 A13
30 A5 DQ5 10 29 A14
MA6 31 11 DB6 LA15 3

DRAS0
DMA10

DMA11
A6 DQ6 A15

XOUT

DMA0
DMA1
DMA2
DMA3

DMA4
DMA5
DMA6
DMA7
DMA8
DMA9

DCAS

DSCK
MA7 DB7 LA16

DCS0
DCS1
DCLK
VD33

VD33

VD33

VD33

DB15
DB14

VD33
DB13
DB12
DB11
DB10
VS33

VS33

VS33

VS33

VS33
32 13 2 32

DWE
VDD
VSS

DB0
DB1
DB2

DB3
DB4
DB5
DB6
DB7

DB9
DB8
A7 DQ7 A16 VCC

XIN
MA8 33 42 DB8 LA17 30
MA9 A8 DQ8 DB9 WRLL# R32 OPEN A17
34 A9 DQ9 44 31 A18

33
33
33
33
MA10 DB10 LA18 R34 0 OHM

4.7K
22 45 1

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
MA11 A10 DQ10 DB11 R35 OPEN A19

1
2
3
4
5
6
7
8
9
35 A11 DQ11 47
48 DB12 LA19 R68 0 OHM
DQ12 DB13 LCS3#
DQ13 50 22 CE GND 16
DSCK R33 33 38 51 DB14 LOE# 24
CLK DQ14 DB15 INSTALL REMOVE TYPE OE
DQ15 53
DOE# R69 33 R34, R68 R32, R35 EPROM 27C040/080-90

R60
R56
R54
R55
R31
37 CKE GND
R32, R35 R34, R68 FLASH
1 U7
CS0# R58 33 VCC VCC
19 CS VCC 14
27 RESET# 1 2
VCC IR WRLL# RESET CLK/CE1 LA21

DMA10

DMA11
RAS0# R57 33

RAS0#
RAS1#

RAS2#
18 3 4

DMA0
DMA1
DMA2
DMA3

DMA4
DMA5
DMA6
DMA7
DMA8
DMA9

DSCK
XOUT

DWE#
CAS#

DOE#
DCLK
RAS WE ADDR/CE1

CS0#

DB15
DB14

DB13
DB12
DB11
DB10
VFD-CLK

DB0
DB1
DB2

DB3
DB4
DB5
DB6
DB7

DB9
DB8
3

XIN
CAS# R40 33 VCCQ VFD-CS VCC LA20 R48 0
17 CAS VCCQ 9
43 VFD-DATA GND ROM EMULATOR SOCKET
DWE# R41 33 VCCQ J2 LCS2# R45 OPEN
16 WE VCCQ 49
VCC IR IR
DQM R44 33 R42 100K FB4 R43 R19 100K VCC 1 +5V
15 DQML 3.3UH 0 U10 VFD-DATA 2 VFD-DATA
4-PIN EXTENSION FOR ROM EMULATOR INTERFACE
39 DQMH VSSQ 6 3

8
7
6
5

8
7
6
5

8
7
6
5
Y1 RESET# VFD-CLK VFD-CLK
VSSQ 12 RESET 1 RESET# (3) 4

10x4

10x4

10x4
RAS1# R46 33 20 46 2 R37 VFD-CS VFD-CS
RAS2# R47 33 BA0 VSSQ GND OPEN\0 5 GND
21 BA1 VSSQ 52 NC 3 6
27M EN 4
R36
EM-MARIN

RN1

RN2

RN3
28 5 HDR6-100
36
VSS
41 C13 C14 C15 VCC OPEN\0 RESET IC
NC VSS 1000PF AAT3521 SOT-23(5pin)

1
2
3
4

1
2
3
4

1
2
3
4
40 NC VSS 54 GND
27PF 27PF U11
1 U10 R36 R37 Title
GND AAT3521 OPEN 0
2
4Mx16 SDRAM (9ns) Vibratto-ll ES66X8

MA10
MA11
RESET V6300 0 OPEN

MA0
MA1
MA2
MA3

MA4
MA5
MA6
MA7

MA8
MA9
GND GND GND GND VCC 3
32/64MBIT SDRAM Size Document Number Rev
AAT3520 SOT-23(3pin) C 4250H-A1 A1
GND Date: Wednesday, March 03, 2004 Sheet 2 of 5
 RF50V CC38
DIN (2) RR52
0.1U
DIP (2)
CC39
CC40 CC41 0.1U (2) SVREF15
0.1U 470P 33 MVCC RR98 R
CC42 CC43 CC75 RR53
0.1U 470P 0.1U 12K RR88 1K
(2) SPDON
RFGND
RR97 R
RFOUT CC48 MGND
RFO (2)
820P
CC44 RF50V RR60 0 DD2
RF50V

(2) DRVSB 1
0.1U CC45 OPEN
0.01U UU3
RR34 12K(1%) BA5954FP/AM5868(OPEN)
RR47 33K FOCUS1 1 28 STBY RR48 22K
(2) FOCUS VINFC STBY
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

RFGND
UU2 RF33V RR56 1K RR49 47K CON2 2 27
(2) SLEGN CFCERR1 BIAS
RFDC

MEV
RFSIN
ATOP
ATON
AIN
AIP
VPA
RFAC

DIN
BYP

DIP
FNP
FNN
VNA

RX

CC50 CC70 CON1 3 26 TRACK1 RR51 33K

CFCERR2 VINTK TRACK (2)
0.1U 100P
OP2OUT RR112 OPEN RR109 0(OPEN) 4 25 RR54 47K
CC51 RR55 3.3K VINSL+ CTKERR1
RFGND
2200P 1 48 SCSJ OPEN RR113 OPEN RR116 0 5 24 CC72
DVDFRP SDEN SCSJ (2) VINSL- CTKERR2
CC52 2 47 SDATA 100P
DVDRFN SDATA SDATA (2) SPINDLE1 RR58
2200P 3 46 SCLK FOCUS- RR114 0 CC73 6 23 0
A2 SCLK SCLK (2) VOSL VINLD SPINDLE (2)
CC53 4 45 4700P
B2 V33 CC54 CLOSE-1 RR115 OPEN RR101 OPEN SVREF15
2200P 5 44 7 22
CC56 C2 LCP 0.047U MVCC LL6 FB VNFFC PREGND
6 D2 LCN 43
ES6603
2200P 7 42 TP23 MVCC 1 2 MVCC
CC57 CP MNTR CE MNTR
8 CN CE 41 CEI (2) MGND
120P 9 40 FE RR108 0 DD4 1 DD5 1 8 21
D FE FEI (2) S12V VCC PVCC2
10 39 TE OPEN OPEN
C TE TEI (2) DCLOAD- TRACK-
11 38 SBA RR107 0(OPEN) 9 20 RR102 0
B PI SBAD (2) PVCC1 VNFTK
12 37 CC77 + CC78
D A V25 SVREF15 DCLOAD+ RR106 0(OPEN) 0.1U
13 CD_D V125 36 10 PGND PGND 19
C 14 35 CC60 RF50V 100U/10V
B CD_C TPH 0.1U TP24 RR105 0 SLED- LOAD-/DCMO-
15 CD_B DFT 34 11 VOSL- VOLD- 18
A 16 33 DEFCT
CD_A LINK RR41 0 SLED+ LOAD+/DCMO+
SDEFCT (2) 12 VOSL+ VOLD+ 17
DVDPD

MGND
DVDLD

MEVO
CDPD

LDON

F 1(0805) FOCUS-1 TRACK-1

CDLD

MLPF
CD_E

LINK TP25 FOCUS- RR66 RR67 1(0805) TRACK-

CD_F

MIRR

MGND 13 16
VNB
VPB

VOFC- VOTK-
MIN
MP
MB

LINK RR68 1(0805) RR69 1(0805)

VC

E FOCUS+ 14 15 TRACK+

GND
GND
VOFC+ VOTK+
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

MVCC

29
30
MEVO
CC63
DD1 IN4148 0.22U RF50V RR103 0 RR104 OPEN
1 RFGND PVC CC65
DVDLD 160P CC66 MVCC
CDLD CC67 33000P MGND
DVDLDO LL13 FB (0805) CC64 DVDMDI 0.01U
1000P CDMDI
MIRR (2)
2

CC85 RR80
SLDC (2)
QQ1 1 RR43 1K
C 2SB1132 J12 R
CC68 1 HOMESW MVCC UU5 MVCC
3

RFGND 2 HOMESW (2)

RFGND 100U/16V
3 DCLOAD+
CC82 1 8
RR45 10 4 OUT1 GND
RF50V 5 LOAD-/DCMO- C DCLOAD-
RR46 10 2 7
6 LOAD+/DCMO+ RR78 VM OUT2
7 MGND
CC69 DCLOAD- 3 6
100U/16V 8 DCLOAD+ OPEN VCC VREF
9
3

SLED- CC80 4 5 CLOSE-1 RR89 1K

10 SLED+ FIN RIN CLOSE (2)
2SB1132 1 MGND
QQ2 RR50 5.1K 11 0.1U
INSW (2)
1000P 2.0MM
CDLDO LL10 FB (0805) CC71 RR81 0 BA6287F ROHM
2

OUTSW (2) OPEN

JJ2 MGND OPEN (2)
CC84 1 SLED+ MGND
RFGND 1 SLED-
1 2 2
C
DD3 IN4148 2.0MM
SBA TP30
RFGND SDATA SBAD TP31
SCSJ TP32 SDATA
RR11 56K SCLK SCSJ TP33
SVREF21 TP34 SCLK
(2) SVREF21
CC34 33P SVREF15 SVREF09 TP35
BEFR_OP (2)
SVREF15
UU4A
RF50V

4
TL3472
RR83 10K 2 -
1 ATR_OP (2)
LINK RR59 0 CC10 RR84 470K 3 +
0
CC6 CC9 MEVO RR72 R CC29
CN1 0.1U 100U/16V RR75 RR85

8
HOP-1200 PUH (JP24-0.5MM) R 0.47U
R
SVREF15
28
26

RFGND
GND
GND

24 TRACK-
TR- TRACK+
TR+ 23
22 FOCUS-
FO- FOCUS+ LOAD-/DCMO-
FO+ 21
20 DVDMDI
PD(MONITOR)
VCC 19
18 RR35 100 RR70
VR 10K
GND 17
16 DVDLDO
LD(DVD) CDLDO
LD(CD) 15
14 RR36 100
VR
GND(NC) 13
12 CDMDI
PD RR71
GND 11
10 RFOUT 1.5K
RFOUT C
C 9
8 B RR73 1M
B A OP2OUT MVCC
A 7
6 D
D RR37 3.3K F
F 5
4 RR39 3.3K E RR74
E 22K RF50V RR76
VCC 3
2 PVC RR40 R 4.7K
VS(VCC) SVREF21
(2)
GND

1 UU4B
GND

GND

8
CC62 OP2IN+ 5 +
MGND 7 MOCTL (2)
25
27

0.1U LOAD+/DCMO+ OP2IN- 6 -

RR77 TL3472
10K RR79

4
1.5K RF50V
RFGND RFGND
CC81
0.1U
RR82
22K Title
RFGND
ES6603 & Motor Drivers
Size Document Number Rev
C R4250H-A1 A1
MGND
Date: Wednesday, March 03, 2004 Sheet 3 of 5
 A B C D E
6-CHANNEL AUDIO OUT
+3.3V WOLFSON 6-CHANNEL AUDIODAC
B55
2-CHANNEL AUDIO OUT
10UF C272 WOLFSON 2-CHANNEL AUDIODAC VCCA
0.1UF VCCA
VCCA
GNDA U38 U31
1 20 CS4360 U32
(2) EAUX43 RST AMUTEC PCM1606
2 VL AUTA- 19 AOUT0L- (5) 1 VLS MUTC1 28
3 18 2 27 TSD0 1 20 MCLK
(2) TSD0 SDATA AUTA+ AOUT0L+ (5) (2) TSD0 SDIN1 AOUTA1 AOUT0R- (5) TSD1 DATA1 SCKI TBCK
4 (2) TBCK 4 SCLK VA 17 (2) TSD1 3 SDIN2 AOUTB1 26 AOUT0L- (5) 2 DATA2 BCK 19 4
5 16 4 25 TSD2 3 18 TWS
(2) TWS LRCK GND (2) TSD2 SDIN3 MUTC2 EAUX40 DATA3 LRCK EAUX43
(2) MCLK 6 MCLK AOUTB+ 15 AOUT0R+ (5) (2) TBCK 5 SCLK AOUTA2 24 AOUT1R- (5) 4 FMT1 DEMP1 17
7 14 6 23 EAUX41 5 16 EAUX42
M3 AOUTB- AOUT0R- (5) (2) TWS LRCK AOUTB2 AOUT1L- (5) FMT2 DEMP0
(2) EAUX42 8 M2 BMUTEC 13 (2) MCLK 7 MCLK VA 22 6 ZEROA VCC 15
9 12 8 21 7 14 U1
(2) EAUX41 M1 CMOUT VD GND AGND VCOM
(2) EAUX40 10 M0 FILT+ 11 9 GND AOUTA3 20 AOUT2R- (5) 8 VOUT5 VOUT4 13 AOUT1R- (5)
(2) EAUX43 10 RST AOUTB3 19 AOUT2L- (5) 9 VOUT6 VOUT3 12 AOUT1L- (5)
(2) EAUX42 11 DIF1 MUTEC3 18 10 VOUT1 VOUT2 11 AOUT0R- (5)
GNDA CS4392 12 17 U1
U1 (2) EAUX41 DIF0 VQ U2
(2) EAUX40 13 M1 FILT+ 16 AOUT0L- (5)
U2 14 15
C258 C259 VLC M2 AOUT2R- (5)
C273 10UF 10UF C274 AOUT2L- (5)
GNDA
C260 B50
0.1UF 0.1UF 0.1UF
10UF
GNDA GNDA GNDA
GNDA GNDA GNDA GNDA GNDA GNDA
T1 T2 T3 T4
TP TP TP TP
GNDA
VCCA GND GND RFGND GND
C256
U30
CS4340 0.1UF
(2) EAUX43 1 RST MUTEC 16
3 R71 33 2 15 3
(2) TSD0 SDATA AOUTL AOUT0L- (5)
(2) TBCK 3 SCLK/DEM1 VCCA 14
(2) TWS 4 LRCK VSS 13
(2) MCLK 5 MCLK AOUTR 12 AOUT0R- (5)
(2) EAUX42 6 DIF1 REF-GND 11
7 10 U1
(2) EAUX41 DIF0 VQ U2
(2) EAUX40 8 DEM0 FILT+ 9
GNDA
VCCA +3.3V
1 1
B51 D23 D24
10UF IN4148 IN4148
3.3V REGUALTOR
VCC VCC33
Q2 OPEN FRONT
3 IN OUT 2
VCC33 RF50V +5V

ADJ
ES66x8 LL2
FERB C23 R38
2
2 OPEN OPEN EZ1085 2
(EZ1085)

1
(10UF) 1%
CC7 (412 OHM)
B15 B16 B17 B18 B19 B20 B21 B22 B31 B33 + 100/10 CC11
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF 10UF 0.1 B2 ADJ INP
GND OPEN
R39 (100UF) OUT
No need to install OPEN
RFGND RFGND EZ1085 circuitry if 1%
J12 provide +3.3V (681 OHM)
LL1
B23 B24 B25 B28 B29 B30 B32 FERB GND GND
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF PLL33V 2 VCC33
LL7 2 OPEN LL8 2 OPEN
LL5
FERB
RF33V 2 VCC33 GNDV GND RFGND GND
GND LL15
FERB LL3 2 OPEN LL9 2 OPEN
VCC33 SDRAM VCC 2
VCC33V VCC33
MGND GND GNDA GND
U9
VCC20 AMS1117
2 OUT IN 3 VCC33
0.1UF
4 OUT

ADJ
B34 B35 B36 B37 B38 B40 B43 B41 B62 B60 B61
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF 0.1UF 0.1UF 10UF 0.1UF +5V +12V -12V S12V VCC33
R67

1
412(1%)
MVCC LL14 2 FERB
8
GND 7
VCC20 LL11 2 FERB
TYP 2.5V ( 2.3V -- 2.7V ) VCCA 6
GND 5
24C01 R66 C16 LL12 2 FERB
VCC 250(1%) 0.1UF(OPEN) VCC 4
1 1
3
B3 B4 2
CC125 CC126 CC127 CC128 CC129 CC130 1
220UF 220UF
0.1 0.1 0.1 0.1 0.1 + 100U B1 2.54MM
GND 220UF GND JS3
B45 GND GNDA
0.1UF
GND
GND
GND Title
ESS CONFIDENTIAL MISC
The information has been checked and is believed to be reliable. However, no responsibility is assumed for inaccuracies. Circuit diagrams are provided as a means of illustrating typical applications; consequently complete information for construction purposes is not necessarily given. ESS reserves the right to make changes at any time in order to improve the design. Size Document Number Rev
C 4250H-A1 A1
Date: Wednesday, March 03, 2004 Sheet 4 of 5
A B C D E
 A B C D E

+12V VCCV VCCV

1
U25-1

8
C263 OPA2134UA R421 R430
10UF R331 R337 2K2 2K2 R441
V+

3
10K 680 C220 75
(4) AOUT2R+ 3
Rs_OUT R157 RS Q36 Q39 G-OUT
1 1 (2) VDAC 1 2 (2) YDAC 1 2 1
2 10 OHM BC848B BC848B

1
R353 C275 C297 C300
V- 10UF LUMA-OUT
100uF/25 CVBS-OUT 100uF/25

1
10K 680PF 1 1
R160 C224

1
C276 R424 R434

4
100K 22PF
3300PF R423 R427 75 R433 R436 75
-12V 1K8 75 1K8 75
C178
4
R12 R25 680PF 4

3
(4) AOUT2R- 1 1
QUIET0 1 R163 2 Q23
10K C189 680 1 R154 2SC3327 GNDV GNDV
470
C261 open GNDV GNDV
10UF 10K +12V

1
VCCV
U25-2

1
VCCV

1
C262 R397 OPA2134UA P1

1
10UF R338 680 R438
10K 1 5 V+ C214 R30 R422 2K2
(4) AOUT1R+

1
3
7 Ls_OUT 1 LS 2K2 6 6

3
6 1 2 Q40
10 OHM (2) CDAC

1
R339 C277 1 2 Q37 BC848B CVBS-OUT 5
V- 10UF (2) FDAC 5
BC848B C301
10K 680PF R150 C217 C298 100uF/25 LUMA-OUT
1 R-OUT

1
4 4
C278 100uF/25 CHROMA-OUT

1
100K 22PF 1

1
3300PF R445 CHROMA-OUT 3 3

1
-12V R426 R437 R444 75

2
R425 R428 75 1K8 75

3
C279 R175 R186 C211 R153 1K8 75
QUIET0 Q20

2
(4) AOUT1R- 1 1 1 2
2SC3327
10K 680 R195 470
10UF 680PF
C235

1
1
open GNDV GNDV
10K +12V GNDV GNDV GNDV
U24-1
R399
8
OPA2134UA (2) SCART-ON
C281 R398 680 VCCV J1
V+ 10K

1
C221 VCC CVBS-OUT
(4) AOUT1L+ 1 1 3 1
LFE_OUT R158 SUB R402 +5VA R-OUT
1 1 2
10K 2 R429 G-OUT
10UF 10 OHM 3

1
R400 C282 2K2 Q30 B-OUT

21
V- 10UF 4

3
2 Q31 R401 8550
10K 680PF R161 C225 Q38 +5VA 2N3904 10K 5
(2) UDAC 1 2 1 3 6
C283 FB3 FB
4

3 100K 22PF BC848B 1 3 1 7

3
3300PF C299
1

-12V 100uF/25 B-OUT C232 FL 8

1
1 9
FR

2
0.1UF GND 10

1
C284 R196 R197 C172 R432 Q32 Q33
11

3
1 1 R431 R435 75 +12V 8550 8550 R403
(4) AOUT1L- R164
QUIET0 1 2 Q24 1K8 75 1 3 1 3 330 1
11K C177 680 R13 680PF 2SC3327 CON24
10UF 470 R406
open 1 GND

1
10K

1
1

3
10K +12V R408 R404 R405

2
U24-2 GNDV GNDV 10K 1 2 Q35 10K 100K
(2) NN 2N3904 D25
8

R410 OPA2134UA IN4148 R420

C285 R409 680

1
1
1 1 5 V+ C215 R148 1
(4) AOUT2L+ +12V

1
7 C_OUT 1 CC GND 10K

1
10K C286 6 D5 1 GND
10UF 10 OHM +12V
1

3
R412 680PF R165 IN4148 C226 R407
V- 10UF
IN4148 6.8K R411 R413 Q34 2 1 10K
10K 470uF SCART-ON (2)
R151 C218 D6 R167 820 1.2K 2N3904

1
C287
4

2.2K

1
100K 22PF
3300PF
1

1
1 1 2 Q25
-12V 8550
+5VA
C288 R14 R15 680 C227 GND GND

3
3

1 1 C180 680PF 220uF/25 QUIET0

(4) AOUT2L- QUIET0 1 R155

1
2 Q21 R170 1K
10K R16 10K 2SC3327 R171
10UF 470 1 1 2 Q26
C181 1 +5VA 8550

1
1

open 1K R174
R173

3
1 1
-12V
OPEN D7

3
+12V 100K U27A
R176 IN4148
12 Q27
U23-1 VCC 1 2
2N3904
470
8

2
R415 OPA2134UA 2

1
C289 R414 680 7404
1 1 3 V+ C219 R156 R166
(4) AOUT0R+ FR
1 1 10M
10K 2 U27B U27C U27D U27E
10UF 10 OHM
1

R416 C290 C228

C291 680PF V- 10UF (2) SPDIF 3 4 5 6 9 8 11 10
10K 3300PF R159 C223
0.1UF
4

100K 22PF
1

7404 7404 7404 7404

-12V
R21 1
C292 R20 680 C184 U27F
3

1 1 R172 1M
(4) AOUT0R- R162
QUIET0 1 2 Q22 P3 13 12
10K C185 R22 680PF 2SC3327
10UF 470
1 10K RCA CONN 6 P9
open +12V RCA CONN
1

7404
4 R178 C230
1 1
3
330 OHM 0.1UF
+12V
C236 C128 C191 C169 C170 R179

2
U23-2
0.1UF 0.1UF 0.1UF 10UF 10UF 91 OHM
8

OPA2134UA
C293 R417 R418680 +5VA

1
GND
1 1 5 V+ C213 R29
(4) AOUT0L+ FL
7 1
10K 6 GND
10UF 10 OHM
1

R419 C294 L21

V- 10UF
P2
10K C295 680PF R149 C216 -12V 47UH
GND 3
3300PF
4

100K 22PF
1

VCC 2
-12V
1

2
3

5
6
7

8
9
VIN 1 1
1 C296 R24 R27 C188 1
3

1 1 680 R152 C173 C174 C193 C175 C176 R187

(4) AOUT0L-

1
QUIET0 1 2 Q13 0.1UF 0.1UF 0.1UF 10UF 10UF MOFT3C2 68 OHM
10K C190 R28 2SC3327 C280
10UF 680PF 470
1 10K 0.1UF
open
1

2
SUB
CC
RS
FR

LS
FL

GND GND

Title
OUTPUT
Size Document Number Rev
C 4250H-A1 A1

Date: Wednesday, March 03, 2004 Sheet 5 of 5

A B C D E
COPYRIGHT ã 2004 BY SHARP CORPORATION

ALL RIGHT RESERVED.

No part of this publication may be reproduced,

stored in aretrieval system, or transmitted in
any form or by any means, electronic, mechanical,
photocopying, recording, or otherwise, without
prior written permission of the publisher.

SHARP CORPORATION
AV Systems Group
Quality & Reliability Control Center
Yaita, Tochigi 329-2193, Japan
28