DATA SHEET
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74HC/HCT74
Dual D-type flip-flop with set and
reset; positive-edge trigger
Product specification 1998 Feb 23
Supersedes data of September 1993
File under Integrated Circuits, IC06
Philips Semiconductors Product specification
FEATURES The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
• Output capability: standard
on the data input is transferred to the Q output on the
• ICC category: flip-flops LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
GENERAL DESCRIPTION clock transition for predictable operation.
The 74HC/HCT74 are high-speed Si-gate CMOS devices Schmitt-trigger action in the clock input makes the circuit
and are pin compatible with low power Schottky TTL highly tolerant to slower clock rise and fall times.
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT74 are dual positive-edge triggered, D-type
flip-flops with individual data (D) inputs, clock (CP) inputs,
set (SD) and reset (RD) inputs; also complementary Q and
Q outputs.
TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V
nCP to nQ, nQ 14 15 ns
nSD to nQ, nQ 15 18 ns
nRD to nQ, nQ 16 18 ns
fmax maximum clock frequency 76 59 MHz
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per flip-flop notes 1 and 2 24 29 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
1998 Feb 23 2
Philips Semiconductors Product specification
ORDERING INFORMATION
TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
74HC(T)74N DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC(T)74D SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HCT74DB SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
74HCT74PW TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
PIN DESCRIPTION
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
1998 Feb 23 3
Philips Semiconductors Product specification
FUNCTION TABLE
INPUTS OUTPUTS
SD RD CP D Q Q
L H X X H L
H L X X L H
L L X X H H
INPUTS OUTPUTS
SD RD CP D Qn+1 Qn+1
H H ↑ L L H
H H ↑ H H L
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH CP transition
Qn+1 = state after the next LOW-to-HIGH CP transition
Fig.4 Functional diagram.
1998 Feb 23 4
Philips Semiconductors Product specification
AC CHARACTERISTICS
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
1998 Feb 23 5
Philips Semiconductors Product specification
1998 Feb 23 6
Philips Semiconductors Product specification
AC WAVEFORMS
Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD
to nCP set-up, the nCP to nD hold times, the output transition times and the maximum clock pulse
frequency.
trem
VM(1)
nSD INPUT
trem
tW tW
VM(1)
nRD INPUT
tPLH tPHL
nQ OUTPUT VM(1)
tPHL tPLH
MGL350
Fig.7 Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set
and reset pulse widths and the nRD, nSD to nCP removal time.
1998 Feb 23 7
Philips Semiconductors Product specification
PACKAGE OUTLINES
D ME
seating plane
A2 A
L A1
c
Z e w M
b1
(e 1)
b
14 8 MH
pin 1 index
E
1 7
0 5 10 mm
scale
UNIT
A A1 A2
b b1 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.73 0.53 0.36 19.50 6.48 3.60 8.25 10.0
mm 4.2 0.51 3.2 2.54 7.62 0.254 2.2
1.13 0.38 0.23 18.55 6.20 3.05 7.80 8.3
0.068 0.021 0.014 0.77 0.26 0.14 0.32 0.39
inches 0.17 0.020 0.13 0.10 0.30 0.01 0.087
0.044 0.015 0.009 0.73 0.24 0.12 0.31 0.33
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
92-11-17
SOT27-1 050G04 MO-001AA
95-03-11
1998 Feb 23 8
Philips Semiconductors Product specification
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
D E A
X
y HE v M A
14 8
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 7 L
e w M detail X
bp
0 2.5 5 mm
scale
0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 o
0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8
0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0o
inches 0.069 0.01 0.050 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
95-01-23
SOT108-1 076E06S MS-012AB
97-05-22
1998 Feb 23 9
Philips Semiconductors Product specification
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
D E A
X
c
y HE v M A
14 8
Q
A2 A
A1 (A 3)
pin 1 index
θ
Lp
L
1 7 detail X
w M
e bp
0 2.5 5 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
95-02-04
SOT337-1 MO-150AB
96-01-18
1998 Feb 23 10
Philips Semiconductors Product specification
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
D E A
X
y HE v M A
14 8
Q
A2 (A 3)
A
A1
pin 1 index
θ
Lp
L
1 7
detail X
w M
e bp
0 2.5 5 mm
scale
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
94-07-12
SOT402-1 MO-153
95-04-04
1998 Feb 23 11
Philips Semiconductors Product specification
1998 Feb 23 12
Philips Semiconductors Product specification
DEFINITIONS
1998 Feb 23 13
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