APPLICATION NOTE
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VCC
BAND-
PASS LOW- LOW-
FILTER ÷ PASS ÷ PASS ADC
IN FILTER FILTER
AUTOMATIC
DETECT
15808-001
Rev. A | Page 1 of 6
AN-1463 Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1 Limitations and Trade-Offs..........................................................4
Application Problem ........................................................................ 1 Conclusion .....................................................................................4
Revision History ............................................................................... 2
Application Solution ........................................................................ 3
REVISION HISTORY
5/2017—v.00.1103 to Rev. A Changes to Introduction Section ....................................................1
Updated Format ................................................................... Universal Changes to Limitations and Trade-Offs Section, Figure 7
Changed HMC364S8G to HMC365S8G and Caption, and Table 1 .........................................................................4
R to R5 ............................................................................. Throughout
Changed General Description Section to Introduction Section ...... 1
Rev. A | Page 2 of 6
Application Note AN-1463
APPLICATION SOLUTION
A typical divider circuit consists of three main components: a
differential amplifier at the input, one or more digital divider
networks, and an output differential amplifier (see Figure 2).
The input differential amplifier creates a digital like output that,
depending on the voltage levels, triggers gates in the digital
divider networks. The output differential amplifier receives the
digital output and amplifies it accordingly.
VCC PACKAGE
R1 R2 R3 R4
15808-004
IN OUT
÷
IN OUT
15808-002
C1
Figure 4. HMC362S8G Evaluation Board with Offset Resistance
Figure 2. Block Diagram of Typical Frequency Divider Figure 5 and Figure 6 show plots of the spectrum, at the output
The input/output differential amplifiers have pull-up resistors, of the HMC362S8G divider, from dc to 20 GHz. Figure 5 shows
R1 to R4 (on chip), connected to VCC. Capacitor C1 is external the output spectrum when no RF is applied and with no offset
and ties the complementary input to RF ground for single- resistor at the complementary input. The multiple tone output is
ended input operation. Because the resistances of R1 and R2 are caused by the false triggering of the digital divider. Figure 6
equal, the difference in potential across the input terminals is shows the spectrum under the same conditions but with an
zero when no RF is present. When the amplifier is in this state, offset resistor at the complementary input. The divider produces
any noise present at the input is amplified and causes the digital no output over the temperature range of −40°C to +85°C.
divider to false trigger. However, when a nominal value of RF 0
15808-005
R1 R2 R3 R4 0 5 10 15 20
IN OUT FREQUENCY (GHz)
÷
IN OUT
Figure 5. Divider Output with No Input and No Offset Resistance
15808-003
C1 R5
0
Figure 3. Block Diagram of Typical Frequency Divider with Offset Voltage
Compensation
–20
Figure 3 shows a schematic of a typical divider with Offset
Resistor R5 placed at the complementary input port. The value of
POWER (dBm)
Rev. A | Page 3 of 6
AN-1463 Application Note
The majority of Analog Devices dividers have differential When using an offset resistor, the minimum input power
inputs/outputs. However, three dividers are designed with required for proper operation is higher, as outlined by the lower
single-ended inputs/outputs. The exceptions are the HMC432, boundary of the light gray shaded area. The upper boundary of
HMC433, and HMC434. Although these devices have single- the light gray shaded area is the maximum allowable input power.
ended inputs, they still require offset resistances because, For the divider to produce output, RF power must be applied at
internally, the inputs are differential but have been terminated the input. Without RF power, the divider produces no output;
for single-ended operation. however, there is still a region where the divider can produce a
LIMITATIONS AND TRADE-OFFS false trigger. This area is marked by the dark gray shaded area.
The input sensitivity of the divider is affected by the offset In this region, the voltage differential across the input goes to
voltage created by the offset resistor. Figure 7 shows the input zero (or close to it) due to the increased input signal. With
sensitivity of the HMC362S8G with and without the offset increasing input power, the voltage differential across the input
resistor. The solid lines outline the upper and lower range of the is reestablished and the divider operates normally.
input sensitivity of the divider with no offset resistor. CONCLUSION
20
Analog Devices dividers provide exceptional reliability and
10
performance in a variety of systems. In the majority of systems,
these dividers require no special biasing. However, there are
0 systems in which the dividers may false trigger, which normally
INPUT POWER (dBm)
0 2 4 6 8 10 12 14 16
INPUT FREQUENCY (GHz)
these dividers over the temperature range of −40°C to +85°C.
The input power sensitivity plots for these dividers, with and
Figure 7. HMC362S8G Input Sensitivity With and Without Offset Resistor
without offset resistors, are shown in Figure 8 to Figure 16.
Rev. A | Page 4 of 6
Application Note AN-1463
Input Power Sensitivity Plots
20 20
10 10
0 0 OPERATING WINDOW
INPUT POWER (dBm)
–20 –20
–30 –30
–50 –50
15808-008
15808-011
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
INPUT FREQUENCY (GHz) INPUT FREQUENCY (GHz)
Figure 8. HMC361S8G Input Sensitivity and Operation, R5 = 40 kΩ Figure 11. HMC365S8G Input Sensitivity and Operation, R5 = 60 kΩ
20 20
10 10
OPERATING WINDOW
0 0 OPERATING WINDOW
INPUT POWER (dBm)
–20 –20
–30 –30
REGION OF FALSE TRIGGERING
REGION OF FALSE TRIGGERING
–40 –40
–50 –50
15808-009
15808-012
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10
INPUT FREQUENCY (GHz) INPUT FREQUENCY (GHz)
Figure 9. HMC362S8G Input Sensitivity and Operation, R5 = 40 kΩ Figure 12. HMC432 Input Sensitivity and Operation, R5 = 4 kΩ
20 20
10 10
–20 –20
–50 –50
15808-010
15808-013
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10
INPUT FREQUENCY (GHz) INPUT FREQUENCY (GHz)
Figure 10. HMC363S8G Input Sensitivity and Operation, R5 = 60 kΩ Figure 13. HMC433 Input Sensitivity and Operation, R5 = 4 kΩ
Rev. A | Page 5 of 6
AN-1463 Application Note
20 20
10
0
OPERATING WINDOW OPERATING WINDOW
OPERATING WINDOW
0
INPUT POWER (dBm)
–20
–10
–20
–40 REGION OF FALSE TRIGGERING
–30
REGION OF FALSE TRIGGERING
–60
–40
–50 –80
15808-014
15808-016
0 2 4 6 8 10 0 1 2 3 4 5 6 7 8
INPUT FREQUENCY (GHz) INPUT FREQUENCY (GHz)
Figure 14. HMC434 Input Sensitivity and Operation, R5 = 4 kΩ Figure 16. HMC438 Input Sensitivity and Operation, R5 = None
20
0
OPERATING WINDOW
INPUT POWER (dBm)
–20
–60
–80
15808-015
0 1 2 3 4 5 6 7 8
INPUT FREQUENCY (GHz)
Rev. A | Page 6 of 6