High speed fault injection tool (FITO) implemented with Verilog HDL

on FPGA for testing Fault tolerance designs

Existing method

Evaluating the sensitivity to soft-errors of integrated circuits and systems became

a main issue especially if they are intended to operate in space or at high altitudes.

Proposed Method

1. Fault Injection will be done by applying some extra gates and wires to the original design
description and modifying the target Verilog Fault injection is mainly used to test and
evaluate the fault-tolerance based designs.
2. There are fundamentally two types of fault injection methods; they are hardware-based
fault injection and software-based fault injection. Both have their own limitations and
advantages.

Advantages

(1) High controllability and observability

(2) High speed fault injection experiments with target system running at full speed
(3) Capability to inject permanent and transient faults.
(4) Minimum time and area overhead into a target system.

Application of fault injection

Fault injection can take many forms. In the testing of operating systems for example, fault
injection is often performed by a driver (kernel-mode software) that intercepts system calls (calls
into the kernel) and randomly returning a failure for some of the calls. This type of fault injection
is useful for testing low level user mode software. For higher level software, various methods
inject faults. In managed code, it is common to use instrumentation. Although fault injection can
be undertaken by hand a number of fault injection tools exist to automate the process of fault
injection.
HARDWARE AND SOFTWARE TOOLS
 Hardware - Xilinx Spartan 3E Family FPGA
board

 Simulation software - Model sim Xilinx Edition

 Synthesis, P&R - Xilinx ISE

FPGA Specifications

 Device - xc3s500E

 Package - FG320

 Speed - -4

Abstract

Fault injection is mainly used to test and evaluate the fault-tolerance based designs. In current
VLSI technology fault injection has become a popular technique for experimentally determining
dependability parameters of a system, such as fault latency, fault propagation and fault coverage.
There are fundamentally two types of fault injection methods; they are hardware-based fault
injection and software-based fault injection. Both have their own limitations and advantages. The
FPGA synthesizable fault injection model can give reasonable solution with high speed testing
platform and also allows good controllability and observability. Even though a considerable
progress has been made in research part of the fault injection algorithms, there is a little
implementation is done which could be of great interest to VLSI industry.
In this project an FPGA-based fault injection tool (FITO) that supports several synthesizable
fault models for dependability analysis of digital systems modeled by Verilog HDL. Aim is to
build real time fault injection mechanism with good controllability and observability. Fault
injection will be done by applying some extra gates and wires to the original design description
and modifying the target Verilog model of the target system. The design will be validated with
state machine based example and applying different types of faults. Analysis will be carried out
studying the controllability and observability of the proposed scheme. Comparison will be
carried out to estimate the speed wise improvement with respect to software simulation based
fault injection method.
. Modelsim Xilinx Edition (MXE) will be used for functional simulation and Xilinx ISE
tools will be used for synthesis and performance analysis. Spartan-3E FPGA board will be used
for on chip verification of the results with Chipscope software running on PC. The possible
applications of the developed core and future scope for extension will also be documented.

Introduction
The fault injection is a technique of Fault Tolerant Systems (FTSs) validation which
is being increasingly consolidated and applied in a wide range of fields, and several
automatic tools have been designed [1]. The fault injection technique is defined in the
following way [2]:
Fault injection is the validation technique of the Dependability of Fault Tolerant
Systems which consists in the accomplishment of controlled experiments where the
observation of the system’s behaviour in presence of faults is induced explicitly by the
voluntary introduction (injection) of faults to the system.
The fault injection in the hardware of a system can be implemented within three
main techniques:
1. Physical fault injection: It is accomplished at physical level, disturbing the
hardware with parameters of the environment (heavy ions radiation,
electromagnetic interference, etc.) or modifying the value of the pins of the
integrated circuits.
2. Software Implemented Fault injection (SWIFI): The objective of this technique,
also called Fault Emulation, consists of reproducing at information level the errors
that would have been produced upon occurring faults in the hardware. It is based
on different practical types of injection, such as the modification of the memory
data, or the mutation of the application software or the lowest service layers (at
operating system level, for example).
3. Simulated fault injection: In this technique, the system under test is simulated in
other computer system. The faults are induced altering the logical values during the
simulation.