H4A71110 Vol-1 All

DOPPLER VOR
VRB-52D
TYPE SERIES A71110
HANDBOOK H4A71110
ISSUE 16 22 MAY 96
Interscan Navigation Systems

Pty Ltd
ABN 28 091 922 315
H4A71110 REVISION RECORD
REVISION No. AUTHORITY DATE INSERTED INITIALS

1 ECO 903306 25/9/96 RR
2 ECO 903829 4/2/97 RR
3 ECO 903874 8/4/97 RR
4 ECO E1296 18/4/97 RR
5 ECO E1369 10/10/97 RR
6 ECO E1350 17/10/97 RR
REVISIONS ABOVE ARE INCLUDED IN HANDBOOK TEXT.
REVISIONS BELOW ARE DETAILED IN REVISION ADVICE PAGES.
7 ECO E1376 3/3/98
8 ECO E1509 3/3/98
9 ECO E1510 3/3/98
10 ECO E1683 13/5/98
11 ECO E1724 13/5/98
12 ECO E1841 4/8/98
13 ECO E1681 10/8/98
14 ECO E1871 24/8/98
15 ECO E1873 24/8/98
16 ECO E1927 10/11/98
17
© Copyright Interscan Navigation Systems Pty Ltd

This publication is copyright and all rights pertaining to it are reserved.
No part may be reproduced by any process without written permission.
H4A71110_RevisionRecord.doc
REVISION ADVICE
HANDBOOK : H4A71110
DOPPLER VOR VRB-52D
REVISION : 12
REVISION DATE : 4 Aug 98
REVISION AUTHORITY : ECO E1841
DETAILS OF REVISION :
Table F-38
Change table heading ‘QTY’ to ‘QTY/CODE’.
Item A3 (Isolator):
Change to circuit reference ‘A6’
In QTY/CODE column, insert code number ‘1043520L’
Change SUPPLIER/REF to ‘DEL IS113-3AN-20’.
Item A6 (Low Pass Filter):

Change to circuit reference ‘A7’
In QTY/CODE column, insert code number ‘1036200E’
Change SUPPLIER/REF to ‘TEL TLP125-3AB1’.
Drawing 71126-3-32
Change identity of COAX CABLE ASSY 71126-4-26 between DRIVER 1A71157

and ISOLATOR (WIDE BAND) to read
‘(71126-4-26) OR (71126-3-41)’
Change identity of COAX CABLE ASSY 71126-4-26 between ISOLATOR (WIDE BAND)
and FILTER (LOW PASS) to read
‘(71126-4-23) OR (71126-3-42)’
These changes are incorporated in Drawing 71126-3-32 Revision 01.
END
H4A71110_RevisionAdvice12.DOC
REVISION ADVICE
HANDBOOK : H4A71110
DOPPLER VOR VRB-52D
REVISION : 13
REVISION DATE : 10 Aug 98
REVISION AUTHORITY : ECO E1681
DETAILS OF REVISION :
Table F-49
Add capacitors C51-C54 to code 1031094E.
Figure I-8
Replace the existing detail with that shown following.
Drawing 71138-2-25
Against the FET labelled ‘V3 3N204’ at grid D2, show capacitors C51, C52 connected in
parallel from the case of the FET to 0V point.
Against the FET labelled ‘V4 3N204’ at grid D4, show capacitors C53, C54 connected in
parallel from the case of the FET to 0V point.
These changes are incorporated in Drawing 71138-2-25 Revision 02.
END
H4A71110_RevisionAdvice13.DOC
H4A71110
HANDBOOK H4A71110
VOLUME ARRANGEMENT
VOLUME 1 SECTION 1 BRIEF SPECIFICATION

2 TECHNICAL DESCRIPTION
VOLUME 2 3 ALIGNMENT AND ADJUSTMENT

3.1 DEPOT TESTING PROCEDURES
3.2 TESTING LINE REPLACABLE UNITS
3.3 PRE-INSTALLATION CHECK
3.4 BEACON ALIGNMENT
3.5 OTHER ALIGNMENT PROCEDURES
4 MAINTENANCE PROCEDURES
VOLUME 3 APPENDIX A OPERATING INSTRUCTIONS

B PHYSICAL DIMENSIONS AND MASSES
C POWER AND REMOTE CONTROL
D SYSTEM INSTALLATION
VOLUME 4 APPENDIX E TEST EQUIPMENT

F COMPONENTS SCHEDULE
G COMPONENT SOURCING
I COMPONENT LAYOUT DIAGRAMS
J AC POWER SUPPLY 3A71130
K FIRMWARE
L CRYSTAL SPECIFICATIONS AND TESTS
VOLUME 5 DRAWINGS
VOLUME 6 APPENDIX H DATA SHEETS
VOLUME 6 IS OPTIONAL AND IS SUPPLIED

ONLY IF SPECIFICALLY ORDERED.
1
H4A71110
WARNINGS
The warning information Included below should be made
known to all personnel engaged in operation and
maintenance of the DVOR VRB-52D equipment
RADIATION EXPOSURE HAZARD

The level of radiation from the DVOR VRB-52D is sufficiently low that normal service,
maintenance and repair procedures represent no hazard to personnel.
ELECTRIC SHOCK HAZARD

Maintenance or other tasks which require access to the equipment during operation
should be performed only by suitable qualified personnel who are aware of the
precautions to be taken when working on equipment in which hazardous operating
voltages may be present.
All personnel should be conversant with emergency cardiopulmonary resuscitation
procedures. An illustrated procedure authorised by the National Heart Foundation of
Australia is included in this manual for reference.
TOXIC SUBSTANCES
Beryllium Oxide
Beryllium oxide in the sintered (ceramic) form is safe to handle whilst it remains intact in
its original manufactured form, but if it is broken or pulverised the resulting dust particles
are highly toxic.
The sintered form of beryllium oxide is a component in the manufacture of thermally
conductive washers as used in transistor heat sink applications, and in the manufacture
of chip resistors. These SHOULD NOT be broken, filed, drilled, sandpapered, or
abraded in any way.
The sintered form of beryllium oxide is also used in the manufacture of high-frequency
(VHF and UHF) transistors; these can usually be identified by a white ceramic-looking
circumferential band. These transistors SHOULD NOT be opened 'in any circumstances.
Beryllium oxide is also used as a greasy-looking paste inside certain types of metal can
transistors; these SHOULD NOT be opened in any circumstances.
Because of the difficulty in identifying those transistors which may contain beryllium
oxide, NO TRANSISTORS SHOULD EVER BE CUT OPEN FOR INTERNAL
INSPECTION. Also, used or replaced transistors should be disposed of in a manner
consistent with the potential hazard that they may present.
Beryllium oxide should not be confused with beryllium copper, which is safe to handle.
2
H4A71110
Polytetrafluoroethylene (PTFE)
Thermal degradation of PTFE will commence at temperatures above 200 degrees
Celsius; toxic vapours will be evolved at such temperatures.
This characteristics of PTFE must be taken into account when repair or replacement of
components may involve heating of PTFE. Adequate ventilation should be provided in
the event that processes (such as soldering) may submit PTFE to temperatures above
200 degrees Celsius.
LIGHTNING PROTECTION
The design of the DVOR VRB-52D minimises hazard from lightning strike effect up to
the order of a few hundred volts. In installations where external wiring is connected to
the equipment and extends over significant distances, suitable protection devices should
be fitted at the point where the external wiring enters the equipment shelter.
CAUTION
The precautionary Information included below should be
made known to all personnel engaged in maintenance of
the DVOR VRB-52D equipment
STATIC-SENSITIVE DEVICES
All metal oxide semiconductor (MOS) devices and the FET family of transistors can
potentially be damaged by electrostatic discharge voltages occurring during handling, or
during testing or installation into a circuit board.
Some types of devices incorporate in-built circuitry to provide protection against the
effects of electrostatic discharge voltages. Other types do not, and are potentially
susceptible to damage. These latter types are referred to as static-sensitive devices
(SSDs).
The DVOR VRB-52D equipment contains SSDs. Personnel involved in testing and repair
of the equipment should be aware of the causes and effects of potential damage to
SSDs, and of the proper practices to be observed in order to obviate such damage.
3
H4A71110
ACRONYMS AND ABBREVIATIONS

The major acronyms and abbreviations used throughout this handbook, and their
meanings, are listed below. Unless shown otherwise these apply to indicate both noun
and verb forms, and to singular and plural cases. Examples:
AM may indicate either amplitude modulation
or amplitude modulated
LED may indicate either light emitting diode
or light emitting diodes
ABBREVIATION MEANING
AC Alternating current
AFC Automatic frequency control
AGC Automatic gain control
AH Ampere-hour
AM Amplitude modulation
ATIS Airport terminal information service
BCD Binary coded decimal
CMOS Complementary metal oxide semiconductor
CPU Central processing unit
CVOR Conventional VHF omni-range
CW Carrier wave
DAC Digital-to-analogue converter
DC Direct current
DIL Dual in line
DIP Dual in line package
DME Distance measuring equipment
DVOR Doppler VHF omni-range
EPROM Electrically programmable read only memory
FET Field effect transistor
FM Frequency modulation
ISEP International standard equipment practice
LED Light emitting diode
LRU Line replaceable unit
LSB Lower sideband
MOS Metal oxide semiconductor
MOSFET Metal oxide semiconductor field effect transistor
PIN P-type/intrinsic/N-type
PPM Parts per million
PRF Pulse repetition frequency
PROM Programmable read only memory
PTFE Polytetrafluoroethane
PVC Polyvinyl chloride
PWB Printed wiring board
RAM Random access memory
R/C Resistor/capacitor
RF Radio frequency
RMS Root-mean-square
ROM Read only memory
SCR Silicon controlled rectifier
USB Upper sideband
SSD Static-sensitive device
UV Ultraviolet
VCO Voltage controlled oscillator
VHF Very high frequency
VOR VHF omni-range
VSWR Voltage standing wave ratio
WPM Words per minute
4
H4A71110
COMPONENT DESIGNATORS
The system of letter codes used for the designation of electronic component items of the
equipment described in this handbook conforms to Australian Standard AS1103.2
(1982). This system is as follows:
Letter Kind of Item

Code
A Assemblies, subassemblies
B Transducers, from non-electrical to electrical quantity or vice versa
C Capacitors
D Binary elements, delay devices, storage devices
E Miscellaneous
F Protective devices
G Generators, power supplies
H Signalling devices
K Relays, contactors
L Inductors, reactors
M Motors
N Analogue integrated circuits
P Measuring equipment, testing equipment
O Mechanical switching devices for power circuits
R Resistors
S Switches, selectors
T Transformers, regulators (power)
U Modulators, changes
V Tubes, semiconductors (discrete)
W Transmission paths, waveguides, aerials (antennas)
X Terminals, plugs, sockets, links, joints (also see below)
Y Electrically operated mechanical devices
Z Networks, hybrid transformers, filters, equalisers, limiters
COMPONENT DESIGNATOR SUFFIXES

All connectors (terminals, plugs, sockets. jacks) are identified by the designator letter 'X';
additionally, suffix letters are used to further identify the type or location of connectors.
Connector designators used are:
Letter Type of Connector
Code
X A single connection point mounted on a printed wiring board or otherwise located
internally within the equipment; example - a board-mounted test pin.
XA A connection point mounted on the face panel of an equipment module and
accessible during normal operation of the equipment; example - a front panel test
jack.
XF A multiway or coaxial connector with female contacts.
XM A multiway or coaxial connector with male contacts.
TERMINAL/PIN DESIGNATION
The system used for identification of terminal designations conforms to Australian
Standard AS1103.2 (1982), Section 6.5. Under this system, a terminal number is
prefixed with the qualifying symbol ':'. Thus, for example:
XFA:13 Identifies pin 13 of connector XFA.
N161:3 Identifies pin 3 of analogue integrated circuit N161.
D5:2 Identifies pin 2 of digital integrated circuit D5.
5
H4A71110
MODULE IDENTIFIERS
The major modular subassemblies of the DVOR VRB-52D are identified by a 3-letter
identifier, which appears on the front panel of the module and which is used throughout
equipment documentation as a means of reference to specific modules.
In listings of modules and their subassemblies within this handbook, the following
system is used:
a. The three-letter unit identifiers are shown thus - MRF.
b. Subassemblies contained within a main unit have the parent unit identifier
shown in brackets, thus - (MRF).
c. Subassemblies which are common to more than one main unit have the
parent unit identifiers shown, thus - (CGD/SMA).
The list following shows the identifiers of the system modules, arranged in alphabetical
order of identifiers, and the subassemblies of each.
IDENTIFIER ASSEMBLY/SUBASSEMBLY
ADS Antenna Distribution Switch 2J66076
Antenna Switch Board 1A71131
Antenna Switch Board 2A71131
ASD Antenna Switch Driver 1A71120
CCB Contactor Assembly 1A71128
CDC Carrier Directional Coupler 2A71124
Detector Board 1A71167
CGD Carrier Generator and Driver 1 A71125
Carrier Oscillator 1A71155
Carrier Generator and Driver Main Board 1A71156
Driver Amplifier 1A71157
Power Amplifier 1A71164
CMP Carrier Modulation and Protection 1A71123
CPA Carrier Power Amplifier 1A71127
Interface Board 1A71165
Splitter/Combiner 1A71166
CTU Control and Test Unit 2A72550
CTU Processor Board 2A72550
CTU Front Panel Board 2A72553
RCMS Interface Board 1A72555
DCC DC/DC Converter 1A71129
Converter Board 1A71169
Regulator Board 1A71170
MBD Monitor Bearing Counter and Data Acquisition 1A72565
MBD Main Board 1A72566
Display Board 1A72567
6
H4A71110
IDENTIFIER ASSEMBLY/SUBASSEMBLY
MFI Monitor Filter and Indent 1A71115
MRF Monitor RF Amplifier 1A71113
RF Amplifier 1A71138
Monitor RF Amplifier Main Board 1A71141
MSc Monitor Subcarrier 1A71114
MSD Monitor Signal Divider 1A71160
RLU Relay Unit 1A71697
Relay Unit Board 1A71698
RPG Reference Phase Generator 1 A71119
SCU Sideband Changeover Unit 1A71122
Driver Board 1A71152
Sideband Switch Unit 1A71153
SGN Sideband Generator 1A71121
Sideband Generator Main Board 1A71146
Phase Detector 1A71147
Sideband Oscillator 1A71150
SMA Sideband Modulator and Amplifier 2A71126
Modulator 1A71159
Sideband Directional Coupler 1A71161
Level Control Board 1A71163
Sideband Isolator (Wide Band)
Filter (Low Pass)
TSD Timing Sequence Generator 1A71118
Timing Sequence Generator Main Board 1A71145
Switch Board 1A71149
7
EMERGENCY CARDIOPULMONARY RESUSCITATION FOR
UNCONSCIOUS PATIENT.
STAY WITH VICTIM – CALL FOR HELP AND COMMENCE
RESUSCITATION.
AIRWAY:
Clear the airway. Quickly turn victim Check breathing and listen to breath, watch for
on side and remove foreign material chest movement. If breathing, leave victim on
from mouth. Place neck and jaw in side and keep the airway clear.
correct positions.
BREATHING:
If not breathing, quickly turn the victim Check circulation, carotid pulse. If present,
on his back and commence expired air continue expired air resuscitation at a rate of 15
resuscitation. mouth or mouth to nose, per minute. Check the
using jaw lift circulation after 1 minute
method to open and then every 2
airway. Give 5 minutes. If breathing
full ventilations returns, place the victim
in ten seconds. on side and keep the
airway clear.
CIRCULATION:
Check carotid pulse. If absent, begin external cardiac compression. Place the heel of one
hand on the lower half of the sternum and lock the other hand to the first by grasping
wrist or interlocking fingers. Keep fingers off the chest.
One Operator: Two Operators:

2 ventilations, 1 ventilation,
15 compressions, 5 compressions,
4 cycles per 12 cycles per
minute. minute.
CHECK PROGRESS GET HELP

- If effective In metropolitan areas, dial 000 and ask
• Carotid pulse felt with each for ambulance service. In country
compression. areas, contact your local ambulance
• Skin will become pinker. service.
National Heart Foundation of Australia

PE3 (rev) 1984
S:\Engineering\Handbooks\Common\NHF-CPR.doc
H4A71110 SECTION 1
SECTION 1
BRIEF SPECIFICATION
1-i
H4A71110 SECTION 1
TABLE of CONTENTS
1. BRIEF SPECIFICATION............................................................................. 1-1

1.1 FUNCTIONAL DESCRIPTION 1-1
1.1.1 Introduction ................................................................................................ 1-1
1.1.2 Application ................................................................................................. 1-1
1.1.3 Doppler VOR Function ............................................................................... 1-1
1.1.4 Generation of Reference and Variable Phase Signals................................ 1-1
1.1.5 Monitor System. ......................................................................................... 1-3
1.2 MECHANICAL DESCRIPTION 1-4
1.3 PERFORMANCE SPECIFICATION 1-5
1-ii
H4A71110 SECTION 1
LIST of FIGURES
Figure 1-1 DVOR Phase Definition.........................................................................1-3
LIST of TABLES
Table 1-1 Performance Characteristics Summary.....................................................1-5
LIST of DRAWINGS
The following drawings appear at the end of Section 1
Figure 1A Block Diagram – Signal Generation Drawing 71110-1-189

Figure 1B Block Diagram – Monitor and Control Sections Drawing 71110-3-180
1-iii
H4A71110 SECTION 1
1. BRIEF SPECIFICATION
1.1 FUNCTIONAL DESCRIPTION
1.1.1 Introduction
The types 4A71110 (single) and 5A71110 (dual) Doppler VOR Ground Beacon
VRB-52D (DVOR VRB-52D) are designed and manufactured to meet the specifications
outlined in Volume 1 of ICAO Annex 10 for International Standards and Recommended
Practices for Aeronautical Telecommunications. The equipment is built to the highest
current manufacturing standards, and incorporates state-of-the-art technology. The unit
is completely solid state, and delivers both the reference phase and variable phase
signals to their respective antenna systems with high efficiency and reliability, and with
small unit size.
The DVOR VRB-52D has been designed using digital techniques in the timing and
waveform generation circuitry, and analogue techniques in the power amplifying circuits.
Timing is derived from stable crystal clock circuits. which ensures accurate clocking of all
critical time-dependent pulse generation and measurement circuits.
The DVOR VRB-52D is available with a transmitter power output of 50 watts, with an
option of incorporating an additional 50-watt power amplifier module and combiner unit
to provide a total power output of 100 watts.
The DVOR beacon may be configured for single or dual operation. A dual beacon
consists of two electronic equipment racks, operating into one antenna system via
changeover relays.
1.1.2 Application
The DVOR VRB-52D provides an omnidirectional navigational aid that enables an
aircraft to determine its bearing in azimuth relative to the ground beacon.
The DVOR system has been designed to give a signal which, as far as the aircraft VOR
receiver is concerned, is compatible with the signal provided by a conventional VOR
system.
1.1.3 Doppler VOR Function

The DVOR system provides each equipped aircraft with information regarding the
bearing of the aircraft relative to the selected DVOR beacon.
Initially, the airborne receiving equipment is set to the correct frequency transmitted by
the desired ground station. The airborne receiver demodulates the two 30 Hz signals
contained as modulation on the transmitted carrier, compares their phase difference,
and displays the resultant difference in degrees on a readout. The readout, therefore,
indicates the bearing of the aircraft relative to the beacon.
1.1.4 Generation of Reference and Variable Phase Signals

" REFER Figure 1A
The DVOR ground beacon radiates complex double sideband signals from which two 30
Hz signals are derived in the aircraft. The phase of one of these signals, called the
reference signal, is independent of the azimuth bearing.
The phase of the other signal, called the variable signal, has a one-to-one relationship
with the magnetic bearing of the aircraft relative to the beacon. This information is
obtained by measuring the phase difference between the reference and variable 30 Hz
signals.
1-1
H4A71110 SECTION 1
In the DVOR system the carrier is amplitude-modulated with a 30 Hz signal (as well as
other components such as speech and identification code signals) and is radiated from
an omnidirectional antenna. This provides the reference signal in the system. The
direction-dependent signal is generated in space by switching upper and lower sideband
signals around a circular array of 48 antennas, to amplitude modulate the carrier with a
9960 Hz subcarrier. This subcarrier is in turn frequency modulated, as a result of
switching around the ring of antennas.
As the frequency deviation of the FM signal specified for the VOR is ±480 Hz and the
time period for one rotation is 1/30th of a second, then the resulting diameter of the circle
is approximately five wavelengths, or 13.5 metres at 115 MHz. The aircraft receiver
therefore sees a Doppler shift of the sideband frequencies deviating ±480 Hz thirty times
a second. Note that the signal is radiated anticlockwise since the FM and AM signals
have changed with respect to a conventional VOR.
The system provides for 160 discrete operating channels within the frequency range 108
to 117.95 MHz. The beacon output is nominally 50 watts which provides a nominal
operating range of 150 nautical miles with a bearing accuracy of ±0.5 degrees for all
elevation angles from 0 to 40 degrees. An optional variant provides for an additional 50
watts power amplifier and combiner unit to raise the total transmitter power output to 100
watts.
Referring to the diagram shown in Figure 1-1, the FM detected signal leads the AM
detected signal as a receiver is moved clockwise around the beacon. The degree of lead
increases with clockwise movement around the beacon. Here the AM signal is always
shown in the same phase (0 degrees) and is called the reference signal. The phase of
the FM detected signal changes in a one-to-one relationship with magnetic bearing and
is called the variable signal.
During installation and adjustment of the beacon the 48-antenna array will be so
positioned that, at magnetic North, both 30 Hz AM and FM signals will be in phase and
the positive-going zero crossing of these signals will coincide with the position of the
number one antenna element. This antenna element is located at the Northern end of a
radial passing through the central antenna.
1-2
H4A71110 SECTION 1
Figure 1-1 DVOR Phase Definition
1.1.5 Monitor System.

" REFER Figure 1B
The monitor subsystem of the DVOR processes a sample of the signal radiated by the
beacon antenna to determine whether the main parameters of the transmitted signal are
within preset tolerances. The signal used by the monitor is received by a monitor
antenna located about 80 metres from the centre of the antenna array. The parameters
monitored are:
Bearing
• 30 Hz AM level
• 30 Hz FM level
• 9960 Hz subcarrier level
• Antenna fault (notch)
• Identification code.
The monitor also incorporates a fail-safe facility that gives an alarm if the bearing
counter circuits stop functioning. Any of the alarms signalled by the monitor will cause
the DVOR rack to cease transmitting.
The DVOR monitor may be configured for single or dual operation. In dual operation,
both monitors are active, and will process the signals received from the radiating
transmitter.
1-3
H4A71110 SECTION 1
1.2 MECHANICAL DESCRIPTION

A single DVOR system VRB-52 D consists of one rack of electronics connected to two
24-antenna distributor switches. A dual DVOR system consists of two electronic
equipment racks, a transfer relay unit and two antenna distributor switches. The antenna
distributors feed the 48 sideband antennas which are mounted on a 30.5 metre diameter
counterpoise approximately 3 metres above ground level. In a standard installation, the
equipment shelter is located underneath the centre of the counterpoise. For a mountain-
top installation the equipment shelter may be located away from the counterpoise, in
which case the antenna distribution switches are sited on the counterpoise at the centre
of the antenna ring.
Most of the active circuits are contained on printed wiring boards which are connected to
the modules by means of a plug and socket arrangement, and are readily removable.
The rack is operated from a mains power supply with an output voltage of 24 volts which
is also used as a float charger for a standby battery supply.
The beacon is designed for unattended operation and may be switched on or off from a
remote location. The status of the beacon functions may also be signalled to a remote
location.
1-4
H4A71110 SECTION 1
1.3 PERFORMANCE SPECIFICATION

The performance parameters of the major system functions are given in Table 1-1
following.
Table 1-1 Performance Characteristics Summary
CHARACTERISTIC PARAMETER VALUE/LIMITS
Power Supply Voltage +22 to +28 volts

Requirements
Current drain (normal operation, 27.5 volts DC)
50 watts rack 16 amperes
100 watts rack 22 amperes
In a dual DVOR system, this power supply is required
for each rack
Environmental Indoor installation Temperature -10 to +60 degrees C
Condition Limits
Outdoor installation Temperature -25 to +70 degrees C
Wind 160 km/hr (100 mph) in
ice and snow
Frequency Frequency range 108 to 117.95 MHz
Characteristics
Operating frequency Crystal controlled at a
frequency within specified
range
Carrier frequency stability ±0.002%
Transmitter Output power 50 or 100 watts
Characteristics
Type of modulation Amplitude
Radiation polarisation Horizontal
Reference phase Frequency 30 Hz ±0.01 %
Modulation depth 28% to 32%
Ident Code International Morse, up to
five characters
Modulation frequency 1020 ±50 Hz
Modulation depth 0 to 15%, adjustable
Keying speed 7 words per minute,
adjustable
Repetition rate 6 times per minute,
adjustable
Voice modulation Frequency range 300 Hz to 3000 Hz
Modulation depth 10% to 30%
(recommended 15%)
Noise due to signal More than 15 dB below
commutation ident tone at modulation
depth of 10%
Variable phase modulation Subcarrier frequency 9960 Hz ±0.2%
(FM on subcarrier) (9969 Hz actual)
Mean depth of 28% to 32%
modulation by
subcarrier
FM modulation index 16±1
1-5
H4A71110 SECTION 1
Amplitude modulation Less than 40%

of subcarrier at a
distance of 300 metres
(1000 feet) from central
antenna
Station bearing adjustment ±6.5 degrees
Monitor Facilities The following conditions cause alarm conditions to be raised by the monitor
facilities:
Change in transmitted bearing 1 degree maximum (adjustable)
information
Reduction in modulation depth of Adjustable, set to 15% of nominal level
subcarrier, or 30 Hz AM, or 30 Hz FM
Ident code failure Continuous tone or absent tone
Antenna monitoring Failure of a diametrically opposite
antenna pair
Remote Input Voice modulating signal:
Facilities
Microphone input -50 dBm to -20 dBm
(into 600 ohms)
Line input -20 dBm to +10 dBm
(into balanced 1200
ohms)
Remote Monitoring Status indications VOR Normal
Facilities
Transfer
Shutdown
Additional parameters monitored Refer Appendix C
AC Mains Power Output voltage adjustment range 20-32 volts
supply
Output current rating 30 amperes maximum
Input voltage 200.210.220,230, 240.
250, 260 volts ±10%
Input frequency 48 Hz to 65 Hz
Line regulation 1 % for ±10% variation
Load regulation 0.4 volts, 0 to 20 amperes
Noise and ripple 0.5 volts peak to peak

Temperature coefficient of output voltage ±0.02% per degree C
Transient response 200 milliseconds
(no load to full load and full load to no load)
Efficiency 70% at 24 volts 20
amperes
Overcurrent protection Current limit is set for 30
amperes
Reverse voltage protection Fuse
Ambient temperature range - 10 to +60 degrees C
Battery Supply 50 watts single equipment requires a 125 ampere-hours battery for 6 hours
operation.
1-6
H4A71110 SECTION 1
A 50 watts dual system requires two 24 volts battery banks of 125 ampere-hours
capacity for 6 hours operation of each rack (a total of 12 hours battery operation).
Antenna System Frequency range 108 MHz to 118 MHz
Carrier antenna Modified Alford loop
Sideband antennas 48 modified Alford loops
mounted in a circle of 13.5
metres diameter with
carrier antenna at the
centre
Polarisation Horizontal
Horizontal pattern Omnidirectional within
±0.5 dB
Bearing accuracy ±0.5 degrees maximum
for 0 to 40 degrees
elevation angle
Alignment Carrier antenna and No. 1
sideband antenna in line
with magnetic North ±1
degree
Weatherproofing Glass fibre radome over
each Alford loop antenna
Monitor antenna Folded dipole
1-7
H4A71110 SECTION 2
SECTION 2
TECHNICAL DESCRIPTION
2-i
H4A71110 SECTION 2
TABLE of CONTENTS
2. TECHNICAL DESCRIPTION ...................................................................... 2-1

2.1 SYSTEM DESCRIPTION 2-1
2.1.1 Station Description ..................................................................................... 2-1
2.1.2 Antenna Description................................................................................... 2-1
2.1.3 Rack Description........................................................................................ 2-1
2.1.4 Subrack Description ................................................................................... 2-2
2.1.5 Mechanical Description .............................................................................. 2-3
2.1.6 Principles of Operation............................................................................... 2-4
2.2 SUBSYSTEM DESCRIPTION DESCRIPTIONS 2-9
2.2.1 Carrier Generation and Modulation Subsystem........................................ 2-10
2.2.2 Sideband Generation Subsystem............................................................. 2-12
2.2.3 Timing Sequence Generation Subsystem ................................................ 2-13
2.2.4 Reference Phase Generation Subsystem ................................................ 2-14
2.2.5 Sideband Amplifier and Modulator Subsystem ......................................... 2-15
2.2.6 Sideband Antenna Commutating Subsystem ........................................... 2-16
2.2.7 Power Supply Subsystem ........................................................................ 2-17
2.2.8 Monitor, Controller and Telemetry Subsystem.......................................... 2-18
2.3 MODULE DESCRIPTIONS 2-21
2.3.1 CGD - Carrier Generator and Driver......................................................... 2-21
2.3.2 CPA - Carrier Power Amplifier.................................................................. 2-25
2.3.3 CDC - Carrier Directional Coupler ............................................................ 2-27
2.3.4 CMP - Carrier Modulation and Protection................................................. 2-28
2.3.5 SGN - Sideband Generator ...................................................................... 2-31
2.3.6 SMA - Sideband Modulator and Amplifier................................................. 2-37
2.3.7 TSD - Timing Sequence Generator .......................................................... 2-44
2.3.8 RPG - Reference Phase Generator.......................................................... 2-50
2.3.9 SCU - Sideband Changeover Unit............................................................ 2-56
2.3.10 ASD - Antenna Switch Driver ................................................................... 2-58
2.3.11 ADS - Antenna Distribution Switch ........................................................... 2-59
2.3.12 CTU - Control and Test Unit..................................................................... 2-61
2.3.13 MRF - Monitor RF Amplifier...................................................................... 2-73
2.3.14 MSC - Monitor Subcarrier......................................................................... 2-75
2.3.15 MFI - Monitor Filter and Indent ................................................................. 2-77
2.3.16 MBD - Monitor Bearing Counter and Data Acquisition.............................. 2-81
2.3.17 DCC - DC/DC Converter ........................................................................ 2-100
2.3.18 CCB - Contactor Assembly .................................................................... 2-103
2.3.19 RLU - Relay Unit .................................................................................... 2-104
2.3.20 MSD - Monitor Signal Divider ................................................................. 2-105
2.3.21 Voltage Limiter ....................................................................................... 2-106
2.3.22 External I/O Board.................................................................................. 2-107
2-ii
H4A71110 SECTION 2
LIST of FIGURES
Figure 2-1 Simulation of Rotating Antennas ...........................................................2-4

Figure 2-2 Received VHF Signal ............................................................................2-5
Figure 2-3 Antenna Switching System Timing Diagram..........................................2-7
Figure 2-4 Sideband Energy Supply to Antennas ...................................................2-8
Figure 2-5 SGN Phase Control Waveforms..........................................................2-35
Figure 2-6 SMA Blending Function Modulation Waveforms..................................2-43
Figure 2-7 TSD Timing Waveforms ......................................................................2-46
Figure 2-8 TSD Timing Waveforms ......................................................................2-47
Figure 2-9 TSD Blending Function Generator Waveforms....................................2-48
Figure 2-10 RPG Keyer Waveforms .......................................................................2-54
Figure 2-11 RPG 30Hz Sine Generator Waveforms ...............................................2-55
Figure 2-12 CTU Block Diagram ............................................................................2-62
Figure 2-13 CTU Processor Board Block Diagram .................................................2-64
Figure 2-14 CTU Front Panel Board Block Diagram...............................................2-68
Figure 2-15 RCMS Interface Board Block Diagram ................................................2-71
Figure 2-16 MSC Notch Circuit Waveforms............................................................2-76
Figure 2-17 MFI Quadrature Phase Detector Waveforms.......................................2-79
Figure 2-18 MFI Ident Fault Detection Timing Diagram ..........................................2-80
Figure 2-19 Monitor Bearing Counter PLD .............................................................2-87
Figure 2-20 Bearing Counter Gating.......................................................................2-89
Figure 2-21 Ident Keying One-Shot PLD ................................................................2-93
Figure 2-22 DCC Converter Switching Waveforms...............................................2-102
LIST of TABLES
Table 2-1 Truth Table D30 - VOR Key Output XMA:21 ...........................................2-53
Table 2-2 Table D31 - DME Key Output XMA:22 ....................................................2-53
Table 2-3 Top Bay Motherboard Interconnections ..................................................2-97
2-iii
H4A71110 SECTION 2
2. TECHNICAL DESCRIPTION
2.1 SYSTEM DESCRIPTION
2.1.1 Station Description

The single DVOR station, type 4A71110, consists of one antenna system and one
VRB-52D rack.
A dual DVOR station, type 5A71110, consists of one antenna system, two VRB-52D
racks and one transfer relay unit.
2.1.2 Antenna Description

The antenna system consists of:
Antenna Distributor Switch Qty 2 2J66076
Loop Antenna (including Antenna Balun 1A71134) Qty 49 1A71133
Monitor Antenna Qty 1 71110-4-125
2.1.3 Rack Description

The VRB-52D rack without electronics is identified as type 2A71136. Included in the rack
are four Subrack Frames (types 2A - 5A71132) and all rear wiring. The intra-rack wiring,
both power and signal wiring, is provided by a cable loom. All the connections provided
by this loom are listed in Drawing 71136-4-143.
The subrack arrangement is:
Subrack Frame Top Bay 5A71132
Subrack Frame 2A71132
Subrack Frame 3A71132
Subrack Frame Bottom Bay 4A71132
A motherboard, type 1A72504, is fitted to the top bay.
2-1
H4A71110 SECTION 2
2.1.4 Subrack Description

The VRB-52D rack with electronics is identified as type 2A71111; the arrangement of the
rack is shown in Drawing 71111-1-29. The bays contain the following modules, listed
from left to right:
TOP BAY
Monitor RF Amplifier MRF 1A71113
Monitor Subcarrier MSC 1A71114
Monitor Filter and Ident MFI 1A71115
Monitor Bearing Counter and Data Acquisition MBD 1A72565
Control and Test Unit CTU 2A72550
Blank Panel (space allocated for Remote Maintenance Monitoring Interface)
SECOND BAY
Timing Sequence Generator TSD 1A71118
Reference Phase Generator RPG 1A71119
Blank Panel 2 units wide
Antenna Switch Driver ASD 1A71120
Antenna Switch Driver ASD 1A71120
Sideband Generator SGN 1A71121
Sideband Changeover Unit SCU 1A71122
THIRD BAY
Carrier Modulation and Protection CMP 1A71123
Blank Panel 1 unit wide
Carder Generator and Driver CGD 1A71125
Sideband Modulator and Amplifier SMA 2A71126
Sideband Modulator and Amplifier SMA 2A71126
BOTTOM BAY
Contactor Assembly CCB 1A71128
DC/DC Converter DCC 1A71129
Blank Panel 4 units wide
Carrier Power Amplifier CPA 1A7112
The bottom of the rack contains the AC Power Supply 3A71130. In the left rear of the
rack are situated the Carrier Directional Coupler (CDC module) 2A71124, and the RF
Low Pass Filter. In the right rear of the rack is situated the Voltage Limiter 1A71168 and
the External I/O Board 2A72557.
The description above refers to the rack as a 50-watt system; for the 100-watt version
the differences are that the bottom bay contains an additional Carrier Power Amplifier
(CPA module) 1A71127 in the space normally covered by a 3-unit width blank panel. In
the rear of the rack are an additional Voltage Limiter 1A71168 and a Splitter/Combiner
1A71166.
2-2
H4A71110 SECTION 2
2.1.5 Mechanical Description

Apart from the two Antenna Distributor Switch cases, the equipment is accommodated
within a standard cabinet approximately 600 mm square and 2 metres high. The
arrangement of the rack and degree of modularity are shown in Drawing 71111-1-29. All
the subassemblies, other than the AC Power Supply (power supply/battery charger), are
contained in plug-in modules.
Access to the rear of the rack is provided by a lockable louvered door fitted with a quick-
release hinge system. Side panels are secured to the rack with screws into threaded
bushes.
More than half of the modules consist of low-power low-frequency circuits. In these units,
the components are all mounted on one large printed circuit board which forms part of
the structure of the module. For servicing or troubleshooting, the entire module can be
replaced. The remainder of the modules contain high power and/or high frequency
circuits. These units consist of a printed circuit board and, where necessary, a number of
subunits. The printed circuit boards and the subunits are readily removable from the
modules, being connected into the module via plugs and sockets. This allows servicing
and troubleshooting to be carried out by replacing the subunits or printed circuit boards,
rather than replacing the entire module.
All VHF circuits are contained within totally enclosed metal boxes to reduce as far as
possible any RF leakage from the equipment.
The AC mains operated power supply is located at the bottom of the rack. Electrical
connections are accessible from the front. For servicing, the AC power supply may be
removed from the rack as a complete unit. Most of the components in the control circuits
are mounted on a plug-in printed circuit board inside the unit. The components that are
hard mounted are arranged to give easy access for removal and replacement.
AC and DC power connections are made to terminals located at the rear of the cabinet.
Cabinet ventilation is provided by an air entry space at the bottom and an air exit via the
mushroom top on the cabinet. In addition, vents are provided at the front of the cabinet
to assist ventilation to the heat generating units. Baffles are mounted inside the cabinet
to deflect the rising hot air away from the low level circuits.
2-3
H4A71110 SECTION 2
2.1.6 Principles of Operation
2.1.6.1 Generation of VOR Signal

A complete equipment installation provides an omnidirectional aid that enables an
aircraft to determine its bearing in azimuth relative to the ground beacon.
The DVOR system has been designed to give a signal which, as far as the aircraft
receiver is concerned, is compatible with the signal given by a conventional VOR
(CVOR) system.
In both systems the ground beacon radiates a complex VHF signal from which two 30
Hz signals are derived in the aircraft. The phase of one of these signals, called the
‘reference' signal, is independent of the azimuth bearing. The phase of the other signal,
called the 'variable' signal, has a one-to-one relationship with the azimuth. The azimuth
information is obtained by measuring the phase difference between the reference and
the variable 30 Hz signals.
For persons familiar with the CVOR beacon it is important to understand that the
definitions of reference and variable signals in the DVOR system are opposite of those in
the CVOR system; that is, for the DVOR system the 30 Hz amplitude modulated signal is
the reference and the Doppler (30 Hz frequency modulated) signal is the variable. To
avoid confusion, these signals are specifically termed 30 Hz AM (for the reference) and
30 Hz FM (for the variable).
From the central DVOR antenna is radiated the carrier (fc) in the band 108 to 118 MHz,
amplitude modulated with the 30 Hz AM (reference) signal. From two diametrically
opposite antennas in the ring there are radiated the upper and lower sidebands to
produce an amplitude modulation of the carrier with a 9960 Hz subcarrier. This
amplitude modulation is a result of adding, in space, the carrier signal and two
sidebands, each differing in frequency from the carrier by 9960 Hz. (Note that both upper
and lower sidebands are produced because the VRB-52D is a double sideband DVOR
beacon). These two sidebands are switched around the antenna ring at the rate of 30
revolutions per second, simulating the continuous rotation of one pair of diametrically
opposite antennas at a 30 Hz rate, as shown in Figure 2-1.
Figure 2-1 Simulation of Rotating Antennas
2-4
H4A71110 SECTION 2
No Doppler shift occurs in the sideband signals when they are radiated from a pair of
antennas that lies on the line joining the central antenna to the aircraft antenna. Hence,
at this instant in time, there is no frequency shift of the sidebands and so there is no
deviation of the resulting subcarrier signal.
When the sidebands are radiated from other antennas in the ring, there will be some
apparent relative motion between the aircraft and the radiating source. This relative
motion causes a Doppler frequency shift of the sidebands, with resulting deviation of the
subcarrier signal.
The VRB-52D sideband frequencies are fc±9960 Hz. The sideband frequencies are
crystal controlled, with crystals matched to the main carrier crystal.
In the aircraft receiver the complex VHF signal is firstly envelope detected to obtain the
30 Hz AM signal and the 9960 Hz subcarrier. Then, after separation of these signals, the
9960 Hz subcarrier is FM demodulated to obtain the 30 Hz FM signal. Because the 30
Hz AM reference signal has been radiated from the fixed central antenna, its phase is
independent of azimuth, and the phase difference between it and the 30 Hz FM variable
signal corresponds, degree for degree, with the bearing from the ground beacon referred
to magnetic North, zero degrees phase difference corresponding with magnetic North.
Figure 2-2 shows the received VHF signal with the 9960 Hz subcarrier and as 30 Hz
frequency modulation (the 30 Hz amplitude modulation is omitted). The deviation of the
subcarrier is determined by the diameter of the antenna ring; this is 13.5 metres, giving
the required frequency deviation of ±480 Hz to the 9960 Hz subcarrier.
Figure 2-2 Received VHF Signal
2-5
H4A71110 SECTION 2
2.1.6.2 Antenna Switching and System Timing

The DVOR beacon uses 48 sideband antennas, numbered 1 to 48 in a counter-
clockwise direction. The system is installed so that the carrier antenna and the No. 1
sideband antenna are in line with magnetic North.
The antenna ring is electrically divided into two sections, comprising antennas 1 to 24
and antennas 25 to 48. For one half of the 30 Hz switching cycle (i.e.; 16.6 milliseconds)
LSB energy is fed to antennas 1 to 24 and USB energy is fed to antennas 25 to 48. For
the remaining half-cycle, the reverse situation applies.
The time sequence for antenna switching is shown in the system timing diagram in
Figure 2-3. This shows the relationship between antenna switching, the 30 Hz AM
reference, and other relevant signals in the beacon. Zero degrees, (or time t = 0) refers
to the positive zero crossing of the 30 Hz AM sine wave reference. At zero degrees,
peak LSB energy is radiated from antenna 1 and peak USB energy is radiated from
antenna 25 (as shown by the cross-hatched 'envelopes' in Figure 2-3). One half-cycle
later, at 180 degrees, USB is radiated from antenna 1 and LSB from antenna 25.
The timing diagram also shows the antenna switch drive signals and the sideband
changeover switch signals in relation to the station timing reference, 30 Hz Φ0.
To allow adjustment of station bearing, the 30 Hz AM reference is varied with respect to
the antenna switching signals. This is shown on the diagram by the adjustment range of
the 30 Hz REF square wave (approximately ±6.5 degrees). The 30 Hz sine wave is
locked to this square wave and so it varies by the same amount.
Sideband energy may be fed to the antennas by various paths, as shown in Figure 2-4.
For clarity, the antennas have been further divided into two groups of odd and even
antennas. The RF switches are shown diagrammatically as single-pole, single-throw
switches. Sideband energy is fed from the sideband modulators to the ODD and EVEN
sideband switches, through the antenna distributor switches and then to the antennas.
In Figure 2-4 the various RF switches are shown in the state that would apply at zero
degrees (time t = 0); that is, at the time corresponding to the positive zero crossing of the
30 Hz AM sine wave. This results in LSB being fed to antenna 1 (then antenna 2) and
USB being fed to antenna 25 (then antenna 26).
Considering the ODD antennas only, at zero degrees, LSB from the LSB modulator
ODD output is fed via switch A of the ODD sideband switch to the 1-23 antenna group.
Switch 1 is also closed, feeding this signal to antenna 1. Simultaneously, USB from the
USB modulator ODD output is fed via switch C of the ODD sideband switch to the 25-47
antenna group and through the closed switch to antenna 25.
One half-cycle later (at 180 degrees), the sideband switch will change state, so that D
and B are closed and A and C are open. This allows USB to be fed to antenna 1 and
LSB to antenna 25.
The switching sequence for the EVEN antennas is the same, except for a 0.7
milliseconds time displacement as shown in Figure 2-3.
2-6
H4A71110 SECTION 2
Figure 2-3 Antenna Switching System Timing Diagram
2-7
H4A71110 SECTION 2
Figure 2-4 Sideband Energy Supply to Antennas
2-8
H4A71110 SECTION 2
2.2 SUBSYSTEM DESCRIPTION DESCRIPTIONS

To assist in the understanding of the operation of the DVOR Beacon, the equipment is
described as a number of subsystems. These subsystems, which are described below,
are shown on two block diagrams in Section 1. These diagrams have the circuits of the
beacon arranged into functional blocks, to best illustrate the methods used for producing
the various signals. Figure 1A shows the arrangement of the signal generation and
transmission sections of the beacon. Figure 1B shows the monitor and control sections.
The block diagrams also indicate the circuit functions provided by the various modules
used in the beacon, and as described in Section 2.3 – Module Descriptions
2-9
H4A71110 SECTION 2
MODULE DESCRIPTIONS.
2.2.1 Carrier Generation and Modulation Subsystem

This subsystem is concerned with the transmission of a reference signal from the carrier
antenna. The 30 Hz AM reference phase signal, the voice and the beacon identity code
signals are summed, compared with an envelope feedback signal and the error signal
(i.e., the difference between the desired and the actual modulation) is used to amplitude
modulate the carrier.
Output power sensing and level control is included to ensure that the carrier is radiated
at constant power.
The modules and subunits contained in this subsystem are:
CGD Carrier Generator and Driver 1A71125
Subunits Carrier Oscillator 1A71155
CW Main Board 1A71156
CPA Carrier Power Amplifier 1A71127
Subunits Splitter/Combiner 1A71166
Power Amplifier (2) 1A71164
Low Pass Filter
CDC Carrier Directional Coupler 2A71124
Subunit Detector Board 1A71167
CMP Carrier Modulation and Protection 1A71123
The CGD module provides two outputs at the carrier frequency; one of these excites the
carrier power amplifier and the other is used for test purposes as a phase reference in
the sideband generator.
The Carrier Oscillator provides two outputs at the carrier frequency; one drives the
Driver Amplifier and the other is used for test purposes as described above.
The Driver Amplifier is a 2-stage RF power amplifier with the second stage modulated at
a low level with signals supplied from the CMP module.
The Power Amplifier is a single-stage RF power amplifier with sufficient power gain to
provide a nominal power output of 10 watts from the CGD module. A feedback loop
limits the maximum power output that can be delivered to the CPA amplifiers. This loop
only operates under fault conditions.
In the CPA module, the input signal is split two ways by a passive power splitter and the
signals are amplified by separate power amplifiers to a level of 30 watts each. The
signals are then recombined in a passive combiner to give a nominal 50 watts output
from the carrier subsystem.
The output signal from the CPA module passes through a low-pass filter (to reduce
carrier harmonics) and a directional coupler. The coupler contains two coupling loops
one to sense forward and reverse power for transmitter control, and the other to provide
a reference signal for sideband phase lock.
2-10
H4A71110 SECTION 2
The CMP module accepts input signals from the 30 Hz reference phase, ident and voice
channels. These signals are summed and compared with a sample of the carrier
envelope in an error amplifier. The derived error signal is used to modulate the second
stage of the driver amplifier.
Protection circuits within the CMP module monitor the forward and reverse power levels
from the directional coupler and detector circuits. The levels obtained are compared with
preset levels and if there is either an increase or a decrease in forward power or an
increase in reverse power which exceeds these levels, then an alarm is given. An
imbalance detector across the combiner senses the difference in power levels from the
two amplifiers. This ensures that transmitter shutdown will occur should one Power
Amplifier fail.
The CMP module contains the voice channel which accepts an audio input from a
remote line (high level) or a local microphone (low level). The voice channel may be
level stabilised by a compression amplifier to give a constant modulation depth of the
carrier. The bandwidth is limited to prevent interference with the navigation signals.
This module also contains the 1020 Hz tone generator for the ident channel. The tone is
gated by the Morse code generated in the keyer (described in Section 2.2.4).
2-11
H4A71110 SECTION 2
2.2.2 Sideband Generation Subsystem

This subsystem is concerned with the generation of the sideband frequencies using two
phase-locked crystal oscillators. To establish the correct relationship between the
sideband and carrier frequencies a sample from the output of the carrier transmitter is
mixed with the sideband frequencies in a balance mixer. The resultant signal is
compared, in a phase comparator, with a 9960 Hz reference frequency derived from the
master clock frequency. A DC voltage generated by the phase comparator is used to
control and maintain the sideband frequencies in a correct relationship with the carrier
frequency.
SGN Sideband Generator 1A71121
Subunits Phase Detector 1A71147
SGN Main Board 1A71146
Sideband Oscillator 1A71150
The SGN module generates two phase-locked sideband signals at fc+9960 Hz and
fc-9960 Hz for feeding the driver amplifiers and sideband modulators. In addition, a 9960
Hz reference signal is derived using the master oscillator frequency of 3.1104 MHz from
the TSD module. Two digital delay circuits in the 9960 Hz signal path allow a range of
adjustment of the phase of each sideband to permit correct RF phasing of the DVOR
beacon. For test purposes, a switch on the front panel provides a direct connection to
the carrier oscillator which allows the sidebands to be locked to the carrier frequency
when sidebands are required without the carrier transmitter operating.
The Phase Detector contains a signal dividing circuit and two balanced mixers. A sample
of the reference carrier output is used as an RF reference for each balanced mixer.
Samples of the sideband signals are taken from directional couplers at the output of
each of the sideband driver amplifiers and fed back to the balanced mixers.
The SGN Main Board contains a sample-and-hold phase detector for each sideband
which compares in phase and frequency, the beat frequency from the mixer with a 9960
Hz reference frequency derived from the master clock frequency in the TSD module.
The upper and lower sideband signals are generated by two voltage-controlled crystal
oscillators. The frequency of each oscillator is controlled by two varactor diodes in series
with the crystal. The DC control voltage derived from the phase controller is applied to
the varactor diodes to correct the sideband frequency, and phase lock the voltage-
controlled crystal oscillators.
The phase shift adjustment circuits in the 9960 Hz signal path to each phase detector
circuit allow the sidebands to be correctly phased with respect to the carrier.
2-12
H4A71110 SECTION 2
2.2.3 Timing Sequence Generation Subsystem

This subsystem generates timing signals for correct sequential control of antenna
commutation, sideband switching, blending function generation, subcarrier and 30 Hz
reference generation. It also provides facilities for static switching of antennas and
simulated rotation of the station for error curve measurement.
The module and subunits contained in this subsystem are:
TSD Timing Sequence Generator 1A71118
Subunits TSD Main Board 1A71145
The TSD module provides the following output signals:

a. 30 Hz for station reference phase generation.
b. 12.96 kHz and 207.36 kHz for clocking the reference phase delay circuits in
RPG.
c. 720 Hz and 30 Hz for antenna commutation.
d. 77.76 kHz for blending function generation.
The master clock crystal oscillator generates a frequency of 3.1104 MHz.
The timing sequence dividers produce the timing signals necessary to synchronise all of
the switching functions in the beacon.
The blending function generator provides a half-sine shaped blending function which is
used to amplitude-modulate the upper and lower sidebands. The generator consists of
two circuits each containing a counter, a read-only memory (ROM) and a digital to
analogue converter (DAC). A 77.76 kHz clock signal from the timing sequence circuits is
applied to the counter, causing it to count up from a preset starting value. The counter
addresses the ROM causing it to give a digital value to the DAC for each location. The
digital values in the ROM correspond to sine values so that the output of the DAC is a
half sine wave.
The amplitude of the blending function waveform is controlled by a DC level supplied
from the sideband level control section in the SGN module.
The changeover switch timing provides two 30 Hz signals of the correct phase
relationship to operate the ODD and EVEN switch drives for the sideband changeover
switches.
The antenna distribution counters provide binary signals for activating the appropriate
antenna distributor switch in the correct timing sequence.
2-13
H4A71110 SECTION 2
2.2.4 Reference Phase Generation Subsystem

This subsystem generates the 30 Hz reference signal used to modulate the reference
carrier signal. It also contains digital delay circuits which allow the 30 Hz reference
phase information transmitted by the beacon to be adjusted to the correct magnetic
bearing.
An ident key provides the Morse code ident signal for station identification.
The module contained in this subsystem is:
RPG Reference Phase Generator 1A71119
The RPG subsystem contains the 30 Hz reference phase adjustment, the 30 Hz

reference sine generator and the ident keyer.
The 30 Hz reference phase adjustment is provided by two stages of variable digital delay
each controlled by a front panel rotary switch. One switch allows a 'fine' phase
adjustment (approximately 0.05 degrees per step) and the other is for 'coarse'
adjustment (approximately 0.8 degrees per step). A total phase delay of 6.5 degrees is
provided in each direction by these adjustments. Two frequencies of 12.96 kHz and
207.36 kHz from the timing sequence dividers provide the necessary timing signals to
generate the delays.
The 30 Hz reference sine wave is synthesised by a digital waveform generator
comprising a counter, a read-only memory (ROM) and a digital-to-analogue converter
(DAC). A 12.96 kHz clock signal from the timing sequence dividers is applied to the
counter, causing it to count up from a preset starting value. The counter addresses the
ROM, causing it to give a digital value to the DAC for each location. The digital values in
the ROM correspond to sine values so that the output of the DAC is a 30 Hz sine wave.
The Morse keyer subsection may be programmed to generate dots, dashes and spaces
to give a combination of Morse letters or numbers. Presets located on the module board
allow the code speed and repetition rate to be set independently.
The DME interfacing provides the necessary sharing of ident functions when the DVOR
is collocated with the DME.
2-14
H4A71110 SECTION 2
2.2.5 Sideband Amplifier and Modulator Subsystem

This subsystem amplifies the sideband signals from each of the voltage-controlled
crystal oscillators to a level of about 5 watts. The amplified sideband signals are then
modulated with a sine-shaped blending function. The modulated sidebands are available
at the output of this subsystem for driving the ODD and EVEN antenna RF switches.
SMA Sideband Modulator Amplifier (2) 2A71126
Subunits Driver Amplifier (2) 1A71157
Sideband Coupler (2) 1A71161
Sideband Modulator (2) 1A71159
Level Control Board (2 1A71163
Sideband Isolator (Wide Band) (2)
Filter (Low Pass) (2)
This subsystem amplifies the sideband signal in a Driver Amplifier subunit identical to
that used in the CGD module. In this application it produces a nominal output of 5 watts.
The output level is controlled by a feedback circuit which varies the error voltage applied
to the modulated stage. The output level is sensed by a peak detector in the modulator.
A ferrite isolator provides a high degree of isolation and an impedance match and, with
the low pass filter, prevents undesirable intermodulation products from being transmitted
to the Sideband Modulator. A directional coupler supplies a RF sample to the phase
detector circuit for phase lock purposes.
Modulation of the sideband signal by the sine-shaped blending function is performed by
a PIN diode absorption modulator. This modulator controls the level of the sideband RF
energy by varying the current through two PIN power diodes. Modulation linearity is
maintained by an envelope feedback loop which compares the detected envelope of the
RF output with the desired modulating signal.
Two outputs are produced, one for the ODD antennas and one for the EVEN antennas.
2-15
H4A71110 SECTION 2
2.2.6 Sideband Antenna Commutating Subsystem

The function of this subsystem is to blend the sideband signals from one sideband
antenna to the next in a manner approximating a smooth transition, thus simulating a
rotating RF source radiated by the sideband antenna system. Two sideband changeover
switches alternatively switch upper and lower sideband signals to the antenna
distribution switches which switch the signals to each antenna in turn.
ASD Antenna Switch Driver 1A71120
SCU Sideband Changeover 1A71122
Unit
Subunits Sideband Switch Unit 1A71153
ADS Antenna Distribution Switch 2J66076
Subunit Antenna Switch Board 2A71131
This subsystem accepts the blended upper and lower sideband signals from the
sideband modulator and commutates them to the sideband antennas so that the two
signals radiated by opposite antennas simulate a smoothly rotating upper and lower
sideband RF source.
The switch drivers for the sideband changeover switches receive two oppositely phased
30 Hz logic signals from the changeover timing in the timing sequence dividers. The
output levels are DC-shifted, with the new DC levels having increased current capacity
for driving the switching diodes in the RF switches.
The sideband changeover switches are operated by the DC switching signals available
from the switch driver outputs which switch the upper and lower sideband signals
between output terminals.
The switched upper and lower sideband signals from the changeover switches are fed to
the Antenna Distribution Switches where the signals are switched to each antenna in
turn. Two distributors are used, one for the ODD and one for the EVEN antennas.
2-16
H4A71110 SECTION 2
2.2.7 Power Supply Subsystem

This subsystem converts the nominal 24 volts DC input into regulated DC supplies of +5
volts, +15 volts, -15 volts, -40 volts and -45 volts. A DC-to-DC converter followed by
series regulators provide the multiple DC supply voltages required by the rack circuits.
The Voltage Limiter limits the voltage supplied to the RF power amplifiers to 24 volts in
order to restrict the power dissipated in these units. Protection against high current
overload is provided by circuit breakers in the 24 volts lines.
CCB Contactor Assembly 1A71128
DCC DC/DC Converter 1A71129
Subunits Converter Board 1A71169
Voltage Limiter 1A71168
The CCB module contains a power contactor switch, two circuit breakers, control and
protection circuitry. The power contactor switch is activated by logic control from the
CTU module. Protection against high current overload is provided by two circuit breakers
in the 24 volts lines to the transmitter and the controller, monitor and test units.
Protection against reverse polarity connection of the battery supply is provided by power
diodes.
The DCC module operates from the nominal 24 volts DC input and produces regulated
voltages of +5 volts and ±15 volts. It also provides regulated sources of -40 and -45 volts
for the sideband switching circuits.
The DCC module contains two subunits. The first unit contains a pulse width modulated
converter, operating at about 50 kHz and using a ferrite cored transformer. This unit
provides outputs of +8 volts and ±18 volts to the series regulators in the second subunit,
and -40 and -45 volts to the sideband and switching circuits. Regulation of the -40 and
-45 volts sources takes place in the inverter itself, which uses pulse width control to
produce an output which remains substantially constant despite load and input
variations. Protection is included which will shut down the converter if either an output
overvoltage condition or an excessively high current condition is sensed.
The second subunit in the DCC module provides further regulated outputs of +5 volts
and ±15 volts for use by various circuits in the rack. All the regulators are current limited
for protection against short circuits.
The Voltage Limiter limits the voltage supplied to the RF power amplifiers to 24 volts in
order to restrict the power dissipated in these units.
2-17
H4A71110 SECTION 2
2.2.8 Monitor, Controller and Telemetry Subsystem

This subsystem processes a sample of the radiated signal and measures some
parameters of the DVOR signal. If one of the monitored parameters goes out of
tolerance the monitor provides a fault signal to the control unit. This unit controls the
overall operation of the system and determines which condition will cause a malfunction
indication or a station shutdown according to the stored program. The monitor also
measures the phase difference between the 30 Hz AM and FM signals, converts this to
a bearing in degrees, and displays the result on a readout.
Facilities are also included for remote ON/OFF control and remote monitoring of DVOR
functions.
MRF Monitor RF Amplifier 1A71113
Subunits MRF Main Board 1A71141
RF Amplifier 1A71138
MSC Monitor Subcarrier 1A71114
MFI Monitor Filter and Ident 1A71115
MBD Monitor Bearing and Data Acquisition 1A72565
Subunits MBD Main Board 1A72566
CTU Control and Test Unit 2A72550
Subunits CTU Processor Board 2A72552
The monitor subsystem of the DVOR processes a sample of the radiated signal to
determine whether it is within allowable tolerances. The monitored parameters are:
• bearing,
• 30 Hz AM level,
• 30 Hz FM level,
• 9960 Hz subcarrier level,
• antenna fault (notch), and
• ident code.
In addition, the monitor incorporates a fail-safe facility that indicates a fault if the bearing
counter circuits stop functioning. All of the faults signalled by the monitor are processed
by the CTU module, which determines if the beacon should be shut down.
The monitor can be considered as a number of circuit blocks; these are:
• RF amplifier.
• 30 Hz AM channel.
• 30 Hz FM channel.
• Subcarrier channel.
• Bearing measurement.
• Ident channel.
2-18
H4A71110 SECTION 2
The MRF module amplifies and demodulates the RF signal received from the monitor
field antenna. The signal is amplified in a 2-stage RF band-pass amplifier. An AGC
amplifier ensures that the output from the RF stages is kept constant over the specified
operating range. After demodulation the composite audio signal is amplified to give an
output of 0.3 volts peak for each of the 30 Hz AM and 9960 Hz subcarrier signals.
The MRF main board contains a DC/DC converter which obtains its input DC voltage
from the AC Power Supply via a separate contactor assembly. It provides regulated
voltages from ±15 volts to the monitor subsystem, thus making it independent of rack
power supplies.
The MSC module performs the following functions; it:
• separates the subcarrier from the composite VOR signals,
• demodulates the 30 Hz FM on the subcarrier,
• detects a change in level of the subcarrier,
• detects a change in level of the 30 Hz AM,
• detects a change in level of the 30 Hz FM, and
• detects an antenna 'notch' alarm.
The subcarrier is separated from the composite VOR audio signal by a band-pass filter.
This signal is amplified, rectified and applied to a comparator, where a fault is indicated if
the detected level moves outside preset limits. The subcarrier is fed to the frequency
discriminator which recovers the 30 Hz FM signal. Other circuitry examines the
subcarrier for the presence of 'notches' (short duration absences of 9960 Hz) caused by
the failure of an antenna in the array.' The presence of a notch causes a fault condition
to be indicated.
The 30 Hz AM and 30 Hz FM signals are each filtered in two identical low-pass filter
circuits to suppress the third and higher order harmonics before being fed to the sine-to-
square converters in the MFI module.
The MSC module also contains the level comparison circuits for generating a fault
indication if there is a decrease or an increase in the level of the 30 Hz AM or 30 Hz FM
signals. Monitoring of the increase in level is selectable inside the module.
The MFI module contains the sine-to-square converter circuits and the ident detectors.
The 30 Hz AM and 30 Hz FM sine wave signals are each applied to a converter circuit
which generates a square wave signal that is locked in phase to the sine wave input.
The ident detector consists of a band-pass filter and amplifier circuit which recover the
transmitted Morse code ident. An ident fault detector gives a fault indication for
conditions of no code or continuous tone.
The MBD module measures the phase difference between the 30 Hz AM and 30 Hz FM
signals and displays the result on a digital readout in degrees. This readout can operate
in either of two modes:
a. relative mode, which displays the measured bearing error with respect to the
correct monitored radial, or
b. absolute mode, which displays the actual bearing with respect to magnetic
North.
Alarm circuitry examines the contents of the counter at the end of each counting cycle
and a fault condition is indicated if the bearing error exceeds a preset limit. In addition
the monitor incorporates a fail-safe facility that indicates a fault if the bearing counter
circuit stops functioning.
2-19
H4A71110 SECTION 2
The MBD also contains data acquisition circuitry to measure the equipment operational
and internal signal parameters, and a communications interface to be used in a dual
DVOR by the two CTUs to enable them to pass information to each other.
The RCMS Interface on the CTU provides relay outputs and opto-isolated inputs for
interfacing to a telemetry system such as the Remote Control and Monitoring System
(RCMS).
A dedicated serial interface is provided on the CTU to interface to the Remote
Maintenance Monitoring (RMM) system.
The controller is a microprocessor based system which is controlled by a program held
in a read-only memory (ROM).
The input/output expansion unit provides all of the interfacing to the external functions,
such as accepting monitor faults, controlling the rack on/off and recycle sequence,
monitoring the state of the battery charge, giving outputs for telesignalling and for the
panel display.
The display and operator controls are on the front panel of the CTU module and the
interfacing to the remote lines is done by relays in the RCMS Interface Board.
2-20
H4A71110 SECTION 2
2.3 MODULE DESCRIPTIONS
2.3.1 CGD - Carrier Generator and Driver

Components Carrier Generator and Driver 1A71125
Subunits Carrier Oscillator 1A71155
CGD Main Board 1A71156
This module provides two outputs at the carrier frequency; one is a low level CW signal
for sideband phase lock for test purposes, and the other is a 30 Hz amplitude-modulated
carrier for driving the Carrier Power Amplifier.
2.3.1.1 Carrier Oscillator

Drawing 71155-1-01
Performance Supply voltage requirements +15 volts
Data
Output signal level to driver 250 mW (3.5 volts RMS)
Output signal level to generator 125 mW (2.5 volts RMS)
Frequency tolerance ±0.002%
Frequency range 108 to 118 MHz
The oscillator unit has an on-board voltage regulator N2, which supplies 10 volts to
transistors V1, V2 and V3 and to frequency multiplier N1. Transistor V1 operates in a
Colpitts oscillator circuit with the frequency controlled by a series mode crystal G 1,
which has a resonant frequency one-half the station frequency. Transistor V2 operates
as a buffer amplifier between the oscillator and the frequency doubler N1. The output
from N1 is transformer coupled to amplifier V3. Transformer coupling in conjunction with
an impedance matching network L22, L8 and C20 matches into the next amplifier V4.
A similar circuit is used to match V4 to a signal-splitting circuit feeding V5 and V6. Buffer
amplifier V5 provides an output to the sideband generator for phase lock and the output
of buffer amplifier V6 provides the RF drive signal for the Driver Amplifier subunit.
Transistors V7 and V8 operate as a switch which removes the RF drive when a signal
from the CMP module indicates that an alarm condition exists.
2-21
H4A71110 SECTION 2
2.3.1.2 Driver Amplifier

Drawing 71157-2-18
Performance Supply voltage requirements +24 volts nominal
Data
Power output 20 watts maximum
Input level for 20 watts output 3.2 volts RMS nominal
Input return loss 108-118 MHz Greater than 15 dB
Range of modulation control 0-21 volts
The driver amplifier is a 2-stage broadband VHF amplifier which incorporates modulation
facilities. It accepts a low level input signal from the carrier oscillator and amplifies this to
about 3 watts average power, rising to about 12 watts on modulation peaks.
The first stage uses a high frequency power MOSFET V3. R18, R19 and R20 form an
input RF attenuator which is used for isolation purposes. C1, C26, L1. L2, R1 and R2
form an input matching network which matches the FET gate impedance to a nominal 50
ohms input impedance for the amplifier unit. A DC bias voltage is applied to the gate
through R3 and R4.
Components C9, C10, C11. L6 and the stripline section W1 comprise an inter-stage
matching network which transforms the base input impedance of V4 up to 25 ohms at
the drain of the FET. Similarly the impedance transforming network L10, L11, C15, C16
and C17 transforms a load of approximately 8 ohms at the collector of V4 to 50 ohms at
the output.
V1 and V2 operate as modulating transistors to enable either stage of the driver to be
modulated. The modulating signal supplied by the CMP module is applied to the base of
either transistor (pin 5 or 12) and the DC supply for the unit is applied to the collectors
(pins 8 and 15). The DC component superimposed on the modulating signal is
determined by the overall feedback loop; and it is this voltage which maintains the mean
carrier power output constant. L3, L4, L8, L9 and associated bypass capacitors function
as decoupling elements.
Diode V5 in conjunction with C24, C25, R15, R16 and R17 functions as a peak detector,
sensing the voltage at the output of the module. L13 and C30 form a selective network
which reduces second harmonic output.
In the reference carrier chain it is only the second stage which is modulated.
2-22
H4A71110 SECTION 2
2.3.1.3 Power Amplifier

Drawing 71164-3-17
Data
Power output 80 watts peak maximum
Input power for 80 watts output 11 watts nominal
Input return loss 108-118 MHz 15 dB
The Power Amplifier is a broadband VHF amplifier which provides a nominal output
power of 30 watts. The same type of amplifier is used in the CGD module and the CPA
module. In this application in the CGD module, it amplifies the driver amplifier output to 8
watts average power, rising to about 30 watts on modulation peaks. This signal is used
to drive two similar amplifiers in CPA after the input is split. The two power amplifier
outputs obtained are combined in CPA to produce a nominal power of 50 watts.
The power amplifier is a single-stage broadband VHF amplifier using a high frequency
power transistor V1, C1, C4, C18, C17, C19, L1, L2, R1, R2 and R3 form an input
matching network which matches the base input impedance to a nominal 50 ohms input
impedance for the amplifier module. C1 and C18 provide adjustment of the input
impedance of the amplifier. The RF choke L3 provides a DC return path for the base-
emitter circuit of V1.
Components L6, L7, C8, C9, C 10, C 11 and C12 form an impedance transforming
network which transforms a load of about 3 ohms at the collector of V1 to a 50 ohms
load at the output. C11 and C12 provide adjustment for obtaining maximum output from
the amplifier. L4 and L5 and associated bypass capacitors function as decoupling
elements.
Diode V2 in conjunction with C15, C16, R8, R9 and R10 functions as a peak detector
sensing the voltage at the output of the module.
2-23
H4A71110 SECTION 2
2.3.1.4 CGD Main Board

Drawing 71156-3-01
Data ±15 volts nominal
Modulating signal level output:
AC component 1.4 volts peak-to-peak
DC component 3.0 volts
Protection voltage from power 3.0 volts
amplifier
Gate bias voltage 5.5 volts nominal
The CGD Main Board contains circuitry which amplifies the modulation signal and
transfers the signal to the second stage of the Driver Amplifier. The first amplifier stage
is not modulated but supplied with a fixed DC level. Circuitry supplies a preset gate bias
to the driver FET stage. Protection functions are included which protect both stages
against excessive current and power output.
The input from the power amplifier peak detector is applied via XMA:27, through a link
on the rear connector to XMA:29 or XMA:30, and then to the inverting input of voltage
comparator N1. The comparator threshold is set by RV1 and the output of N1 is high.
Under a fault condition in which the power amplifier is delivering excessive power output,
the threshold will be exceeded and the output of N1 will go low causing the gate bias to
V3 on the drive board to shut off. The diode chain V2, V3 and V4 provides a temperature
compensated reference voltage for N1.
Input XMA:32 receives the modulating signal including a DC component from the CMP
module; this signal is amplified by V11 and V12 and the output at XFB:12 is transferred
to the base of the modulation transistor V2 in the second stage of the Driver Amplifier.
The supply current applied to the same stage is monitored across R21. If the current
exceeds the turn-on threshold of V10, the output of V11 is reduced, which decreases the
drive supplied by the Driver Amplifier.
Stage 1 amplifier has a fixed DC bias applied to V9 which causes the amplifier to deliver
a fixed DC voltage to stage 1 of the Driver Amplifier. The output at pin 15 is a nominal 24
volts with the same current protection circuitry as used in the second stage amplifier
block.
The DC component derived from the output sensing level control is transferred to the
driver stage as part of a feedback loop which ensures that the carrier is radiated at a
constant power.
2-24
H4A71110 SECTION 2
2.3.2 CPA - Carrier Power Amplifier

Drawing 71127-3-22
Components Carrier Power Amplifier 1A71127
Subunits Power Amplifier (2) 1A71164
Splitter Combiner 1A71166
This module amplifies a nominal 8 watts signal from the CGD module to a nominal 50
watts level. The input signal from the CGD module is split two ways by a passive power
splitter and the signals are amplified to a nominal 30 watts by separate power amplifiers
of a type identical to that used in the CGD module. The two outputs are recombined in a
passive combiner to give a nominal 50 watts output.
2.3.2.1 Power Amplifiers

Drawing 71164-3-17
Performance Supply voltage requirements 22 to 27 volts
Data
Power output 30 watts
Input level 4 watts nominal
Input return loss 108-118 MHz 15 dB minimum
The Power Amplifier is a broadband VHF amplifier identical to that used in the CGD
module. It accepts the power output from one port of the power splitter and amplifies this
up to a nominal 30 watts.
The power amplifier is a single-stage broadband VHF amplifier using a high frequency
power transistor V1, C1, C4, C17, C18, C19, L1, L2, R1, R2 and R3 form an input
matching network which matches the base input impedance to a nominal 50 ohms input
impedance for the amplifier module. The RF choke L3 provides a DC return path for the
base-emitter circuit of V1.
Components L6, L7, C8, C9, C10, C11 and C12 form an impedance transforming
network which transforms a load of about 3 ohms at the collector of V1 to a 50 ohms
load at the output. L4 and 15 and associated bypass capacitors function as decoupling
elements.
Diode V2 in conjunction with C15, C16, R8, R9 and R10 functions as a peak detector,
sensing the voltage at the output of the module. This facility is not used in the CPA
module.
2-25
H4A71110 SECTION 2
2.3.2.2 Splitter/Combiner
Drawing 71166-3-18
Performance Centre frequency 113 MHz
Data
Input return loss 25 dB minimum
Isolation between outputs 26 dB minimum
Insertion loss 3.0 to 3.4 dB
Maximum difference between 0.2 dB
outputs
Insertion phase shift 95 degrees ±2 degrees
The Splitter/Combiner consists of two sections; one is used for splitting the signal into
two equal signals and the other is used to recombine the signals. Each section contains
a Wilkinson combiner or splitter which consists of two quarter-wavelength 70 ohms
coaxial lines with imbalance resistors R3 and R4 connected across the input of the
combiner and the output of the splitter to dissipate any imbalance power.
The combining unit contains an imbalance detector consisting of transformer T1, R1, R2,
V1, C1 and C2. The primary winding of the transformer T1 is connected between the two
input ports and the secondary is connected to a peak detector. Any amplitude or phase
imbalance between the output signals from the power amplifiers produces an output
from the transformer and hence a DC output from the detector. If this DC output exceeds
a preset threshold level a protection circuit in the CMP module operates and the
transmitter is shut down.
2.3.2.3 Interface Board

Drawing 71165-3-12
The Interface Board distributes the 24 volts supply to each of the Power Amplifiers whilst
providing a facility for inserting a current meter to measure the current in the individual
power amplifiers during tuning. The output of the imbalance detector is also available
from this unit for connection to the CMP module.
2-26
H4A71110 SECTION 2
2.3.3 CDC - Carrier Directional Coupler

Performance Supply voltage requirements ±15 volts
Data
Carrier power 200 watts maximum
RF forward coupling 24.7 dB nominal
RF directivity 30 dB minimum
Detected output for 50 watts 3.9 volts DC nominal
Calibrated output for 50 watts 3.0 volts DC
The Carrier Directorial Coupler comprises two sections: an RF coupler body and a
detector board.
2.3.3.1 RF Coupler Body

Drawing 71124-3-40
The RF coupler body is a machined part containing a central transmission line (the main
line) and two coupled lines. Each coupled line has a forward port (connectors XFD and
XFF) and a reverse port (connectors XFC and XFE), to give a sample of the forward and
reverse power on the main line (connectors XFA and XFB).
In normal operation, power from the carrier transmitter travels from input connector XFB
to the output at connector XFA.
Provided that the coupled lines are correctly terminated, a carrier sample will be present
at each forward port of the coupler. One of these (at XFE) is detected to provide carrier
envelope feedback, and the other (at XFC) is used for carrier/sideband phase control.
2.3.3.2 Detector Board

Drawing 71167-3-02
The Detector Board (type 1A71167) is connected to the forward and reverse ports of one
of the coupled lines in the coupler body. This board contains two identical detector
circuits, to give a signal which accurately represents the level and the envelope of the
RF samples at input connectors XMF (forward) or XME (reverse).
Taking the circuit on XMF as an example, the RF input is terminated by resistors R1 and
R2 and detected by hot-carrier diode V1. The circuit comprising N1 a, V2 and associated
resistors, compensates the offset and the temperature drift of detector diode V1, so that
the output from N1 accurately reproduces the carrier level and the modulation envelope
of the RF signal at the input.
The forward output at XMG:1 is used for carrier transmitter control, and the forward
output at XMG:6 is set by RV1 to give a calibrated signal for carrier power metering. The
reverse signals at XMG:5 and XMG:9 are likewise used for control and metering
respectively.
2-27
H4A71110 SECTION 2
2.3.4 CMP - Carrier Modulation and Protection

Components Carrier Modulation and Protection 1A71123
The transmitter uses 'low level' modulation combined with envelope feedback to achieve
good linearity. The RF modulation is carried out in the driver unit, at a low power level.
This type of modulation on its own has poor linearity. To compensate for this, the
transmitter output is detected (at the output directional coupler) and fed back to an error
amplifier which compares this signal with the desired modulation. The difference signal
is used to modulate the RF signal. This method of amplitude feedback ensures good
linearity and stability of the carrier modulation, which is especially important for the 30
Hz reference.
The same feedback loop is used to maintain the transmitter power output at a constant
level by comparing the DC component of the feedback signal with a DC reference
voltage in the error amplifier. The error voltage, when applied to the modulation stage,
changes the gain of the stage thus correcting for the original change in power output.
Modulation signals for the transmitter comprise the 30 Hz reference sine wave, the 1020
Hz keyed ident tone, and the voice channel input. These are combined before being
applied to the modulation comparator.
Forward and reverse signals from the directional coupler at the transmitter output are
compared with preset levels to give an alarm if there is either an increase or a decrease
in forward power or an increase in reverse power. This alarm will cause a shutdown of
the transmitter by removal of RF drive. Protection is also provided by means of an
imbalance detector, which senses a large difference in power being applied to the
combiners. This prevents the power amplifiers from being overdriven should a fault
occur in either a power amplifier or in the combiners themselves.
The voice channel input may be taken from a high level line input or a low level
microphone input. The signal is amplified and fed to a compression amplifier, where the
signal is held level to within 3 dB for input variations of more than 30 dB. The
compressor may be switched out of circuit if not required. A front panel LED indicates
when the compressor is in circuit. Active filtering limb the bandwidth of the voice channel
to a range of 300 Hz to 3 kHz.
2-28
H4A71110 SECTION 2
2.3.4.1 CMP Main Board

Drawing 71123-1 -01
Data
30 Hz reference sine wave 20 volts peak-to-peak
Forward power feedback input 3.9 volts nominal
Reverse power feedback input for 3.9 volts nominal
100% reverse power
VSWR trip point 2.0:1 nominal
Forward power trip points 40 watts or 60 watts
Microphone input level -50 dBm nominal
Line input level -20 dBm nominal or 0 dBm
nominal
Compression range 30 dB for less than 3 dB
variation
Voice channel frequency range 300 to 3000 Hz ±3 dB
Ident tone frequency 1020 ±50 Hz
This module provides low level modulation signals to the transmitter driver and senses
carrier forward and reverse power and gives an alarm if either is outside allowable limits.
Voltage regulator N12 provides a DC reference for the carrier level. Subcarrier (CVOR
only), voice and ident inputs are switched in or out via test switches S3, S4 and S5
which in turn control the analogue switch D8. 30 Hz AM is controlled by switch S2, and
transmitter on/off by switch S1. Operational amplifier N13:1 acts as a buffer amplifier for
subcarrier, voice and ident inputs. Operational amplifier N13:7 is the summation
amplifier for 30 Hz AM, N13:1 and DC carrier level signals. Transistor V24 shorts the
modulation signal to ground if an alarm condition arises. Operational amplifier N14 is the
error amplifier for the carrier envelope feedback loop. The output goes to the Driver
Amplifier in the CGD module.
Voltage regulator N11 sets the alarm level reference with a DC voltage for the
comparators. The alarm circuits on this board process signals from forward and reverse
power sensors in the Carrier Directional Coupler and the imbalance detectors in the
Splitter/Combiner units. Two of the imbalance comparators N10:2 and N10:13 sense the
outputs from the individual power amplifiers using input signals via XMA:16 and XMA:17.
The remaining imbalance detector N10:14 senses the summed 100-watt signals from
the rack-mounted Splitter/Combiner in a 100-watt rack using an input signal via XMA:18.
Forward power is sensed by comparator N15:13 (level too low) and N15:14 (level too
high). One half of the dual timer N9 gives a 10-second delay to prevent any alarm
condition triggering on spurious signals.
Amplifiers N16:1, N16:7, N15:2 and timer N9:9 comprise a variable time delay circuit for
reverse power sensing. The reverse power threshold is determined by N15:2 which turns
off V17 to allow N9 to start timing. N16:1 and N16:7 apply a voltage to N9, the
magnitude of which is dependent upon the incoming reverse signal level. This is applied
to N9, so that for a moderate VSWR, a delay time of about 10 seconds occurs. For a
high VSWR, however, the voltage applied to N9 causes it to time out in less than 50
milliseconds.
2-29
H4A71110 SECTION 2
The board contains line and microphone input amplification, filtering and ident oscillator.
Line input goes to amplifier N1:7 which acts as a balanced line receiver. N1:1 acts as a
buffer amplifier with gain determined by the strapping used in the feedback loop to adjust
to different input level requirements. Amplifier N4:7 acts as an amplifier for microphone
level input signals. Switching between the two inputs is done automatically by the
insertion or withdrawal of the microphone plug; inserting the microphone plug disables
the line input
The position of switch S7 determines whether the signal from amplifier N3:1 is directed
to the compression circuit or is fed directly to the output buffer amplifier. The
compression circuit operates by having a FET acting as a variable resistance element
which is controlled by a feedback signal from the output of the compression circuit. The
resistance control is such as to keep the level at the output of N2 substantially constant.
With the switch in the compressor position, the signal is attenuated by R8 and R9 before
being applied to the level control element V8. The signal from V8 is amplified by N2:7,
then split with one output going to the output buffer stage N3:7 and the second output
acting as a feedback signal.
This signal is rectified by V5 as well as a small proportion of the signal being directed to
V8 substrate to improve the linearity of the device. Level amplifier N2:1 provides the
control voltage for the control element V8. Transistor V7 disables the compressor when
switch S7 is in the bypass position.
The output of amplifier N3:7 is applied to the first stage of the 24 dB/octave voice filter.
N5:7 and N5:1 are identical low-pass active filters with a 3 kHz cut-off frequency. The
following stages N6:7 and N6:1 are identical high-pass active filters with a 300 Hz cut-off
frequency. The output from the filter is applied to a level clipper followed by a voice level
control RV9.
The 1020 Hz keyer oscillator N8 generates a triangular output waveform which is
amplified by N7. This waveform is converted to a sinusoidal waveshape by passing the
signal through a 6 dB/octave passive filter followed by a 12 dB/octave low-pass active
filter N7:7. The output from the filter is applied to the ident level control RV8.
2-30
H4A71110 SECTION 2
2.3.5 SGN - Sideband Generator

Components Sideband Generator 1A71121
Subunits SGN Main Board 1A71146
Phase Detector 1A71147
Sideband Oscillator (2 off, 1A71150
designated Upper and
Lower)
The upper sideband (USB) and lower sideband (LSB) signals are generated by two
voltage-controlled crystal oscillators, the frequencies of which are controlled by two
variable capacitance diodes.
Control voltages for the oscillators are derived from two phase-control circuits, each of
which compares the phases of two 9960 Hz signals. The first of these is the 9960 Hz
subcarrier derived from the master clock oscillator; the second is derived by mixing
samples of the individual sideband signals with a sample of the carrier signal to produce
a beat frequency of 9960 Hz. This system phase locks the high level sideband signals to
the output of the carrier transmitter. To enable the sidebands to have the correct phase
relationship with respect to the carrier, phase delay circuitry has been included to en
able the phase of the reference 9960 Hz to one of the control circuits to be adjusted over
a wide range. For test purposes, the sidebands may be locked to a signal from the
carrier oscillator, to allow the sidebands to be generated when the carrier transmitter is
not operating.
2-31
H4A71110 SECTION 2
2.3.5.1 Phase Detector

Drawing 71147-3-01
Data
Reference carrier sample level 2.8 volts RMS
Upper and lower sideband sample 0.3 volts RMS
level
USB/LSB phase output 0.8 volts peak-to-peak
Signal generator input level 7.6 volts peak-to-peak for
30% modulation
Modulated RF output level Greater than 0.12 volts
The input signals to the Phase Detector circuits are sampled from the outputs of the
reference carrier and the two sideband amplifiers. The signals from the reference carrier
is split two ways by transformer T1; each signal goes to separate sideband balanced
mixer transformers T2 and T3. A sample of each sideband is injected into the balanced
mixer circuits at the junctions of C2 and C3 (USB) and C5 and C6 (LSB). The resulting
9960 Hz beat frequency from each mixer is available as an input signal for the phase-
lock detector circuits on the SGN Main Board.
Variable resistors RV1 and RV2 balance the mixers so that the 30 Hz modulation signal
introduced into the mixers by the reference carrier is cancelled out at the output terminal
XMP:1.
For test purposes the sidebands can be locked to the carrier oscillator signal by
switching S1 to the TEST position. The switch changes over the input to transformer T1
from the transmitter output sample to the carrier oscillator signal.
A test modulator is included to allow a modulated VOR RF signal to be generated for
monitor calibration. The diode balanced modulator U1 is biased by current through R2 to
operate as an amplitude modulator. This modulator enables DC coupling to be used
between the output of a VOR signal generator and the modulator, thus avoiding the
introduction of phase shift to the 30 Hz AM component. The source of RF carrier signal
for the modulator is supplied directly from the carrier oscillator via switch S1. This facility
only functions when S1 is in the NORM position.
2-32
H4A71110 SECTION 2
2.3.5.2 SGN Main Board

Drawing 71146-1-28
Data
Master clocking frequency 3.1104 MHz,
15 volts peak-to-peak
Variable phase control range (USB) 0 to 480 degrees
coarse - 15 steps of 30
degrees/step
fine - 15 steps of 2.3
degrees/step
Preset phase control range (LSB) 0 to 480 degrees
coarse - 15 steps of 30
degrees/step
fine - 15 steps of 2.3
degrees/step
Sideband control to TSD and SMA 2.5 to 11.5 volts
Input from phase detector (USB and 0.8 volts peak-to-peak
LSB) nominal
Frequency control voltage range ±9 volts
(USB and LSB)
The SGN Main Board controls the phase of the two sidebands relative to the carrier and
ensures that these signals quickly acquire phase-lock when the beacon is first switched
on. The board contains the 9960 Hz generator, digital phase shifters and phase
detectors for each sideband, and sideband level control circuits. A block diagram of the
board is shown in Figure 1A.
The master clocking frequency 3.1104 MHz is supplied to SGN via connector XMA:2
from the TSD module. The signal is buffered by D2:4 and applied to divider D1:1
(divided by 2). The output is the clock frequency for the fine phase-adjust shift registers
D6 and D8 via three delay gates D2:2, D2:6 and D2:15. The same clock frequency is
applied to divider D3:12 (divided by 13), the output is the clock frequency for the coarse
phase-adjust shift registers D5 and D7 as well as for the divider 04:12 (divided by 6).
The output is divided by 2 in D1:15 to give the sideband reference frequency of 9960 Hz.
This signal is applied as an input to both shift register chains D5, D6 and D7, D8. The
shift registers supply 1 to 16 steps of delay in each register; the smallest increment of
delay is determined by the clock frequency.
The upper sideband delay D5, D6 is controlled by the front panel switches S2 and S3
labelled COARSE and FINE. COARSE provides 30 degrees of delay per step and FINE
2.3 degrees of delay per step. The lower sideband delay is controlled by the preset
binary switch S1 on the board which only comes into operation when the sideband
phase switch S4 is in the TEST position. In practice only about 180 degrees of phase
delay is required in the lower sideband chain.
Only the operation of the USB circuit is described below. The LSB circuit is the same
except for component references.
In the phase lock loop section, amplifier N2 functions as a nulling amplifier which
maintains zero DC offset at the input to the sample and hold circuit V2. Amplifier N1
provides two levels of gain controlled by V1. Under search conditions V1 is cut off and
N1 operates as a unity gain voltage follower, but when the loop is frequency locked V1 is
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H4A71110 SECTION 2
biased hard on and V1 reverts to a gain of four thus providing increased loop gain under
lock conditions. R1, C10 is a filter intended to keep switching transients in the sample
and hold circuit from causing errors in the output. The sampling pulse is provided by V3
and its output circuit using the 9960 Hz reference phase signal from D1:15. FET V2
charges the sample and hold capacitor C6 for a period of 1 microsecond at a repetition
rate of 9960 Hz.
The primary function of N3:7 with its feedback components is to operate as a loop filter
for the complete USB phase lock loop.
When the loop is frequency and phase locked the sampling pulses will occur at the zero
crossings of the sine wave input to the sample and hold detector. This will produce a DC
output which is very close to zero; refer to Figure 2-5 (1).
When the loop is in frequency lock but not in phase lock then the sampling pulses will
not occur at the zero crossing but at some other point on the sine wave; refer to Figure
2-5 (3). This condition will produce a resultant DC voltage from the sample and hold
detector which will then cause the VCO to change such that phase lock takes place, as
shown in Figure 2-5 (2).
The output of N3 supplies the DC voltage which controls the varactors and therefore the
frequency and phase of the sideband oscillator.
When the loop is out of lock, the search ramp generator is activated (N4 and V4-V8) and
the UNLOCK indicator lights. An 'unlock' condition results in an AC signal occurring at
N3:1 which is detected by V11. This causes the output of N4:1 to swing negative, thus
activating the search ramp generator. When in the search mode, N3:7 operates as an
integrator controlling the rate of charge of the ramp. The excursion limits of trigger N4:7
and transistors V4-V7 switch the voltage to integrator N3:7 between +12 volts and -12
volts to generate the ramp; refer to Figure 2-5 (3).
N41 provides a reference voltage for the sideband power and balance preset
adjustments. With test switches S5 and S6 in the ON positions the sideband-balance
adjust voltages are buffered by N40 and applied to the TSD and SMA modules.
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H4A71110 SECTION 2
Figure 2-5 SGN Phase Control Waveforms
2-35
H4A71110 SECTION 2
2.3.5.3 Sideband Oscillators

Drawing 71150-2-33
Data
Oscillator frequency - USB fc+9960 Hz
- LSB fc-9960 Hz
Frequency pull-in range ±2.4 kHz
Frequency control voltage range ±9 volts nominal
Output voltage into 50 ohms 3.5 volts RMS
Crystal frequency tolerance 0.002%
The upper and lower sideband voltage-controlled crystal oscillators are identical to the
carrier oscillator (see Section 2.3.1.1 for circuit description) except for the inclusion of
varactor frequency control diodes and associated components in series with the crystal.
The crystals used in the sideband generators differ in frequency from that used in the
carrier oscillator by +9960 Hz (upper sideband) and -9960 Hz (lower sideband), and only
a single buffered output stage is provided.
Control voltages for the oscillators are derived from the SGN Main Board described in
Section 2.3.5.2. The range of control voltage available is capable of pulling the crystal
frequency by ±2.4 kHz.
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H4A71110 SECTION 2
2.3.6 SMA - Sideband Modulator and Amplifier

Components Sideband Modulator and Amplifier 2A71126
Subunits Driver Amplifier (2) 1A71157
Sideband Directional 1A71161
Coupler (2)
Modulator (2) 1A71159
Level Control Board (2) 1A71163
Sideband Isolator (Wide Band) (2)
Filter (Low Pass) (2)
The outputs from the USB and LSB oscillators are amplified to approximately 5 watts by
the sideband Driver Amplifiers. These units are identical to the driver amplifier used in
the CGD module. The peak power level is controlled by a feedback circuit which varies
the voltage applied to the modulation stage.
The output of the Driver Amplifier is fed through an Isolator and Directional Coupler. The
Isolator provides isolation between the modulator and amplifier and also provides a
satisfactory impedance match for the amplifier under all loading conditions. The
Directional Coupler provides an RF sample of the amplified sideband signal which is fed
back and used by the phase control circuit to phase lock the loop.
The Driver Amplifier output is sensed by a peak detector. If the rectified signal increases
above a preset level, a protection circuit is activated and the bias to the FET stage of the
amplifier is removed.
Modulation of the sidebands by a sine-shaped blending function waveform takes place in
the PIN diode absorption modulator. In this modulator, the instantaneous level of the
sidebands is controlled by varying the direct current through two PIN power diodes. A
high degree of modulation linearity is obtained by using a feedback circuit which
compares the detected envelope of the RF output with the desired modulating signal.
The derived error signal is used to modulate the PIN diode.
Two modulated outputs are produced, one for the ODD antennas and one for the EVEN
antennas.
2.3.6.1 Driver Amplifiers

Drawing 71157-2-18
Performance Supply voltage requirements 24 volts
Data
Power output 10 watts nominal
(20 watts maximum)
Input level 3.2 volts RMS (0.2 watts)
Input return loss, 108 to 118 MHz Greater than 15 dB
Range of modulation control 0 to 21 volts
The Driver Amplifier is a broadband VHF amplifier which incorporates modulation

facilities. It accepts a low level signal from the sideband voltage-controlled oscillator and
amplifies this to a nominal 10 watts (depending on sideband level).
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H4A71110 SECTION 2
Except for operating levels, the SMA Driver Amplifiers are identical to the Driver
Amplifier used in the CGD module, and as described in Section 2.3.1.2. However, as
used in the sideband chain, it is only the first stage which is modulated.
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H4A71110 SECTION 2
2.3.6.2 Sideband Isolators and Low Pass Filters

a. Sideband Isolators (Wide Band).
Performance Frequency range 108 to 118 MHz
Data
Insertion loss 0.5 dB maximum
Isolation 18 dB minimum
Impedance 50 ohms nominal
VSWR 1.25:1 maximum
Power input 25 watts maximum
Temperature range -10 to +70 degrees C
Connectors (input and output) BNC female
The sideband isolator is a non-reciprocal device which has low insertion loss when RF
energy passes in one direction and high attenuation when the energy direction is
reversed. Because of its high degree of isolation, the isolator prevents undesirable
intermodulation products from being generated in the amplifier by the non-linear input
characteristics of the modulator. It presents a satisfactory impedance match to the
Sideband Driver Amplifiers under all conditions of loading.
b. Filters (Low Pass).
Performance Cut-off frequency 125 MHz
Data
Insertion loss 0.6 dB max to 118 MHz
Attenuation 30 dB minimum at 216 MHz
and above
Power rating 25 watts
VSWR 1.5:1 up to 120 MHz
The low pass filter provides attenuation for harmonics of the VHF sideband signal which
may be generated in the Driver Amplifier.
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H4A71110 SECTION 2
2.3.6.3 Sideband Directional Couplers

Drawing 71161-3-27
Performance Coupled output level 300 mV RMS for 4 watts
Data output
Directivity 18 dB
Peak detector output 2.7 volts for 4 watts output
Each Sideband Directional Coupler in the upper and lower sideband chains contains a
directional coupler which supplies an RF sample to the phase detector circuit for phase
locking each sideband loop. Each unit also contains a peak detector which supplies an
output to the CTU for the purpose of monitoring sideband power. Each coupler consists
of a length of coupled transmission line W1 which has 22 dB coupling loss between the
primary and the secondary line. The output signals from the forward and reverse ports of
the secondary line are fed to the output connectors XFB and XFC through resistive
networks which terminate the line and reduce the signal level to a nominal 300 mV with
4 watts in the primary line.
The peak detector and resistive divider circuit provide a signal for the CTU to enable
each levelled sideband power output to be monitored.
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H4A71110 SECTION 2
2.3.6.4 Sideband Modulators

Drawing 71159-3-27
Performance RF input 5 watts CW nominal
Data
Peak power output, ODD and EVEN 4.0 watts typical
Output, forward port of coupler 1.6 volts peak
for 4 watts output
Output, reverse port of coupler 0.5 volts typical
for VSWR 2.0:1
PIN diode bias voltage 6.8 volts DC
Output, automatic level control 5.2 volts nominal
An input signal of about 5 watts is fed to the Sideband Modulator by the Driver Amplifier.
The CW signal is modulated by PIN diodes V1 and V2 with a signal derived from the
Level Control Board and shunt fed to the diodes through chokes L4 and L5. A fixed bias
current is supplied to the PIN diodes via choke L3.
The PIN diode appears to the RF signal as a resistance, the value of which is controlled
by the DC through the diode.
The forward and reverse waveforms of the ODD and EVEN signals are sampled by two
coupled line directional couplers W1 and W2 and then rectified. The sampled forward
signal forms part of a negative feedback loop which linearises the modulated sideband
signal. The sampled reverse signals are supplied to the Level Control Board as inputs to
a protection circuit.
Inductors L1 and L2 are adjusted to tune out the residual reverse biased capacitance of
each PIN diode.
A peak detector circuit comprising V3, R1, R2, R3, C4 and C6 rectifies the signal at the
input to the modulator. The detected signal is supplied to an amplitude level control
network which maintains a constant peak level at the input to the PIN diodes.
The outputs of the modulator feed the ODD and EVEN antenna circuits. The phase of
the envelopes of the modulation from the two outputs differ in phase by 90 degrees as
produced by the blending function generator in the TSD module. The RF phase at the
two outputs is the same.
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H4A71110 SECTION 2
2.3.6.5 Level Control Board

Drawing 71163-2-20
The Level Control Board contains ODD and EVEN sideband modulation amplifiers each
having an envelope feedback circuit. It also contains the ODD and EVEN reverse power
alarm circuitry as well as an RF level feedback circuit. Amplifier N1:1 (N1:7) provides
compensation for the thermal drift of the ODD (EVEN) forward power detector diode V4
(V5) in the modulator by means of a diode V2 (V3) in its feedback loop. The output goes
to comparator N2 (N3) which sums the fed-back signal with the ODD (EVEN) modulation
drive from the blending function generator. The derived error signal is used to drive the
PIN diodes; refer to Figure 2-6. Voltage follower N4 supplies buffered outputs of the
blending function signal to test points on the front panel.
Voltage follower N8 receives a signal from the peak detector in the Directional Coupler
and provides a buffered output for the Test Unit.
Amplifier N7 is supplied with a signal from the peak detector V3 at the input to the
sideband modulator which is compared with the sideband level reference set by RV4.
The output drives the collector modulator of the FET stage in the Driver Amplifier, via
transistor amplifier V12 and V13. Amplifier V15 and V16 provides a fixed limited voltage
to the collector modulator of the second stage of the Driver Amplifier. Transistors V11
and V14 provide peak current limiting for protection of the Driver Amplifier.
The circuit block containing N5, N6, D2 and D3 is used in conjunction with the
corresponding circuits in the second SMA module to provide a composite alarm system.
These circuits detect the level of reverse power on the sideband feed system and will
generate sideband alarm signals from the monostable D1. D1:6 generates an alarm if a
single antenna fails and D1:10 generates an alarm if a pair of diametrically opposed
antennas fail. The outputs from the alarm circuits are supplied to gates D2 and D3. N5 in
conjunction with diodes V5 and V6 in the feedback loops provide compensation for the
ODD and EVEN reverse power detectors V6 and V7 in the modulator. The outputs are
directed to the reverse power alarm circuit comparators N6.
N9:7 in conjunction with zener V22 and diodes V17, V18 and V19 provide a
compensated bias voltage to the FET stage in the driver amplifier. Comparator N9:1
provides a protection circuit which operates by removing the bias from the FET stage
when an excessive output level is detected from the Driver Amplifier.
2-42
H4A71110 SECTION 2
Figure 2-6 SMA Blending Function Modulation Waveforms
2-43
H4A71110 SECTION 2
2.3.7 TSD - Timing Sequence Generator

Components Timing Sequence Generator 1A71118
Subunits TSD Main Board 1A71145
The TSD module contains the master clock circuitry from which is derived all the timing
signals for synchronising the switching and timing functions in the DVOR beacon. The
output from a crystal controlled oscillator is frequency divided in a number of stages to
produce the timing signals for generating the 30 Hz reference frequency, the 9960 Hz
sideband modulation frequency, the blending function waveforms for the sideband
modulator, and the drive signals for the sideband changeover switch and antenna
commutation subsystems.
The 720 Hz blending function waveforms are generated digitally from sine values stored
in ROM; these values are decoded to provide the blending function outputs to the upper
and lower sideband modulators.
The ODD and EVEN signal changeover system is driven by simple switching
waveforms, whereas the antenna commutation is generated by binary coded decimal
signals.
The Switch Board provides facilities for bearing (error curve) tests and static selection of
blending function and sideband antennas.
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H4A71110 SECTION 2
2.3.7.1 TSD Main Board

Drawing 71145-41 -01
Performance Supply voltage requirements +15 volts, +5 volts
Data
Outputs (all 15 volts logic level):
To SGN 3.1104 MHz
To RPG 622.08 kHz
207.36 kHz
12.96 kHz
30 Hz
To ASD - ODD and EVEN
To SCU - ODD and EVEN 30 Hz
To front panel test sockets:
XA1 Master clock
XA2 720 Hz
XA3 30Hz
XA4 30 Hz trigger
D1:1 with crystal G1 and associated components generate the 3.1104 MHz master
clock; C3 permits small adjustments to the clock frequency. D1:12 buffers the clock into
three other buffer sections, D15:8 to the SGN module, D15:6 to test socket XA1 and
D1:4 to dividers within the TSD module. The clock is divided by five in D2, which gives
the 622.08 kHz for RPG via buffer D14:2, and via buffer D15:4 it drives D5 (divide by 3)
which gives the 207.36 kHz for RPG. This is further divided by 8 in D4 and then by 2 in
D28:15, which then gives the 12.96 kHz to RPG. This is divided by 9 in D8, which
provides a 1440 Hz clock for the 60 Hz odd and even reset set-up generators D30:13
and D31:1 respectively, which in turn drive D21:1 and D20:1 reset generators; see
Figure 2-7.
D21:1 and D20:1 generate reset pulses (0.7 milliseconds wide at a 60 Hz rate) to
synchronise commutation counters D9 and D10. D21:15 and D20:15 provide the 30 Hz
drives, of the correct phase, for the sideband changeover switches. Each stage gives a
delay of 7.5 degrees (at 30 Hz) to the 30 Hz and 30 Hz inverted from D29. The 30 Hz is
derived from D6:12 and D29 and may be delayed in 15-degree increments by D7 when
in the BEARING TEST mode. In the NORMAL mode, D7 does not introduce any delay to
the 30 Hz signal. The 1440 Hz is further divided by 2 in D28:1 to provide 720 Hz inputs
for the preload pulse generators D22 and D23 for the blending function generators. This
720 Hz also goes to the 720 Hz delay generators D30:1 and D31:13 giving a delay of
two clock cycles at 77.76 kHz. This delay compensates for the 25 microseconds delay
introduced by the blending function filter; see Figure 2-8.
The outputs of D31:12 and D31:13 synchronise the odd and even reset generators
D21:1 and D20:1. The 720 Hz also provides the clock for down counter D1 3. The clocks
for down counters D11 and D12 are supplied from the delayed 720 Hz. The odd and
even commutation counters D9 and D10 clock 720 Hz drive to the D17 output buffers
and antenna switch drive. These counters each have a maximum count of 12 as they
are reset at a 60 Hz rate. The blend function generator is clocked by 77.76 kHz which
drives the counters D33, D34, D38 and D39. The counters sequentially address the
ROM, which has stored sine values, causing it to give to the digital-to-analogue
converter (DAC) digital values corresponding to points on a sine wave. The ROM
2-45
H4A71110 SECTION 2
contains 216 addresses for sine values, but in the TSD application only the even
addresses are used, giving 108 available data values.
The DAC produces an analogue version of these digital values; 108 steps generate a
half sine wave at the converter output. The output of the two ROMs D32 and D35 are
latched by D46, D47 and D48, D49 respectively before being applied to the digital-to-
analogue converters. The amplitude of the output is fixed by a voltage reference from
the SGN module. Amplifiers N1 and N2 provide some filtering of the step frequency
ripple via the capacitor in the feedback path. The output of the module is a negative half-
sine wave of 720 Hz. Two pairs of outputs are provided, for upper and lower sidebands.
The blending function generator waveforms are shown in Figure 2-9.
Figure 2-7 TSD Timing Waveforms
2-46
H4A71110 SECTION 2
Figure 2-8 TSD Timing Waveforms
2-47
H4A71110 SECTION 2
Figure 2-9 TSD Blending Function Generator Waveforms
2-48
H4A71110 SECTION 2
2.3.7.2 Switch Board

Drawing 71149-2-30
Performance Lines XMB:7, XMC:11 and XMC:19 revert to a low level when the
Data respective switches S1 1, S10 and S9 are switched to the output
corresponding to the coded binary word on the input lines. These
lines are high for all other conditions.
The output lines controlled by all other switches give a 15 volts
level when in the active condition but are open-circuit otherwise.
This board provides facilities for bearing (error curve) tests, and static selection of
blending function and sideband antennas.
Blending function selection is done by S1, which connects to gates D42 on the TSD
Main Board. It stops the dynamic generation of the blending function and gives DC
voltages corresponding to the EQUAL amplitude, ODD MAXimum or EVEN MAXimum
positions on the blending function waveform.
Switch S11 selects bearing delay, in 15-degree increments, for error curve testing. D1, in
conjunction with D13 on the Main Board, forms a circuit for converting the 12-position
switch S11 to a binary value. When in the test mode, D13 will count down, and its count
value will be decoded by D1. When the decoded value reaches the current switch
position, counter D13 is inhibited, thus holding the binary value of the switch. This value
is preloaded into the delay counter D7 on the Main Board.
The antenna selectors S10/D2 and S9/D3 work in the same way using D11 and D12 on
the Main Board.
Switches S5 and S6 force sideband changeover generators D21:15 and D20:15 to a
fixed condition for static switching of the sideband RF switches.
The unit is designed in such a way that if the Switch Board is removed the TSD module
will continue to operate normally.
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H4A71110 SECTION 2
2.3.8 RPG - Reference Phase Generator

Components Reference Phase Generator 1A71119
The RPG module contains the 30 Hz reference phase adjustment, the 30 Hz reference
sine generator, and the ident keyer. The 30 Hz reference phase adjustment is provided
by switched digital phase delay circuits. The delay introduced is used for station bearing
adjustment, to allow the beacon to be correctly aligned with magnetic North. The inputs
to the digital delay circuits are the 30 Hz square wave and clock signals from the TSG
module.
The 30 Hz reference sine wave is generated by a digital waveform generator comprising
a counter, a read-only memory (ROM), and a digital-to-analogue converter (DAC).
The ident keyer consists of a 23-stage demultiplexer, which is scanned by the output of
a 5-stage counter. The output of the demultiplexer may be connected to a 'dot' line, to a
'dash' line, or left open, respectively enabling a dot, a dash, or a space to be generated
in a given time period. Up to 23 dots, dashes, or spaces may be generated to give a
combination of Morse letters or numbers. The dots and dashes are selected by two rows
of on-board preset switches. The code and repetition rate may be adjusted
independently.
The RPG module also contains a 3:1 counter for gating the ident code; this counter
divides the code word -in the ratio of 3 to VOR to 1 to DME.
Front panel switches allow associated or independent operation, and allow selection of
either the VOR or the DME as the master ident source.
2.3.8.1 RPG Main Board

Drawing 71119-1-25
Data
Input frequency 30 Hz
Clock frequencies for delay circuits 622.08 kHz
207.36 kHz
12.96 kHz
Modulation signal output (sine 30 Hz
wave)
DME signal input 15 volts logic level
VOR key to CMP 15 volts logic level
DME key 15 volts logic level
DME keyed output 15 volts logic level
The 30 Hz reference phase adjustment is provided by two stages of variable digital

delay, each controlled by switches S1 and S2. One switch allows a 'fine' phase
adjustment (approximately 0.05 degrees per step) and the other provides for 'coarse'
adjustment (approximately 0.8 degrees per step). A total phase delay of 6.5 degrees is
provided in each direction by these two switches. A third delay stage comprising D4 and
S3 applies a fixed delay to the 30 Hz to correct for system delays; this enables the 30 Hz
reference to be correctly centred about zero degrees. Two frequencies, 12.96 kHz and
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H4A71110 SECTION 2
207.36 kHz from the TSD module, provide the necessary timing to generate the delays.
Shift register D2 and D3 are actually clocked by the edge of a 622.08 kHz signal, but are
gated by the 207.36 kHz signal, thus effectively clocking them at a 207.36 kHz rate.
The 30 Hz reference sine wave is synthesised from a digital waveform generator
comprising an 8-bit counter D6 and D7, a read-only memory D10, and a digital-to-
analogue (DAC) converter D11. The sine generation is initiated by the positive edge of
the 30 Hz signal from D5:10; this is applied to a preload pulse generator consisting of
flip-flops D12 and D13. A preload pulse, generated one clock cycle (12.96 kHz) later is
applied to D6:1 and D7:1, initialising the counter to its preset starting value (count 40).
As the counter counts up it addresses the ROM D10, causing it to output a digital value
to the DAC D11 for each location. The digital values in the ROM correspond to sine
values from 0 to 180 degrees so that the output of the DAC is a 30 Hz half sine wave
digitised into 216 steps. When the counter reaches its maximum count of 255, a carry is
generated at the carry output D7:7 and this pulse is applied to inverter D15:4 and the
preload generator D13:6. The output pulse preloads the counter to its starting value, and
the counting sequence is repeated for the remaining half-cycle.
A bistable latch D15, D14 and N1:7 generates the reference voltage for the DAC. During
the first half-cycle of the sine wave a reference voltage of -10 volts is generated, which
causes the DAC to output the positive half-cycle of the sine wave; at the end of the first
half cycle, when the carry pulse is generated, the state of the latch D15 is changed so
that +10 volts is applied to the DAC D11:15, causing the negative half-cycle to be
generated. This circuit thus produces an accurate sine wave with 432 steps. Filtering is
introduced by N1:1, C1 to reduce the ripple at the step frequency. The waveforms are
shown in Figure 2-11.
An accurate 10 volts reference is generated by voltage regulator N2 and associated
components.
The ident keyer circuit generates a repeated Morse code identification signal of up to
four characters. The characters are built up by setting switches to place the 'dot' and
'dash' elements in the required sequence.
The speed at which the identification signal is transmitted is set by the frequency of the
oscillator circuit associated with N3:5. The frequency can be varied by altering the
CODE SPEED preset RV1.
The repetition rate of the ident signal is determined by the frequency of the oscillator
circuit associated with N3:9. The rate can be varied by altering the CODE REPTN preset
RV2.
The required sequence of dots and dashes is provided by circuitry associated with D20,
D21, D22 and D23. The arrangement of common binary lines to the demultiplexers D21,
D22 and D23 in conjunction with the steering circuitry implemented with D19 and D26
enables D21, D22 and D23 in turn, while inhibiting the other two demultiplexers. The
4-bit binary counter D20 generates the binary codes corresponding to decimal 0 through
15. Thus a high (15 volts) is stepped along first from D21:4 through to D21:13, and then
through D22 and D23 and, depending on the settings of switches S6-S11, the high is
applied to the 'dots' bus or the 'dashes' bus.
The detailed operation of the keyer can be seen with reference to Figure 2-10 which
shows the signals present at various circuit points for the generation of the letters UN.
The sequence is started by the asynchronous start pulse which is produced at D17:12
by dividing the frequency of the repetition oscillator N3:9 by 15. The start pulse initialises
the sequence by setting D19:1 high and by setting all the Q outputs of D20 high. This
enables the first output D21:4 which may be switched by S6/S7 to the dash or dot line to
give the first desired code element. With a dot selected a high level will be produced at
the code output X16 for one full clock cycle when D19:2 goes high.
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H4A71110 SECTION 2
When D19:2 is clocked low on the next clock pulse the generation of a 'dot-length' space
is automatically inserted after the first dot.
The next clock pulse from N3:5 clocks D20 to its next state for the generation of the next
code element and the sequence is repeated.
With a dash selected by closing S6 to the dash position, the dash bus will be high which
will preload the dash timer D 18 with a decimal 3 causing the output to remain high for
three dot periods.
The space between letters (see line labelled STATE in Figure 2-10) is formed by leaving
both the dot and dash switches in the 'off' position. This allows a space equivalent to
three dot elements to be generated between letters of the code word.
The line labelled counter state in Figure 2-10 traces the counter zero 15, 14, etc, states
and the progression of the high along the demultiplexer output.
At the end of the character generation sequence D23:13 is activated and an inhibit
signal is applied to D 18:4 stopping the operation of the keyer until the next start pulse is
received.
Where a VOR and a DME beacon are collocated they may be operated in either
'independent' mode or 'associated' mode.
The DME beacon may or may not have its own ident code generator. If the two beacons
are to be associated, S4 is switched to ASSOCIATED and further, where the DME
beacon does have an ident code generator, a choice is made at switch S5 MASTER
between using the DME or the VOR as the common source of ident code for the pair.
With the DME acting as the code source (VHF/3), ident code from the DME enters at
XMA:28 (this point is grounded for the duration of a code element) and after passing
through the input protection circuitry all code elements longer than 50 milliseconds pass
N4:5 and are converted into 10 milliseconds pulses by D37:6. Provided pulses of 10
milliseconds duration follow one another at intervals of less than 23 seconds, D37:10 of
this retriggerable monostable is held high. Provided also another 10 milliseconds pulse
is generated which occurs more than 5 seconds after the first 10 milliseconds pulse then
it is assumed that DME code is present at XMA:28 and D39:3 goes low and remains low
provided D37:10 does not time out. If D37:10 does time out (after 23 seconds) the code
presence circuitry causes the internally-generated code to be fed to the VOR beacon.
If the DME code is restored at XMA:28 the code presence circuitry causes the DME-
generated code to be again supplied to the VOR beacon.
Switch D35:4 inhibits code to the VOR except when the DME code presence detector
determines that valid code is present.
With the VOR keyer acting as the code source, each ident code signal generated
appears at X16 and is available at XMA:20, labelled KEYER OUT (SPARE).
The counter D24 operates the switches labelled D35:14 and D35:15 to channel three
consecutive ident signals past X17, labelled VOR-3 (for the VOR) and then to channel
the next ident signal past X18, labelled VOR-1 (for the DME).
When the code source is a DME (DME/1), the DME beacon may have two separate
outputs with three consecutive ident signals appearing at one of them and the next ident
appearing at the other output. For a beacon with this ident signal arrangement the three
idents output is connected to XMA:28 as previously described while the next 'ident after
three output' is connected to XMA:27. The signal at XMA:27 passes through the input
protection circuitry to appear at X20, labelled DME-1.
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H4A71110 SECTION 2
When the power is off to the VOR rack, relay contacts K2/1 close and the input at
XMA:27 passes to the output at XMA:26 provided the link labelled BYPASS is in place
between X31 and X32.
The ident signal for the VOR beacon leaves the RPG module at XMA:21, labelled VOR
KEY, and the VOR LED V5 flashes the ident signal.
The ident signal to an associated DME beacon leaves at XMA:22 labelled DME KEY and
the DME LED V6 flashes this ident signal.
Depending on the 3-bit code presented to the multiplexer D30 one of its eight inputs is
selected and becomes the VOR ident signal at XMA:21.
Likewise the code applied to a second multiplexer D31 causes one of its eight inputs to
be selected and this input becomes the DME ident signal at XMA:22.
The truth tables below show how the multiplexers are used to select the ident codes
output from the RPG module.
Table 2-1 Truth Table D30 - VOR Key Output XMA:21
VHF/3 CODE PRESENT ASSOCIATED/VOR INDEPENDENT IDENT CODE OUTPUT
FROM DME MASTER
X X 1 VOR-4
X 1 0 VOR-3
1 0 0 VHF/3 FROM DME
0 0 0 VOR-3
Table 2-2 Table D31 - DME Key Output XMA:22

ASSOCIATED/ VOR INDEPENDENT 'THIS RACK IDENT CODE OUTPUT
MASTER RADIATING' FOR DUAL
SYSTEM ONLY
X X 0 NO OUTPUT
X 1 1 DME/1 CODE FROM
DME
1 0 1 VOR-1
0 0 1 DME/1
In a dual VOR installation the ASSOCIATED line runs between XMA:17 on each VOR
and likewise the VOR line runs between XMA:18 on each VOR. If the KEYER MODE
switch, S4 and the MASTER switch, S5 on each VOR are not set the same, the MODE
WARNING indicator LED lights to warn of the change to the ident signal which will occur
upon a changeover between the VOR beacons.
If the associated DME has been selected as the master ident and if D39:3 goes high
indicating that no ident code is present at XMA:28 then the ident code FAULT indicator
lights.
Relay K1 and transistor V8 are driven by the DME code output. Appropriate linking of the
pins X26 through X30 allows either the relay contact or the transistor to supply the DME
KEYED OUTPUT.
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H4A71110 SECTION 2
Figure 2-10 RPG Keyer Waveforms
2-54
H4A71110 SECTION 2
Figure 2-11 RPG 30Hz Sine Generator Waveforms
2-55
H4A71110 SECTION 2
2.3.9 SCU - Sideband Changeover Unit

Components Sideband Changeover Unit 1A71122
Subunits Sideband Switch Unit 1A71153
This unit consists of three boards, one main switching board and two sideband switching
units. The main board receives inverted and non-inverted 30 Hz square wave signals
which are converted to switching drive signals for operating the diode high frequency
switches.
Two sideband changeover switches alternatively switch upper and lower sideband input
signals to the two halves of each antenna distributor switch. The outputs are switched at
a 60 Hz rate so that the appropriate sideband signal is fed to the appropriate group of
antennas at the correct time in the commutation cycle. For example, LSB will be
switched to antennas 1 to 24 in the first half of the cycle and then to antennas 25 to 48 in
the second half.
Each changeover switch unit is the RF equivalent of a double pole, double throw switch.
The RF diode switches are the same as those used in the antenna distributor switch.
2.3.9.1 Sideband Switch Units

Drawing 71153-3-01
Performance Insertion loss Less than 0.5 dB
Data
Insertion phase shift 77 ±2 degrees
Isolation (switch ‘off’) Less than -60 dB
Input return loss Greater than 28 dB
The diodes are arranged in four groups of three for each of the RF switches. Each
switch consists of a T network of two series diodes and one shunt diode, the series
diodes being in the conduction state when the RF switch is 'on' (the shunt diode being
reverse biased).
For example, in switching RF from XFA to XFB, V1 and V3 will be forward biased by the
switch drive signal from the SCU Main Board. The switching voltage applied is
approximately -42 volts. This causes the forward bias current to flow from the -40 volts
supply through chokes L5, L6 and L1 to the switching line. V2 will be biased off by this
same negative voltage.
For the 'off' state, the applied switching voltage is approximately +1 volt (derived from
the +5 volts supply in the Driver Board). This voltage reverse biases diodes V1 and V3
and forward biases V2, to shunt any residual RF to ground. The other three switches
operate in the same manner. The switches are driven so that only two are 'on' at any
one time.
This gives two switching states, determined by the phase of the applied switch drives:
a. switches connect XFA to XFB and M to XFD in the 'on' state, or
b. switches connect XFA to XFD and XFC to XFB in the 'on' state.
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H4A71110 SECTION 2
2.3.9.2 Driver Board

Drawing 71152-1-24
Performance Supply voltage requirements +5 volts and -40 volts
Data -45 volts
ODD input 30 Hz, 15 volts peak
EVEN input 30 Hz, 15 volts peak, phase
inverted with respect to
ODD input
Output (with RF switch connected) +1.2 volts
-42 volts
The SCU Main Board contains four identical switch circuits with input inverters which
translate the input CMOS logic levels (0 volts and +15 volts) to +5 volts and -45 volts
respectively, in order to provide drive for the switching diodes in the sideband switch. A
logic 'high' on inverting gate D1:10 gives a logic low into transistor V11, which turns off
V12, V13 and V14, leaving V15 'on', and producing an output of -45 volts. A logic 'low'
on the gate produces the opposite effect, turning V14 'on' and giving +5 volts at the
output.
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H4A71110 SECTION 2
2.3.10 ASD - Antenna Switch Driver

Drawing 71120-2-31
Components Antenna Switch Driver 1A71120
There are two identical Antenna Switch Driver modules per rack. Each module consists
of 12 identical switching circuits, each of which is controlled by a 4-bit binary word reset
at a 60 Hz rate by the antenna commutation counters in the Timing Sequence
Generator. The output of each Switch Driver controls two RF switching circuits in the
respective ODD or EVEN Antenna Distribution Switches. Each module therefore controls
24 switching circuits in each Antenna Distribution Switch module.

Data +5 volts
-40 volts
-45 volts
Input levels Logic 1 15 volts peak
Logic 0 Less than 0.4 volts
Output levels (into switch diodes)

Logic 1 +1 volt
Logic 0 -41 volts
As all 12 switching circuits are identical only one will be described. The input circuit
consists of a 4-bit to 16-line decoder D1 which outputs to 12 switch drivers. The input
signal is coded so that D1 outputs sequentially from 1 to 12. The selected output of D1
switches to logic '0' for 1/720th of a second each time the antenna commutation counters
in TSD are clocked by the positive edge of the 720 Hz clock.
A logic '0' cuts off transistor V11 which in turn cuts off V12, V13 and V14 and makes
transistor V15 conduct. This gives -41 volts output at pin 1 via R21 which limits the
current through V15 when the output is connected to the associated input of the ADS
module.
With a logic '1' input from D1, V11 conducts, turning V12, V13 and V14 'on' and causing
V15 to turn 'off'. The output at pin 1 is switched from -41 volts to +1 volt. Resistor R20
limits the current through V14 when the output is connected to the ADS module.
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H4A71110 SECTION 2
2.3.11 ADS - Antenna Distribution Switch

Drawing 66076-2-18
Components Antenna Distribution Switch 2J66076
There are two Antenna Distribution Switch units per beacon; they are designated
ADS-ODD and ADS-EVEN, and are mounted externally to the rack. Each unit contains
two printed circuit boards, each containing 12 antenna switching circuits per board.
Therefore there is an antenna switching circuit associated with each of the 48 sideband
antennas.
Each board has a common RF input which is switched in turn to the 12 antennas
associated with the board. The corresponding circuits of each board are switched
together; for example, antenna 1 is driven at the same time as odd numbered antenna
25.
All RF antenna feed lines in each ADS unit are fitted with gas discharge protectors to
provide surge protection against any lightning induced transients. The cables carrying
the control signals are fitted with semiconductor type protectors to provide protection
against any transients.
Performance Supply voltage requirements -40 to -40.5 volts
Data
Switching input Square wave, +5 volts to
-45 volts source voltage
Insertion loss when 'on' Not more than 0.4 dB
Attenuation when 'off’ Not less than 60 dB
Input return loss Not less than 23 dB
Output reflection coefficient Amplitude 0.60 ±0.04 volts
Phase -39 ±5 degrees
Since all the switching circuits in both units are identical, only board 1 and circuit 1 in the
Antenna Distribution Switch (Odd) is described in detail.
The common RF input to the first board is received at socket SKM and fed to all the
circuits via capacitor C63. Similarly, socket SKZ is the common RF in put for the second
board, feeding its circuits via capacitor C163.
The 12 switching inputs for the unit, received at PLA:1 to PLA:6 and PLA:14 to PLA:19
are logic '0' pulses, 1/720th of a second wide, at a repetition rate of one every 1/60th of a
second, and occurring sequentially and cyclically. These pulses are obtained from the
Antenna Switch Driver (AM). Each switching input has a logic '1' level of +5 volts source
voltage and a logic '0' level of -45 volts source voltage. The corresponding circuits of
each board are switched together, the input to PLA:1, for example, switching the first
circuit in each of the two boards.
Two RF chokes and two capacitors in each switching input circuit (for example, L1, L2,
C3 and C4 for the switching input to circuit 1 in the first board) provide RF isolation for
the source circuits from which the switching inputs are obtained. The -40 volts fixed bias
input to each circuit is similarly decoupled by a choke and a capacitor (for example, L3
and C65 for circuit 1 in the first board). In addition, a choke, a resistor and a capacitor
provide RF isolation for the -40 volts bias input to all the circuits on that board (for
example L61, R61, and C61 for the first board of the ADS module).
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H4A71110 SECTION 2
Each of the 12 circuits on each board is an RF switch. Referring to the first circuit of the
first board, when the input to PLA:1 is negative, it reverse biases diodes V3 and V4, and
forward biases diodes V1 and V2. Thus the RF signal at SKM is switched through to
antenna 1 via input capacitor C63, diodes V1 and V2, output capacitors C1 and C2 and
socket SKA. When V1 and V2 are on, the -45 volts source voltage of the switching input
becomes -40 volts at PLA:1 due to the -40 volts bias applied to PLA:13.
When the input to PLA:1 becomes positive, it forward biases diodes V3 and V4 and
reverse biases diodes V1 and V2. Thus antenna 1 is taken to ground via capacitor C2,
resistor R1 and diode V4. The resistor R1 is switched across the signal path at an odd
multiple of quarter-wave lengths from the antenna.
Gas discharge protectors F1 through to F60 and F101 to F160 provide protection for the
RF coaxial feed lines against any lightning induced transients. F61 through to F72 and
F81 to F94 provide protection against transients on the incoming control lines.
The operation of switches in the second board is similar to the operation described
above; these switches are driven coincident with the first board but their RF input is the
other sideband signal. Thus, at any one time, diametrically opposite antennas are driven
with opposite sidebands; for example, the RF input at SKM being switched to the odd
antenna 1 and that at SKZ being switched to odd antenna 25.
The operation of the Antenna Distribution Switch (Even) is identical with the 'odd' switch
except that the RF input to its socket SKM is switched through to even numbered
antennas 2 to 24 and the RF input to socket SKZ to even numbered antennas 26 to 48.
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H4A71110 SECTION 2
2.3.12 CTU - Control and Test Unit

Drawing 72550-1-29
Components Control and Test Unit 2A72550
Subunits CTU Processor Board 2A72552
The Control and Test Unit (CTU) monitors, controls and tests various functions within the
VRB-52D DVOR. The CTU contains a comprehensive test facility to allow rapid
assessment of performance. By keypad selection, each of the main DVOR parameters,
including signal levels and status conditions, can be measured and displayed. The CTU
is used in conjunction with the Monitor Bearing Counter and Data Acquisition (MBD)
module to perform the measurements and tests.
The CTU controls the operation of a VRB-52D DVOR rack, both locally and remotely. It
also provides status signalling and control functions for the Remote Control and
Maintenance System (RCMS).
A detailed description of the controls and indicators of the CTU is given in Appendix A.3.
The CTU comprises three boards, namely the CTU Processor Board (2A72552), the
CTU Front Panel Board (2A72553) and the RCMS Interface Board (1A72555). The
boards are mounted on an aluminium frame and connected using ribbon cables. A
DC/DC converter is also mounted on the aluminium frame and connects to the CTU
Processor Board. The CTU is installed in the top bay of the DVOR rack.
A block diagram of the CTU is shown in Figure 2-12. The interwiring diagram is
72550-1-29. Details of the individual boards are given in the following sections.
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H4A71110 SECTION 2
Figure 2-12 CTU Block Diagram
The bare printed wiring boards (PWB) used in the CTU are the same as those used in
the 1A72550 CTU, which is used in the LDB-102 DME, although the assembled
components may be different. In some cases circuitry on the boards will have no
function in the VRB-52D.
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H4A71110 SECTION 2
2.3.12.1 CTU Processor Board

Drawing 72552-1-38
The CTU Processor Board provides the microprocessor and memory for the CTU. It
contains a slowed bus (extended CTU bus) which provides interfaces with the CTU
Front Panel Board, the RCMS Interface Board, and the MBD module. The CTU also has
a serial port for communications with the optional Remote Maintenance Monitoring
(RMM) system. A block diagram of the CTU Processor Board is shown in Figure 2-13.
The microprocessor, D9, is a CMOS 80C186 which operates at 10 MHz. The processor
provides a clock generator, an interrupt controller, three 16-bit timers, memory and
peripheral chip select logic, and a wait state generator.
The microprocessor supervisory chip, N2, acts as a watchdog for the processor and as a
24 volts monitor. If the watchdog input (WDI), pin 11, is not toggled within 1.6 seconds,
RESET (pin 15) pulses low causing the processor to be reset. N2 monitors the 24 volts
line via the power fail comparator input (PM), pin 9. If the 24 volts line voltage drops
below a preset value then the voltage at PFI drops below its threshold. This in turn
causes PFO (pin 10) to go low, which activates the LOW_TPNDR_BAT alarm. The
preset value may be adjusted by R32 to cover the range 18 to 23 volts.
The wait state generator (WSG) and address decoder, D13, is implemented using an
EP610 programmable logic device (PLD). D13 generates external CTU bus signals for
the interfaces with the CTU Front Panel Board, RCMS Interface Board and the MBD
module. It also produces the SRDY signal for the processor. The SRDY signal causes
the processor to insert wait states during input/output operations to slower devices. All
devices selected by PCS0, PCS1, PCS2, MCS1 and MCS2 require seven wait states.
All other devices require zero wait states. D7, D8 and D10 are address latches.
The wait state generator and address decoder, D13, operates as follows. A BCD counter
(counting from 0 to 9) consisting of CT0, CT1, CT2, XIPL CT0, is the least significant bit)
is clocked by input CLK2. It is normally held at count 0, but is enabled to start counting
from count 0 whenever any of the chip select input signals PCS0, PCS1, PCS2, MCS1,
MCS2 go active low. XIPL provides a positive clock edge at the beginning of count 8 of
the wait state counter. This clock is used to latch read data on the extended CTU bus
into latches to be then read by the CTU.
XRD goes active low whenever the input signal RD is active low and the wait state
counter is at counts in the range 3 to 8. XWR goes active low whenever the input signal
WR is active low and the wait state counter is at counts in the range 3 to 8. SRDY, on
going low, causes the 80C1 86 microprocessor to generate wait states until this signal
goes high again. This signal is low whenever either input RD or WR is low and the wait
state counter is at counts in the range 1 to 8.
WR_PCS1 is an active HIGH latch control signal for data written by the microprocessor
at the address(es) selected by input PCS1. This signal is only high when both inputs WR
and PCS1 are active LOW and the wait state counter is at counts in the range 4 to 8.
WR_PCS2 is an active HIGH latch control signal for data written by the microprocessor
at the address(es) selected by input PCS2. This signal is only high when both inputs WR
and PCS2 are active LOW and the wait state counter is at counts in the range 4 to 8.
DEN_PCS0 is an enable signal to the data bus transceiver for the extended CTU bus to
the CTU Front Panel and RCMS Interface Boards. The signal is active LOW whenever
both inputs DEN and PCS0, are active LOW.
DEN_MCS1 is an enable signal to the data bus transceiver for the extended CTU bus to
MBD module. The signal is active LOW whenever both inputs DEN and MCS1 are active
LOW. DEN_MCS2 is not used in the VRB-52D DVOR.
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H4A71110 SECTION 2
Figure 2-13 CTU Processor Board Block Diagram
The memory on the CTU Processor Board comprises 8Kx8 EEPROM, 64Kx16 EPROM,
and 32Kx16RAM.
The EEPROM, D16, is used to store the state of the CTU front panel at power down so
that it can be restored to the same state at the next power-up; it also stores the number
of restarts.
The EPROM, D17, is used to store the CTU program, operating system, applications
code, built-in tests and production test code.
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H4A71110 SECTION 2
The RAM is divided between two chips; D15 stores the low bytes, and D14 stores the
high bytes.
The RS-422 serial port comprises two differential bus transceivers, N4 and N5, as well
as a universal asynchronous receiver/transmitter (UART), D6. This arrangement allows
the serial port to operate in full-duplex mode.
The serial port is dedicated to communications with the Remote Maintenance Monitoring
(RMM) System.
The interface to the RCMS Interface Board and the CTU Front Panel Board is
implemented using D29, D30 and D31.
D29 is an octal bus transceiver used to transfer data between the CTU Processor Board
and the other two boards. DT/R from the processor controls the direction of data flow
through the transceiver. Resistor networks RN20 and RN21 reduce noise susceptibility
on input data to D29.
D30 is the address buffer, and its outputs are enabled when PCS0, is low. A0 from the
processor is not buffered since it is used as an enable signal rather than an address
signal by the processor (analogous to BHE for the low data byte). Hence ADDR0 to the
CTU Front Panel and RCMS Interface Boards connects to A1, ADDR1 connects to A2,
and so on up to ADDR6.
D31 is the control byte buffer. Its outputs are always enabled.
The interrupt input (XINT) from the CTU Front Panel and RCMS Interface Boards enters
the CTU Processor Board on XN3:34. It is ANDed with the RDY/BSY signal from the
EEPROM. This has the effect of disabling XINT while the EEPROM is being written to.
The MBD module interface comprises D35, D36 and D37, and connects to the MBD
Module via XN2. The arrangement and operation of this interface is similar to the
interface to the RCMS Interface Board and the CTU Front Panel Board.
The address and control bus buffers, D36 and D37, are disabled (through gates D38 and
D39) when bus signal BUS_SUPPLY_OK_1 is LOW. BUS_SUPPLY_OK_1 is pulled
LOW by V1 1 if the +5 volts supply fails or by V1 0 if the watchdog monitor, N2, detects
that the +5 volts supply is below its lower limit. BUS_SUPPLY_OK_1 is used on this
board and on the MBD module to disable all bus drivers unless all circuitry connected to
the bus is powered.
There are two 8-position DIP switches on the board, S1 and S2, which are read via
buffers D20 and D25 and are used to configure the CTU. The setting details for these
switches are given in Appendix A.
There are six green LEDs on the CTU Processor Board. H1 and H2 are driven by one of
the address latches, D10, (to indicate address line activity) and the remaining four LEDs
are driven by octal latch D26. H6 is a "heartbeat" indicating healthy processor operation.
H4, H7 and H8 have no meaning on this board during normal operation.
Four outputs of D26 are used for control purposes. The output on pin 14 toggles the
watchdog, N2. The outputs on pin 18 and 19 have no meaning on this board and are
permanently set LOW. The ACTIVE low output on pin 20 is a processor controlled
RESET ANDed in D1 1 with the watchdog RESET and then fed to the board and
peripheral circuitry.
The CTU Processor Board has six links, XN5-10, which have the following functions (the
function being enabled when the link is fitted):
LINK FUNCTION
XN5 No function on this board
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H4A71110 SECTION 2
XN6 Watchdog disable

XN7 Select signature analysis
XN9 Watchdog test
D19 and D24 provide for up to 16 status inputs. The only ones implemented on this
board are:
• D19:2 Low Battery from N2;
• D24:2 EEPROM Ready from D1 6;
• D24:6 Battery Charger Normal from the rack; and
• D24:8 AC Power Normal from the rack.
D18 and D23 provide for up to 16 control outputs. On this board they are implemented
as follows:
• D18:13 Monitor (in other rack of a dual) On (5 volts logic output from D28);
• D18:14 Transfer Relay Activated (5 volts logic output from D28);
• D18:15-17 No function, set permanently OFF (resistive pull up to +5 volts);
• D18:18-20 No function, set permanently OFF (that is, high impedance);
• D23:13 Monitor (in this rack) On (5 volts logic output from D28);
• D23:14 Rack Power On (5 volts logic output from D28);
• D23:15 Transmit Inhibit (open collector output);
• D23:16 MBD Module Power On (open collector output);
• D23:17 Ident Inhibit (open collector output);
• D23:18 No function, set permanently OFF (i.e. high impedance);
• D23:19-20 Selects signal to CTU speaker;
D12 is a binary ripple counter. The clock input (pin 10) is 10 MHz clock output from the
processor. The three D12 outputs used are 610 Hz (pin 3), 1220 Hz (pin 2) and 2440 Hz
(pin 1). Either 610 Hz or 1220 Hz can be selected to be a clock input for the processor
(D9:20, 21) and the UART (D6:5). The selection is made by fitting either R30 or R31 as
required. The 2440 Hz output of D12 is an input to the ident PLD (D2:2).
Switching of the signal to the internal sound transducer, B1, is performed by PLD D2.
The ident tone is received on XN2:21 a and connects through protection resistors RN3
and RN4 to pin 18 of D2. A 2440 Hz tone from D12 connects to pin 2 of D2.
REC_IDENT_SEL_1 and REC_IDENT_SEL_2 select the tone to the speaker as follows:
REC_IDENT_SEL_2 REC_IDENT_SEL_1 SPEAKER OUTPUT
0 0 Ident Tone
0 1 None
1 0 2240 Hz
1 1 None
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H4A71110 SECTION 2
24 volts from the main power supply enters the CTU board via XN1:3a and XN1:3c. This
is distributed around the board and to XN3:43 and XN3:44 for distribution to the CTU
Front Panel and RCMS Interface Boards. 24 volts is also connects to XN11:1. From here
it is fed to the CTU DC/DC converter which returns 5 volts via XN11:4. The DC/DC
converter is a switching power supply which is mounted on the CTU metalwork.
5 volts from the DC/DC converter is used on the CTU Processor Board; it is distributed
to the CTU Front Panel Board and RCMS Interface Board via XN3:39 and 40; it is
distributed to the external I/O board via XN1:12c and it is available on XN1:12a,c, 13a,c
and 14a,c, for use by a Navaid Maintenance Processor (NMP) module if fitted as part of
an RMM system.
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H4A71110 SECTION 2
2.3.12.2 CTU Front Panel Board

Drawing 72553-1-34
The CTU Front Panel Board provides the CTU user interface. It has switches, LEDs and
a 2-line by 40-character LCD which allow the user to:
a. display operational parameters and test results; and
b. exercise local control and monitoring of the DVOR.
The LCD displays a menu of functions available to the user on the function keys, while
other keys have dedicated functions.
A block diagram of the CTU Front Panel Board is shown in Figure 2-14.
Figure 2-14 CTU Front Panel Board Block Diagram
The interface with the CTU Processor Board comprises D7, D9, RN1-6 and RN 12-14.
Resistor networks RN1, RN2, RN4, RN5, RN 12 and RN 13 reduce noise effects on the
incoming lines. D7 is a 74HC245 data transceiver which is used to transfer data bits
D0-D7 between the front panel and the CTU Processor Board. The XDT/R signal from
the processor is used to control the direction of data flow through the transceiver.
D9 is an EP610 PLD which is programmed as the address decoder for the front panel.
• FP_DEN (pin 17) enables the transceiver, D7, for the data bus. It is active LOW
when inputs _PCS0 (pin 10) and XDEN (pin 19) are active LOW and XRES (pin
18) and A6 (pin 2) are inactive LOW.
• DIS_EN (pin 22) enables read and write access to the LCD display. It is active
HIGH when inputs: _PCS0 is active LOW, either _XRD (pin 20) or _XWR (pin 21)
is active LOW, XRES is inactive LOW, and the address (set by A7 to A1) is in the
range 00H to 01H.
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H4A71110 SECTION 2
• CS_RD (pin 3) enables read access to keypad interface PLD, D5. It is active
LOW when inputs: _PCS0 and XRD are active LOW, XRES is inactive LOW, and
the address is 02H.
• ALARM_SEL (pin 4) enables read access to the two BCD Alarm Delay setting
switches through buffer D3. It is active LOW when inputs: _PCS0 and XRD are
active LOW, XRES is inactive LOW, and the address is 03H.
• A_REG1 (pin 8) enables write access to octal latch, D1 1, driving alarm
indicators. It is active HIGH when inputs: _PCS0 and XWR are active LOW,
XRES is inactive LOW, and the address is 04H.
• A_REG2 (pin 5) enables write access to octal latch, D 10, driving alarm
indicators. It is active HIGH when inputs: _PCS0, and XWR are active LOW,
• C_STAT1 (pin 9) enables write access to octal latch, D6, driving status
indicators. It is active HIGH when inputs: _PCS0, and XWR are active LOW,
• C_STAT2 (pin 6) enables write access to octal latch, D12, driving status
indicators. It is active HIGH when inputs: _PCS0 and XWR are active LOW,
• M_STAT (pin 7) enables write access to octal latch, D8, driving alarm indicators.
It is active HIGH when inputs: _PCS0 and XWR are active LOW, XRES is
inactive LOW, and the address is 08H.
The liquid crystal display (LCD) is 40-character by 2-line display. The viewing angle of
the LCD may be adjusted by varying R1, which changes the feedback of the drive
voltage to the LCD display provided by N1. V1 and V2 in the operational amplifier circuit
provide temperature compensation. The forward voltage drop across diodes V1 and V2
varies with temperature, resulting in the positive input to the amplifier also varying with
temperature; this helps to maintain good LCD contrast.
There are 34 LEDs visible on the CTU front panel. These LEDs provide information on
DVOR control status, test functions, power status, alarms and miscellaneous status.
Another LED, the heartbeat LED (H14) is visible only when the CTU is not in its normal
position in the DVOR rack (e.g. when the CTU is placed on extenders). It is used as a
diagnostic aid to ensure that the CTU processor software is writing to the front panel.
During normal operation the heartbeat LED will flash about once a second.
The octal latches D6, D8 and D10-12 are used to control the LEDs. A high level on the
XRES line from the CTU processor will force all latch outputs to a high impedance state,
turning the LEDs off. Also during reset, transistors V7 and V8 will turn on, causing the
PRIMARY alarm LED (H30) and the CTU alarm LED (H33) to be on.
The front panel has 14 pushbutton switches which are read by the switch scanner and
coder PLD, D5. These keys are divided into two groups, those with direct inputs to the
PLD, and those read as part of a four-by-four matrix and encoded to form a 4-bit output.
The ANTENNA CHANGE switch, S6, and S7 (which is not fitted) have direct inputs to
D5. Debouncing is provided by R12, C10 and D4 for S6. D5 buffers the inputs on pins 14
and 23 to the outputs on pins 20 and 21 respectively when D5 is selected for reading by
the address decoder (at D5:4).
Switches S1 -5, S8-1 0 and S1 3-20 are read as part of a 4x4 array. (No switches are
fitted in the S7, S8, S9 and S20 locations.) D5 senses switch closures by driving the
COL 1-4 outputs LOW, one at a time, and reading the ROW1 -4 inputs. With no keys
pressed, the LOW column signal repeatedly cycles from COL1 through COL4. The rate
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H4A71110 SECTION 2
is controlled by the CLK1 input signal (1221 Hz). If a key is pressed when the
corresponding COL signal goes LOW, that COL signal stays LOW until all keys in that
column are released.
DEBNZOUT (pin 22) is an active LOW debounce signal. It is LOW while ever one and
only one key in a column is pressed. This signal is delayed by R10 and C8 (nominally 14
milliseconds) and inverted by D4 and fed back into the DEBOUNCE input (PIN 3).
Thus when a single key in a column is pressed for longer than the debounce delay, the
column and row data will be stable with only one each of the column and row signals
LOW, and DEBOUNCE HIGH.
If more than one key in a column is pressed, DEBOUNCE will remain LOW.
If keys in more than one column are pressed, the column in which the first pressed key
is detected will be the one which remains low (while the key remains pressed). Pressed
keys in other columns will remain undetected while the detected key remains pressed.
DEBOUNCE will go HIGH indicating a valid key input provide only one key is pressed in
the selected column.
While input CS_RD is HIGH, the seven output signals KEY0 (pin 15), KEY1 (pin 16),
KEY2 (pin 17), KEY3 (pin 18), KEYON (pin 19), ANT_CHNG (pin 20) and pin 21 are in a
high impedance state. When CS_RD is low these seven signals become active and
drive the data bus (pin 21 being low since S7 is not fitted).
KEYON, when HIGH, indicates that valid key data is present on KEY0, KEY1, KEY2 and
KEY3 from the switch matrix.
KEY0, KEY1 provide a binary code KEY0, is the least significant bit) for the column of
the pressed key as follows:
COLUMN KEY1 KEY0
1 0 0
2 0 1
3 1 0
4 1 1
KEY2, KEY3 provide a binary code (KEY2 is the least significant bit) for the row of the
pressed key as follows:
ROW KEY3 KEY2
1 0 0
2 0 1
3 1 0
4 1 1
There are two rotary switches, ALARM INHIBIT (S11) and ALARM DELAY (S12). The
outputs of these binary coded decimal (BCD) switches are read via buffer D3. S11 is
only accessible to the operator when the CTU is withdrawn from the rack. S12 is
mounted on the front panel and is accessible to the operator . -5 volts for the LCD
display is obtained from +5 volts by using two 74HCO4 inverters chips, D1 and D2, in a
charge-pump voltage inverter circuit.
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H4A71110 SECTION 2
2.3.12.3 RCMS Interface Board

Drawing 72555-1-02
The RCMS Interface Board provides opto-isolators to read remote control relay inputs,
and relays to control remote lamp outputs. All of the RCMS interface relays are fitted
with surge protection. The RCMS Interface Board also extends the Transponder 2
interface signals from the CTU Processor Board to a back plane connector. (This bus is
not used in the DVOR, but two control signals, SIGNAL-14 and SIGNAL-15 are used.) A
block diagram of the RCMS Interface Board is shown in Figure 2-15.
Figure 2-15 RCMS Interface Board Block Diagram
The interface with the CTU Processor Board comprises D1, D2 and RN1-9. Resistor
networks RN2, RN3, RN4, RN5, RN8 and RN9 reduce noise effects on the incoming
lines. D1 is a PLD which is programmed as the address decoder for the RCMS Interface
Board.
The address map implemented by the address decoder is shown in the table below.
FUNCTION READ/WRITE ADDRESS
RCMS_CONTROL_1 READ 20H
MISC_STATUS WRITE 22H
RCMS_STATUS_2 WRITE 23H
BITOUT_2 WRITE 25H
BITFB_2 READ 27H
D2 is a 74HC245 data transceiver which is used to transfer data bits D0-D7 between the
RCMS Interface Board and the CTU Processor Board. The XDT/R signal from the
processor is used to control the direction of data flow through the transceiver.
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H4A71110 SECTION 2
The latch D5 and buffer D6 form an input/output feedback circuit. This circuit is used to
check for the presence of the RCMS Interface Board. If a byte written to the latch can be
read back, the RCMS Interface Board is present and operational.
The RCMS Interface Board is fitted with 15 relays, K1-15. The relays have change-over
contacts fitted with varistors, F2-31, to provide surge protection. The relays are
controlled via octal latches D3 and D4.
The heartbeat LED, H1, is used as a diagnostic aid to show that the CTU processor
software is writing to the RCMS Interface Board. During normal operation the LED will
flash about once a second.
The RCMS Interface Board is fitted with six opto-isolator inputs. Each input comprises
an opto-isolator, a protection diode, a zener diode, a shunt capacitor and a series
resistor. The resistor limits current to the opto-isolator; the capacitor filters the applied
voltage; the zener ensures that low voltage inputs do not activate the opto-isolator; and
the diode protects the opto-isolator against reverse polarity voltages. The inputs are read
via buffer D7. The inputs to the buffer are normally pulled high by RN11 and go low
when the opto-isolator is switched on.
The ident tone transformer, T1, is not used in the DVOR.
The external 5 volts circuit comprising circuitry around N7 is not used in the DVOR.
The external 24 volts circuit comprising R9 and F1 is not used in the DVOR.
The RCMS Interface Board interconnects signals between XN2 and XN3. XN2 is a back
plane connector. XN3 connects via ribbon cable to the CTU Processor Board which
controls the interface to the transponder. Except for SIGNAL_14 (TRANSFER_RELAY
control) and SIGNAL-15 (MONITOR_O_RACK_ON control), these signals are not used
in the DVOR.
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H4A71110 SECTION 2
2.3.13 MRF - Monitor RF Amplifier

Components Monitor RF Amplifier 1A71113
Subunits RF Amplifier Board 1A71138
MRF Main Board 1A71141
The MRF module performs two separate functions. One function is to amplify and
demodulate the RF signal received from the monitor field antenna. The second function
is to provide a number of regulated voltages from an independent power supply for
powering all monitor units.
The RF Amplifier consists of a 2-stage RF bandpass amplifier, a demodulator, and an
amplified AGC system which maintains the average value of the RF envelope at the
detector close to a constant amplitude over a wide range of signal input levels. The
demodulated VOR audio signal is supplied to the MSC module.
The MRF Main Board contains the power supply which generates regulated voltages for
all of the monitor units. The power supply generates a dual 15 volts output using a
regulated pulse width modulator as the control element in a flyback converter
configuration. An independent voltage regulator supplies a separate +15 volts source.
2.3.13.1 RF Amplifier
Drawing 71138-2-25
Data
AGC reference voltage ±1 volt
RF signal input range 3 to 100 mV
Output Composite VOR signal
The RF Amplifier consists of a 2-stage band-pass amplifier using three resonant circuits
all tuned to the station frequency. The input circuit consists of a parallel resonant circuit
(L1, C2) followed by a dual-gate FET amplifier in which the gain is controlled by an AGC
voltage.
This is followed by a second resonant circuit (L3, C10) and another dual-gate FET
amplifier with a fixed gain. The amplified signal is passed through a third resonant circuit
(L5, C15) buffered by an emitter follower V8, then rectified in a signal detector V5 which
is biased on by V6. A unity-gain amplifier N1:1 with the same diode type in as feedback
circuit compensates the detector diode for changes related to temperature. The
composite VOR signal output from N1:1 is output via XMA:11 and XMA:14 to the MSC
module.
A sample of the output signal is filtered by a 2-stage filter R20, C19 and R21, C22 and
fed to the AGC amplifier N1:7. This operates as a high gain amplifier with an AGC
reference voltage of 1 volt applied to the non-inverting input. The voltage level
developed by the AGC amplifier is used to control the gain of the first dual-gate FET V3.
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H4A71110 SECTION 2
2.3.13.2 MRF Main Board

Drawing 71141 -1 -01
Data
Output voltage from pulse width ±15 volts
modulated supply
Output from regulated supply +15 volts
Logic control level to switch supply +5 volts
‘on'
The MRF Main Board contains a pulse width modulated switching power supply using a
regulating pulse width modulator N2 and switch transistor V11 in a flyback configuration.
The 24 volts DC input is connected to the switching power supply by an active switch
V1, V2 and V3. When a 5 volts logic signal from the controller is applied to V3, V1 and
V2 conduct and the 24 volts source is connected to the power supply with a voltage drop
of less than 0.7 volts.
The pulse width modulator N2 generates a continuous train of 50 kHz pulses with the
pulse period determined by R12 and C8. The pulses are fed to a MOSFET power
transistor V11 which operates as a series switch to the current flowing in the primary
winding of transformer T1. The voltage developed across the secondary winding is
rectified by V18 and V19 and filtered. A sample of this voltage is fed back through the
voltage dividing network R10, RV1 and R11 to the error amplifier in the modulator N2
which controls the pulse width and therefore the output voltage.
Overvoltage protection is provided by the circuit containing zener V1 5 and SCR V14. A
voltage surge will cause zener V15 to strike, triggering the SCR and removing the drive
to the MOSFET power transistor by clamping the D1 supply rail to ground. The
protection clamp is unlatched by resetting the DC input voltage.
Current limit sensing is achieved by monitoring the primary circuit current as a voltage
drop across resistors R20 to R24. A large primary current will drive V10 into conduction,
causing it to draw current from pin 9 of the modulator N2. As this current increases, the
modulator pulse duty cycle is reduced, thereby limiting the output current that can be
supplied by the unit.
Voltage overshoot on the positive edges of the driving pulse across the primary winding
is controlled by V12, C14 and R28. Isolated transient voltage spikes are clamped at 72
volts by the zener diodes V1 6 and V17.
Voltage regulator N1 provides a separate +15 volts supply, which is more highly
regulated, at XA2 for use with the Monitor RF Amplifier.
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H4A71110 SECTION 2
2.3.14 MSC - Monitor Subcarrier

Drawing 71114-1 -01
Components Monitor Subcarrier 1A71114
The MSC module contains filter circuits for separating the subcarrier from the composite
VOR signal, the subcarrier from the 30 Hz AM signal and harmonic content from both
the recovered 30 Hz FM and AM signals. The filtered subcarrier is fed to a frequency
discriminator which recovers the 30 Hz FM signal. Monitoring facilities are included for
checking the levels of the various signals and for generating an alarm if any of these
levels move outside preset limits. A voltage regulator provides a voltage reference for
the AGC circuit in the MRF module.
A notch alarm circuit examines the subcarrier for the presence of 'notches', that is, short
duration gaps in the subcarrier waveform. An alarm is given if any notches are detected.

Data
Input VOR signal:
AM component 0.3 volts peak
subcarrier component 0.3 volts peak
keyed ident 0.15 volts peak
FM sine-wave output 2.4 volts peak
AM sine-wave output 2.4 volts peak
Fault line voltage level under fault 0 volts (logic low)
conditions
AGC reference voltage 1 volt nominal
The VOR input signal is fed to both the subcarrier band-pass filter N1 and N2 and the 30
Hz AM filter N12:2. The subcarrier is separated from the composite VOR audio signal by
a 3-pole active band-pass filter comprising N1:1, N1:7 and N2:1. The filtered subcarrier
is amplified, level set and buffered by N3: 1, RV1 and N3:7. The output is applied to both
a precision rectifier N4:1, V1, V2 in the signal chain and to the input of the notch
detection circuit. The output from the rectifier is filtered by passive filters R27, C8 and
R28, C9, buffered by voltage follower N4:7 and applied to a window comparator N5:1
and N5:2 The level is compared with preset limits set by RV3 (upper limit) and RV4
(lower limit). If the level fails outside these limits the comparator output goes high and
the level inverted by D1 generates a fault indication.
The output from the buffer N3:7 is also applied to comparator N6:2 and a diode clamp
V9. The squared positive-going signal is applied to a frequency discriminator D6 and
D7:6 which recovers the 30 Hz signal. The discriminator is the pulse type in which the
average value is derived from a train of constant width pulses with variable mark/space
ratios. The average value of these pulses reproduces the 30 Hz sine wave signal.
The 30 Hz FM chain is identical to the 30 Hz AM chain from C21 and C31 onwards. Only
the AM chain will be described.
The 30 Hz AM signal is separated from the composite VOR input signal by means of an
active low-pass filter N 12:1 with a 30 Hz cut off. The 30 Hz output passes through a
passive low-pass network R104 and C33, an amplifier N12:7 with level set RV11 and a
second active low-pass fitter N13:1 identical to N12: 1. At this point the 30 Hz is
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H4A71110 SECTION 2
available at the output terminal for connection to the MFI unit. The output signal level is
monitored by a precision rectifier N14, filtered by two passive R/C filters R120, C37 and
R121, C28, buffered by N14:7 and applied to a window comparator N15:1 and V15:2
where the level is compared with preset limits set by RV12 (upper limit) and RV13 (lower
limit). If the input level fails outside these limits the comparator goes high and the level
inverted by D8 generates a fault alarm. Voltage regulator N7 provides the reference for
all level fault thresholds.
The rectified 9960 Hz signal from N4:1 goes to the input comparator N6:13 in the notch
chain with the threshold trigger point set by RV5. D2 is the notch detector which
indicates the absence of one or more cycles at the subcarrier frequency. D3:6 and D3:9
form time delays for the generation of the notch fault. D3 has a time delay such that the
notch must be present for half a second before a fault is generated.
A 'notch' refers to the absence of a few cycles of the 9960 Hz subcarrier signal. A fault
signal is generated by any notches which fall below the threshold level and which are
spaced less than the timeout period of D3:6. Normally, this is only caused by the failure
of a diametrically opposite antenna pair. If this condition persists for a period exceeding
the timeout of D3:9, then a high level fault signal will be given at D3:9 (see Figure 2-16).
A number of self-test facilities enable alarm threshold levels to be checked. When S1,
S3 or S4 are operated the gain of the associated amplifier is altered by a preset amount
which exceeds the trigger limits of the associated comparator and the appropriate fault
condition should be indicated.
When S2 is operated a 30 Hz rectified signal from N11 turns transistor V3 off once every
16.6 milliseconds. D2 is no longer retriggered and D3:10 eventually times out. This
provides a self check test for D2 and D3 monostables and a functional test for the
NOTCH FAULT indicator LED.
Figure 2-16 MSC Notch Circuit Waveforms
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H4A71110 SECTION 2
2.3.15 MFI - Monitor Filter and Indent

Drawing 71115-1 -01
Components Monitor Filter and Ident 1A71115
The MFI module performs two separate functions. One function is to convert the 30 Hz
FM and AM sine waves from the MSC module to square waves to provide input signals
for the MBC module.
The second function is to detect the presence of the keyed ident signal and to be able to
distinguish this from speech. The detection system is based on receiving two marks
spaced by the equivalent of one dot. If the monitor does not receive two correctly spaced
pulses in the received signal over a 35-second period then a fault signal will be
generated.
Adjustable phase networks are incorporated in the FM and AM channels which allow the
phase errors in the two channels to be equalised.
All faults signalled by the MFI module are processed by the Controller Unit which
determines if the beacon should be shut down.
Performance Supply voltage requirements 15± volts

Data
30 Hz sine wave AM 4.8 volts peak-to-peak
30 Hz sine wave FM 4.8 volts peak-to-peak
30 Hz square wave AM 15 volts CMOS logic level
30 Hz square wave FM 15 volts CMOS logic level
1020 Hz ident level 0.2 volts peak-to-peak
Ident filter centre frequency 1020 Hz
Ident filter bandwidth ±65 ±10 Hz
Line output level 6 volts peak-to-peak
(600 ohms termination)
Bearing fault adjust range ±1.5 degrees
Coarse calibrate range ±0.5 degrees
Fine calibrate range ±0.05 degrees
Time for fault to alarm 35 ±5 seconds
Ident fault inhibit output +15 volts
Minimum mark length 100 milliseconds
Minimum mark spacing 100 milliseconds
Complexity of at least one letter in Two marks separated by a
ident message to reset 35 seconds dot space
timer
The AM and FM paths are identical except for the inclusion of a BEARING FAULT
TEST facility (RV6, S2) and variable lead/lag phase networks at the input to the FM and
AM channels respectively. Calibrate presets RV9 (MONITOR BEARING CALIBRATE
COARSE) and RV10 (MONITOR BEARING CALIBRATE FINE) allow a small phase
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H4A71110 SECTION 2
adjustment to be made in each channel to equalise phase errors. Because the remaining
circuitry is the same for both channels, only the AM channel will be described.
Components N4 through to D8 comprise a phase-locked loop (with phase detector, filter
and VCO) which generates a square wave which is accurately locked to the input sine
wave.
Amplifier N3 reduces the input signal amplitude to half, and shifts it to 5 volts DC level.
Inverter N4 and analogue switches D6:2 and D6:9 constitute a quadrature phase
detector. The operation is shown in Figure 2-17. It will be seen that in phase lock the
chopped sine-wave signal at D6:2 has equal positive and negative portions with respect
to the 5 volts level.
N5 and associated components form a second-order loop filter. Its output is used to
control the frequency of the voltage controlled oscillator D7, which operates at a nominal
frequency of 120 Hz. Dividers D8:1 and D8:13 produce a square wave at a nominal 30
Hz, which is compared in frequency and phase with the incoming 30 Hz sine wave in the
quadrature phase detector. It will be seen from the waveforms in Figure 2-17 that when
the loop is in lock, the output square wave is 90 degrees displaced with respect to the
input sine wave. D12 level shifts the 11 volts logic from D8 (and D11) to the 15 volts
level required by the MBC module. Voltage regulator N9 provides the reference and
supply voltages for this module. S2 is the BEARING FAULT TEST switch located in the
FM channel. When operated, the switch introduces a phase error, preset by RV6, which
enables the bearing counter alarm to be checked.
The 1020 Hz keyed tone ident signal, input at XMA:2, is separated from the composite
VOR signal by band-pass filter N1:1 and associated components. The filter centre
frequency is set by RV1. Gain stages N1:7 and N2:7 provide an output of the recovered
ident for driving a remote line. Comparator N2:1 has a threshold of 3 volts, which
determines the minimum detection level.
The ident sensing circuits D1 to D4 distinguish between genuine ident marks and
random pulses from voice modulation which fails within the filter bandwidth. This is
achieved by rejecting marks which have a duration less than 85 milliseconds and by re-
setting the fault timer only when two marks are separated by a 'dot' space. A timing
diagram of the operation of these circuits is shown in Figure 2-18.
D1 is a retriggerable monostable which converts 1020 Hz keyed tone bursts into pulses.
During a mark, D1:7 enables the one-shot timer D2 which will time out after 85
milliseconds.
When D2 times out and the output goes low V4 conducts and the D1 time constant
increases to 19 milliseconds. The longer time constant prevents small drop outs due to
speech from corrupting the remainder of the mark pulse. The low output of D2 enables
monostable D1:10 which is repeatedly retriggered by the oscillator signal input to D1:11.
This maintains a logic high at the output D1:10 until D2 is reset by the negative-going
signal at D2:6, and D1:10 times out after 70 milliseconds. The output waveform from
D1:10 is a reconstruction of the input ident marks, delayed by 85 milliseconds.
D1:10 and D4:6 in conjunction operate as a double pulse detector. The end of the mark
signal at D1:10 triggers D4:6, a non-retriggerable monostable with a time constant of
223 milliseconds. Providing that a positive-going edge from the next mark appears at
D1:10 within the 223 milliseconds gate period, both D1:10 and D4:6 will be high,
disconnecting the diode clamp V5, and resetting D3. D3 is a 35-second time delay which
is repeatedly reset, if the ident is correctly decoded, thus preventing it from timing out
and alarming. In the non-alarmed state a logic high from D3 enables monostable D4
which is repeatedly retriggered by the oscillator signal from D3, giving a pass signal to
the controller via buffers D5:4 and D5:12. If the ident fails, a logic low at D3:6 will
activate the 35 seconds time delay, D3 will time out and D4:9 will be cleared causing a
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H4A71110 SECTION 2
fault to be signalled. If the ident fault clears within the 35 seconds period D3 will be
reset.
Monostables D1 and D4 provide a fail-safe feature. If the oscillator in either D2 and D3
fails, D1:10 or D4:9 will time out and a fault signal will be generated.
A continuous input tone will also cause the monitor to generate a fault signal. Under
these conditions D1:7 will be continually retriggered causing D2 to time out, enabling
D1:10. D4:6 will remain low, preventing a reset on D3; this will cause D3 to time out after
35 seconds and signal a fault.
A facility for inhibiting the ident fault alarm is provided by D5:14 and V10 when a logic
high is applied to XMA:8.
S1 provides an ident fault test facility which, if operated just after a reset has occurred,
enables the timing period of D3 to be checked and the ident fault indicator to be
functionally tested. Two on-board LED indicators V8 and V9 display the ident mark
element pulses and reset pulses for the 35 seconds timer.
Terminals X1,X2 and X4,X5 are strapped together under alignment conditions to allow
adjustment of the upper frequency limits of the voltage-controlled oscillators D7 and D10
using RV4 and RV7 respectively. Similarly, X2,X3 and X5,X6 are strapped together to
allow adjustment of the lower frequency limits using RV5 and RV8.
Figure 2-17 MFI Quadrature Phase Detector Waveforms
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H4A71110 SECTION 2
Figure 2-18 MFI Ident Fault Detection Timing Diagram
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H4A71110 SECTION 2
2.3.16 MBD - Monitor Bearing Counter and Data Acquisition

Components Monitor Bearing Counter and Data Acquisition 1A72565
Subunits MBD Main Board 1A72566
The MBD module consists of three main sections: the monitor bearing counter (MBC),
the data acquisition circuitry, and the communications interface between the two racks of
a dual DVOR.
The MBC circuitry measures the phase difference between the 30 Hz AM and 30 Hz FM
signals and displays the result in degrees on a digital readout. It allows for offsetting the
bearing of the monitor antenna, and it will initiate an alarm if the station bearing is out of
tolerance.
The 30 Hz square wave signals from the MFI module are used to control the contents of
a 5-stage counter. The counter is started by the 30 Hz FM and stopped by the 30 Hz AM
signal. The clock input to the counter is derived from a 4.32 MHz crystal oscillator within
this module. The contents of the counter at the end of a counting period is equal to the
phase difference of the two 30 Hz signals. This value, which is the station bearing error,
is displayed on the digital readout. The counter contents are the average of 32 counting
periods.
A digital delay circuit provides a phase offset to correct for the bearing of the monitor
antenna. This is programmed by a group of BCD rotary switches which have a resolution
of 0.01 degrees.
A fault detection circuit examines the contents of the counter at the end of each counting
cycle and a fault is registered if the bearing error exceeds a preset limit. These limits are
adjustable in increments of 0.1 degrees up to a maximum of 0.9 degrees.
A 5-digit display is used, which can display bearings from -172 to +188 degrees. The full
range of the display is useful for the measurement of error curves. The display, which
has a resolution of 0.01 degrees, can operate in either one of two modes:
a. ABSOLUTE, which displays the actual VOR bearing as received at the
monitor antenna.
b. RELATIVE, which displays the bearing error after the offset due to the
position of the monitor antenna has been cancelled.
The bearing counter is also able to be read by the CTU.
The data acquisition circuitry consists of a frequency counter, an analogue-to-digital
converter, signal activity detectors and status inputs with the appropriate input
multiplexers and signal conditioning circuitry. All these are able to be read by the CTU.
The communications interface provide a serial link between the Control and Test Units in
the two racks of a dual installation.
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H4A71110 SECTION 2
2.3.16.1 MBD Main Board

Drawing 72566-3-05
Data +24 volts
-15 volts
MBC counter resolution 0.01 degrees
MBC counter range -172 to +188 degrees
MBC clock frequency 4.320 MHz ±40 Hz
MBC bearing update rate 1.214 seconds
MBC bearing error accept range 0 to ±0.9 degrees in
increments of 0.1
MBC delay offset range 0 to 360 degrees in
increments of 0.01
MBC switch modes ABSOLUTE
RELATIVE
TEST
Voltage measurement accuracy ±0.4%
Frequency measurement accuracy 0.02%
The circuitry of the MBD Main Board can be broadly divided into eight functional groups:
a. Bus Interface to the Control and Test Unit (CTU).
b. Monitor Bearing Counter.
c. Fault and Status Signal Input.
d. Signal Voltage Measurements.
e. Signal Frequency Measurements.
f. Signal Activity Detectors.
g. Serial Communications Interface.
h. Power Supplies.
2.3.16.1.1 Bus Interface to the CTU

Drawing 72566-3-05, Sheet 10
The extended CTU bus consists of eight data lines (XDATA0 to XDATA7) ' 8 address
lines (7 address lines, XADDR0 to XADDR6 plus an active low board select line
XPNDR_CS) and seven control lines (XRD - active low read, XWR - active low write,
XDT_R - data direction -when high, data is written to module, XDEN - active low data
enable, XRES - active high reset, XINT - active high interrupt to the processor, and
BUS_SUPPLY_OK, active high signal indicating that all circuitry connected to the bus is
powered).
The address and control lines are buffered by D26 and D27. D25 is a bi-directional
buffer for the data lines. Its outputs are enabled whenever both BUS_SUPPLY_OK and
BUFEN (from the address decoder PLD, D22) are active high.
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H4A71110 SECTION 2
The buffered write signal out of D27 is delayed through D28A and D28B and associated
resistors and capacitors so that the write signal into D22 occurs after any transients on
the address and data buses (due to crosstalk) have settled.
R147, C61 and D28C provide a power up reset to D23.
The input to D28D is an active LOW wired-or interrupt connection. The output of D28D is
buffered and inverted by D24B which is directly connected to an interrupt on the CTU
Processor Board.
BUS_SUPPLY_OK is HIGH only when all circuitry connected to the bus is powered.
When LOW, it is used to disable bus drivers to ensure that no unpowered circuitry tries
to power up through the IC input protection diodes. In normal operation
BUS_SUPPLY_OK is HIGH. When BUS_SUPPLY_OK goes LOW, the output of D24C
will then go HIGH causing the outputs of D25 to go to a high impedance state.
Address decoder PLD D23A provides the interface to the bus from the CTU. It also
provides chip select signals to programmable devices on the MBD, latched outputs
(mainly to control multiplexers) and status inputs.
An internal signal R_W_EN (Read/Write Enable) of D23A is active high only when:
input BUS_PWR_OK is active HIGH
input PWR_UP_RESET is inactive LOW
input RESET is inactive LOW
input NBOARD_SEL is inactive LOW
Output BUFEN is active HIGH when both R_W_EN and input DEN are active HIGH. It is
used in the enabling of the octal transceiver D25.
Output IO_RD is inverted input NRD. This is used as a control input to the analog to
digital converter, N18, on sheet 7 of the circuit diagram, 72566-3-05.
Output IO_SEL is active HIGH when both inputs NRD and NWR are active LOW. This is
used as a control input to the analogue to digital converter, N18, on sheet 7 of the circuit
diagram, 72566-3-05.
Output CS0 (Chip Select 0) is active LOW when internal signal R-W-EN is active HIGH,
input NRD is active LOW and ADDR6 to ADDR3 represent addresses in the range 00H
to 07H ('H' indicating hexadecimal code). It is used for reading monitored bearing
measurement values from D1 (sheet 2 of circuit diagram, 72566-3-05). Address 00H
provides the "0.01" degrees digit; address 01H the “0.1” degrees digit; address 02H the
“1" degrees digit; address 03H the “10” degrees digit; and address 04H the "100"
degrees digit.
Output CS1 is active LOW when internal signal R_WE_N is active HIGH, input NRD is
active LOW and ADDR6 to ADDR0 represent address 08H. It is used for reading the
state of fault signals from the monitors in its rack (through buffer D8 - see sheet 4 of
circuit diagram, 72566-3-05).
Output CS2 is active LOW when internal signal R_W_EN is active HIGH, input NRD is
active LOW and ADDR6 to ADDR0 represent address 09H. It is used for reading the
state of fault signals from the monitors in the other rack of a dual (through buffer D9 -
see sheet 4 of circuit diagram, 72566-3-05).
active LOW and ADDR6 to ADDR0 represent address 0AH It is used for reading the
state of ancillary fault signals from the monitors in its rack (through buffer D10 - see
sheet 4 of circuit diagram, 72566-3-05).
active LOW and ADDR6 to ADDR0 represent address 0BH. It is used for reading the
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H4A71110 SECTION 2
state of equipment status and ancillary fault signals from its rack (through buffer D11 see
sheet 4 of circuit diagram, 72566-3-05).
active LOW and ADDR6 to ADDR0 represent address 0CH It is used for reading the
activity status of signals from its rack (through buffer D19 - see sheet 8 of circuit
diagram, 72566-3-05).
Output CS6 is active LOW when internal signal R_W_EN is active HIGH and ADDR6 to
ADDR3 represent addresses in the range 20H to 27H. It is used for reading from and
writing to the serial interface chip, D20 (see sheet 9 of circuit diagram, 72566-3-05).
ADDR1 represent addresses in the range 28H to 29H. It is used for reading from and
writing to the analogue to digital converter chip, N18 (see sheet 7 of circuit diagram,
72566-3-05).
ADDR2 represent addresses in the range 2CH to 2FH. It is used for reading from and
writing to the counter/timer chip, D18 (see sheet 9 of circuit diagram, 72566-3-05).
ADDR3 represent addresses in the range 30H to 37H. This output is not currently used
on the MBD.
Output OUT0 latches the state of DATA0 on the failing edge of NWR when internal
signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent address 10H. It is used
as the COUNT_EN (counter enable) control to the counter/timer D18:14 (on sheet 9 of
circuit diagram, 72566-3-05).
signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent address 11H.
OUT1 to OUT3 provide the 3-bit selection address (COUNT_MUX_ADR0 to
COUNT_MUX_ADR2 respectively) for the counter/timer input multiplexer D15 (on sheet
9 of circuit diagram, 72566-3-05).
OUT4 to OUT6 provide the 3 bit selection address (ADC_MUX_ADR0 to
ADC_MUX_ADR2 respectively) for the analogue to digital converter input multiplexers
N1 and N2 (on sheet 5) and N3 and N4 (on sheet 6 of circuit diagram, 72566-3-05).
Output OUT7 is active HIGH if the state of DATA3 to DATA0 is 0H or in the range 4H to
0FH on the failing edge of NWR when internal signal R_W_EN is active HIGH and
ADDR6 to ADDR0 represent address 13H.
Output OUT8 is active HIGH if the state of DATA3 to DATA0 is 1H on the falling edge of
NWR when internal signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent
address 13H.
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H4A71110 SECTION 2
Output OUT9 is active HIGH if the state of DATA3 to DATA0 is 2H on the failing edge of
NWR when internal signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent
address 13H.
Output OUT10 is active HIGH if the state of DATA3 to DATA0 is 3H on the failing edge
of NWR when internal signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent
address 13H.
OUT7 to OUT10 are four mutually exclusive, active HIGH enable signals
(ADC_MUX_SEL0 to ADC_MUX_SEL3 respectively) which enable the output of one
only of the analogue to Digital Converter Input Multiplexers N1 and N2 (on sheet 5) and
N3 and N4 (on sheet 6 of circuit diagram, 72566-3-05).
Output OUT11 is set active HIGH if the state of DATA3 to DATA0 is DH or FH on the
failing edge of NWR when internal signal R_W_EN is active HIGH and ADDR6 to
ADDR0 represent address 13H. The state of this output will not change unless DATA3 to
DATA0 represent a value in the range CH to FH on the failing edge of NWR when
internal signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent address 13H.
This output, when HIGH, is used to activate relay K3 on the Display Board of the MBD
(see circuit diagram 72567-3-03).
Output OUT12 is set active HIGH if the state of DATA3 to DATA0 is EH or FH on the
failing edge of NWR when internal signal R_W_EN is active HIGH and ADDR6 to
ADDR0 represent address 13H. The state of this output will not change unless DATA3 to
DATA0 represent a value in the range CH to FH on the failing edge of NWR when
internal signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent address 13H.
This output, when HIGH, is used to activate relay K2 on the Display Board of the MBD
(see circuit diagram 72567-3-03).
Output OUT13 is set active HIGH if the state of DATA3 to DATA0 is FH on the failing
edge of NWR when internal signal R_W_EN is active HIGH and ADDR6 to ADDR0
represent address 13H. The state of this output will not change unless DATA3 to DATA0
represent a value in the range CH to FH on the failing edge of NWR when internal signal
R_W_EN is active HIGH and ADDR6 to ADDR0 represent address 13H. This output,
when HIGH, is used to activate relay K1 on the Display Board of the MBD (see circuit
diagram 72567-3-03).
signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent address 14H. It is used
as the FAULT_TEST control to the MBC, D1 (see sheet 2 of circuit diagram,
72566-3-05).
signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent address 19H. This
output is not currently used on the MBD.
signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent address 1AH. This
output is not currently used on the MBD but its state is able to be read back by the CTU
as described below.
signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent address 1BH. This
as described below.
signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent address 1CH. This
as described below.
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H4A71110 SECTION 2
signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent address 1DH. This
as described below.
Inputs IN3 to IN0 are connected to DATA3 to DATA0 respectively while NRD is active
LOW when internal signal R_W_EN is active HIGH and ADDR6 to ADDR0 represent
address 38H. This enables the status of the counter/timer, analogue to digital converter
and the ident measuring circuitry to be read by the CTU.
Latched outputs OUT3 to OUT0 are connected to DATA3 to DATA0 respectively while
NRD is active LOW when internal signal R_W_EN is active HIGH and ADDR6 to ADDR0
represent address 39H. This capability is provided for test purposes.
represent address 3AH. This capability is provided for test purposes.
represent address 3BH. This capability is provided for test purposes.
BUS_SUPPLY_OK signal control circuitry is shown on sheet 11 of the circuit diagram
72566-3-05. In normal operation transistor V24 is ON and transistor V25 is OFF and
R154 attempts to pull BUS_SUPPLY_OK to HIGH. When the local +5 volts supply
voltage fall below about 4 volts, V24 turns OFF and V25 turns ON pulling
BUS_SUPPLY_OK to LOW.
2.3.16.1.2 Monitor Bearing Counter

The monitor bearing counter (MBC) circuitry consists of five main components: bearing
counter PLD; switches to set the operating conditions; a crystal oscillator; bearing fault
signal processing; and bus interface.
A schematic representation of the MBC PLD, D1 is shown in Figure 2-19.
The timing for the MBC is provided by the 4.32 MHz input clock signal CLOCK_IN. It is
divided internally by 4 to provide a 1.08 MHz clock signal, brought out of the PLD at
CLOCK_OUT. The 1.08 MHz clock enables a measurement resolution of 0.01 degree on
the phase difference between the two 30 Hz input signals (1.08 MHz = 36.000 x 30 Hz).
The sequence counter provides the timing control of the MBC. The 1.08 MHz clock is
successively divided by 4096, 5 and 64 to give a cycle time of 1 310 720 cycles or 1.214
seconds.
The divide-by-5 counter is used to provide the timing for CHAR0 to CHAR4, the
character select output signals for the five multiplexed 7-segment LED displays on the
MBD front panel. Each of the CHAR_ signals is HIGH for 4089 clock cycles or 3.79
milliseconds and LOW for 16 391 clock cycles or 15.18 milliseconds for a frequency of
52.73 Hz. A delay of seven clock cycles or 6.5 microseconds exists from a CHAR_
signal going LOW and the next CHAR_ signal going HIGH.
The internal signal COUNT_EN is set HIGH on the next clock pulse following a count of
0 on the sequence counter and is set LOW on the next clock pulse following a count of
1 152 000 on the sequence counter. (1 152 000 = 32 x 36 000; the count time is set for
32 sets of bearing readings to obtain an averaged result.)
The internal signal LATCH is set HIGH for one clock period when the count on the
sequence counter is 1 153 023.
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H4A71110 SECTION 2
Figure 2-19 Monitor Bearing Counter PLD
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H4A71110 SECTION 2
The internal signal PRESET is set HIGH for one clock period when the count on the
sequence counter is 1 269 763.
The output signal DATA_VALID is set LOW on the next clock pulse following a count of
1 110 016 on the sequence counter and is set HIGH on the next clock pulse following a
count of 1 153 024 on the sequence counter. DATA_VALID being LOW indicates that
measurements of the bearing reading may be invalid - due to a new reading being
loaded into the output latches. It is low for 43 008 clock cycles or 39.8 milliseconds and
goes HIGH following loading of a new bearing measurement into the bearing counter
latches.
The internal and output signal DISPLAY_EN is set LOW on the next clock pulse
following a count of 1 152 000 on the sequence counter and is set HIGH on the next
clock pulse following a count of 1 259 520 on the sequence counter. It goes LOW for
107 520 clock cycles or 99.6 milliseconds following the end of the bearing measurement.
It is used for display blanking to indicate a new reading is to be displayed.
Outputs CLK_13HZ and CLK_34KHZ are connections from the sequence counter
stages brought out for use by other circuitry. CLK_13HZ is the 1.08 MHz clock divided
by 81 920 to give 13.1836 Hz and CLK_34KHZ is the 1.08 MHz clock divided by 32 to
give 33.75 kHz.
Changes of input signal ABS_NREL are detected and cause the Sequence Counter to
be preset to a count of 1 269 760, and COUNT_MEN, PRESET, LATCH, DATA_VALID
and DISPLAY_EN all to be reset to LOW. Thus when a change occurs between absolute
and relative measurements, the sequence counter immediately begins a new
measurement cycle.
Active low input signal N_SIG_1_N is connected to the input of an edge detector. While
input signal ABS_NREL is HIGH, negative transitions on N_SIG_1_IN will cause the
counter gate to be set and positive transitions on N_SIG_1_IN will be ignored. However.
while ABS_NREL is LOW the transitions of N_SIG_1_IN which set the counter gate are
determined by the state of input signal SIG_1_PH_INV. While both SIG_1_PH_INV. and
ABS_NREL are LOW, negative transitions on N_SIG_1_IN will cause the counter gate to
be set and positive transitions on N_SIG_1_IN will be ignored. However, while
ABS_NREL is LOW and SIG_1_PH_INV. is HIGH, positive transitions on N_SIG_1_IN -
IN will cause the counter gate to be set and negative transitions on N_SIG_1_IN will be
ignored.
Active low input signal N_SIG_2_IN is also connected to the input of an edge detector
which only detects negative transitions. If ABS_NREL is HIGH, negative transitions on
N_SIG_2_IN will cause the counter gate to be reset. The counter gate output pulses
then represent the time difference between the negative transitions of the input signals
N_SIG_1_IN and N_SIG_2_IN.
Negative transitions on N_SIG_R_IN also cause the programmable delay counter to be
loaded with the state of bearing offset switches S3 to S7 and commence counting down
to zero at which time the counting ceases. S4 to S7 are 10 position rotary switches with
BCD (binary coded decimal) output. The programmable delay counter consists of four
cascaded decade counters and a final 1-bit binary counter. If ABS_NREL is LOW, the
programmable delay counter reaching a count of zero causes the counter gate to be
reset. The counter gate output pulses then represent the time difference between the
selected transitions of the input signal N SIG_1_IN and the negative transitions of the
input signal N_SIG_2_N plus the state if the bearing offset switches.
To provide averaging of the measurements, 32 time difference measurements are taken
for each output reading. The divide-by-32 counter following the counter gate corrects for
this and the following bearing counter measures the average time difference. At the
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H4A71110 SECTION 2
beginning of a measurement cycle, the divide-by-32 counter is reset to zero by the

PRESET signal.
The bearing counter consists of four cascaded decade counters and a final 3-bit binary
counter. If ABS_NREL is HIGH, the PRESET signal will cause the bearing counter to be
preset to zero. The bearing counter then measures the average time difference between
the negative transitions of the input signals N_SIG_1_IN and N_SIG_2_IN. With a clock
frequency of 1.08 MHz, this time difference represents the phase difference between the
two input signals in multiples of 0.01 degrees.
If ABS_NREL is LOW, the PRESET signal will cause the bearing counter to be preset to
a value of 62 799 (provided input signal FLT_TEST is LOW - if FLT_TEST is HIGH, the
bearing counter is preset to a value of 62 499).
The bearing counter counts to a value of 79 999 before it rolls over to zero. Count values
from 00 000 to 39 999 ( 000.00 to 399.99 degrees) are considered positive. Count
values from 40 000 to 79 999 are considered negative, representing bearings in the
range -399.99 to -000.00 degrees. The most significant bit of the bearing counter is used
as the sign bit - a HIGH indicating a negative number.
In relative mode, the preloaded value of 62 799 therefore represents a bearing of
-172.00 degrees. The bearing offset switches are nominally set to a value equal to
172.00 minus the absolute monitor bearing so that the bearing count has a nominal
value of 00 000.
Figure 2-20 shows counter gating in absolute and relative modes.
Figure 2-20 Bearing Counter Gating
At the end of the count period set by signal COUNT_EN being high, the contents of the
bearing counter are loaded into latches by signal LATCH. On detection of a change of
input signal ABS_NREL the latches are loaded with all l's to indicate that valid data is not
held in the latches.
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H4A71110 SECTION 2
A multiplexer with three control lines selects the count output of each of the five counter
stages to output to DATA0 to DATA3. When the fifth counter stage is selected, a value
of 2 is added to the count if the count is greater than 3. The output from this counter
stage is therefore 0 to 3 for positive counts and 6 to 9 for negative counts. Negative
counts can then be converted to negative numbers by taking the 9's complement.
The control inputs to the above multiplexer may come from two sources. When input
signal NADR_STROB is HIGH the multiplexer is controlled from the three outputs of the
divide-by-5 stage of the sequence counter to drive the front panel multiplex 7-segment
display. When NADR_STROB is driven LOW by the CTU bus interface, the multiplexer
is controlled from the three input signals ADR0 to ADR2 to enable the CTU to read the
bearing count.
The 7-segment encoder takes the multiplexed count data and sign and generates the
signals required to drive the display segments. Conversion of negative counts to
negative numbers is included. If the count input to the decoder is not in the range 0 to 9
the segments are all turned off. Thus when input signal ABS_NREL is detected as
having changed state, the front panel bearing display will show -0 with the four right
hand digits blank. When input signal DISPLAY_TEST is HIGH all display segments are
illuminated.
The fault processor compares the latched bearing count with the limit value set by the
input signals FLT_LIM0 to FLT_LIM3. These inputs are driven by S8, a 10-position
rotary switch with BCD output. In relative mode, if the absolute value of the latched
bearing count is less than or equal to the set limit value, the output NO_FAULT produces
a positive pulse of one clock period duration immediately following the PRESET pulse. In
Relative mode, the NO_FAULT pulses are inhibited.
The NO-FAULT output pulses are used to retrigger two one-shots D4A and D4B (see
sheet 3 of circuit diagram, 72566-3-05) each of which has a nominal pulse period of 1.6
seconds. Since D4B is only enabled if D4A has not timed out, two consecutive
NO_FAULT pulses are required to give a HIGH for the BEARING_OK output. The
BEARING_OK output is fail-safe in that failure of the NO_FAULT pulses for any reason
will cause BEARING_OK to go inactive LOW. Comparator N20A is used to convert the 5
volts logic BEARING_OK to the 15 volts logic output NOT_BEARING_FAULT for
compatibility with other circuitry.
D2A (see sheet 3 of circuit diagram, 72566-3-05) and its associated components form a
crystal oscillator operating at 4.32 MHz. D28 to D2D provide buffering of the clock signal.
D7 (see sheet 2 of circuit diagram, 72566-3-05) is a tristate buffer. When addressed by
the CTU, signal BEARING_CS from the address decoder causes the outputs of D7 to
drive the internal data bus with the MBC data and the logic state of signals DATA_VALID
and ABS_NREL BEARING_CS being active LOW, through D3, also pulls D1 input
NADR_STROB to LOW. This enables the state of internal address bus signals ADR0 to
ADR2 to select the bearing count digit to be put on the internal data bus.
All input signals to D1 are buffered through D3. When signal MBC_OFF (from the +15
volts supply detector - see sheet 11 of circuit diagram, 72566-3-05) goes HIGH the
outputs of D3 are placed in a high impedance state and the output signals are pulled
LOW by the resistors in RN4. This ensures that when the MBC PLD is powered down, it
is isolated from all power sources.
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H4A71110 SECTION 2
2.3.16.1.3 Fault and Status Signal Input

The fault and status signal Input circuitry consists of four tristate buffers, D8 to D11, with
level shifting circuitry on the inputs, as appropriate, to convert from 15 volts and 24 volts
logic levels to the 5 volts logic levels of the MBD module.
The level shifting circuitry on the inputs of D9 to D11 each consists of a resistive divider
to reduce the voltage to a nominal one-third. If the input signals exceed a nominal 15
volts, the input protection diodes of D9 to D11 will clip the input voltage to a safe value.
The level shifting circuitry on the inputs of D8 has lower value series resistors to allow for
the pull-down resistors on the Display Board in parallel with the resistors in RN8. Diodes
V1 to V5 provide protection from overvoltage should the Display Board be disconnected.
2.3.16.1.4 Signal Voltage Measurements

Drawing 72566-3-05, Sheets 5, 6, 7
The analogue input signal conditioning circuitry consists of four 8-input analogue
multiplexers with a common output AD_IN, plus input signal conditioning circuitry. In the
signal conditioning circuitry, all gain determining resistors are 0.1% tolerance to maintain
measurement accuracy.
The power supply monitoring inputs (except for the +24 volts SUPPLY VOLTAGE) have
a simple R-C filter with a time constant in the range 5.0 milliseconds (for the +5
V_SUPPLY_VOLTAGE) to 9.2 milliseconds (for the -45 V_SUPPLY_VOLTAGE). The
+24 V_SUPPLY_VOLTAGE input has a second-order active filter with both time
constants equal to 100 milliseconds. This gives a 6 dB frequency of 1.59 Hz and at least
50 dB attenuation of 30 Hz ripple on this supply. In all cases scaling is provided by input
resistive attenuators.
All signal monitoring inputs (i.e. not supply voltage inputs) have an output buffer to
maintain a low impedance drive to the multiplexers. Some have simple input R-C
filtering, some have second order active filters without gain and some have second order
active filters with gain. All active filters have the same filtering characteristics as the +24
volts supply voltage input filter.
Inputs CARRIER_FORWARD_LVL, BLENDING_FUNCTION_USB and
BLENDING_FUNCTION_LSB have peak detectors. The positive peak detection is
achieved by including a diode in series with the op amp output to charge a capacitor to
the positive peak value. Since the two blending function inputs have inverting first
stages, the positive output voltages represent the negative peak input voltage.
Inputs 30HZ_SINE_REFERENCE and IDENT_LVL have peak-to-peak detectors. These
are achieved by adding before the positive peak detector a stage which stores the
negative peak voltage on a capacitor. This negative peak voltage is then added to the
positive peak voltage and stored on the output capacitor. The
30HZ_SINE_REFERENCE input has an additional input scaling and buffer stage.
Since the IDENT_LVL input signal is only present during Ident transmission, one-shot,
D13A produces an signal IDENT_LVL_READY to the CTU (via the bus) to indicate when
input signal IDENT_LVL is active and a voltage measurement can be made.
Resistors R104 to R106 provide a small positive bias on the inverting input of N17B
when no Ident signal is present. This ensures that the output of N17B is near the op amp
-15 volts negative rail when the next Ident signal commences and a positive pulse will be
generated to trigger D13A.
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H4A71110 SECTION 2
The analogue to digital converter (ADC) N18 is a 12-bit ADC interfaced to the 8-bit bus.
It is configured to accept input voltages in the range ±5 volts. Opamp N17A provides
impedance matching between the signal conditioning circuitry and the ADC input which
has an input impedance less than 20 kilohms.
2.3.16.1.5 Signal Frequency Measurements

The frequency measurements circuitry consists of a frequency counter, D18, which
interfaces to the bus and an input multiplexer, D15.
Multiplexer D15, under control from the CTU, selects one of four inputs
(COMMUTATION, 9960HZ_CLOCK, 30HZ_CLOCK and 400HZ_CAL) for connection to
the counter for frequency measurement.
D18 contains three counters whose operating mode is set by the CTU via the bus.
D18 counter 0 is programmed to divide the frequency of its input signal (from the serial
interface) by a number such that its output signal (400HZ_CAL) has a frequency of 400
Hz. This signal is used to prove correct operation of the counter.
D18 counter 1 is programmed to produce a negative output pulse with a nominal
duration of 1 second. The signal selected by D1 5 is used to clock this counter.
Following COUNT_EN (GATE1 of D18) going HIGH, OUT1 goes LOW for the number of
clock cycles programmed from the CTU and then goes HIGH again. The number of
clock cycles programmed into counter 1 is equal to the nominal frequency (in Hz) of the
selected input signal.
OUT1 of D18 is inverted in D6C to provide a signal, COUNTER_STATUS, to the CTU
(via the bus) that the frequency measurement is in progress. COUNTER_STATUS is
also used to gate counter 2 of D18.
D18 counter 2 is programmed to count the cycles of its 33.75 kHz input clock while its
input gate signal is HIGH. If COUNT1 represents the count loaded into counter 1 and
COUNT2 represents the count of counter 2 after COUNTER_STATUS goes LOW, then
the input signal frequency, F1, is given by:
F1 = COUNT1/COUNT1 . 33750 Hz.
2.3.16.1.6 Signal Activity Detectors

The signal activity detector circuitry consists of four signal activity detectors built around
comparators and analogue one-shots, a signal activity detector based on a digital one-
shot and a tristate buffer to enable the CTU to read the state of the five detectors.
The tristate buffer, D19, is also used to monitor the state of the switched 5 volts supply
to the MBC circuitry and the state of the ident keying signal.
The input signal 30HZ_CLOCK is a nominal 15 volts logic level signal. It will only cause
the output of N22A to toggle if its HIGH voltage is greater than a nominal value of 12.6
volts and its LOW voltage is less than a nominal value of 2.9 volts (due to the hysteresis
around N22A). The nominal pulse width of D16A is 75 milliseconds. Therefore provided
the frequency of input signal 30HZ_CLOCK is greater than a nominal 13.3 Hz and meets
the input logic level excursion specification, one-shot D16A will remain continuously
triggered and the output to D19 will remain HIGH.
The input signal 9960HZ_CLOCK is also a nominal 15 volts logic level signal and
therefore has the same comparator circuitry as the 30HZ_CLOCK input signal. The
nominal pulse width of D16B is 200 s. Therefore provided the frequency of input signal
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H4A71110 SECTION 2
9960HZ_CLOCK is greater than a nominal 5.0 kHz and meets the input logic level
excursion specification, one-shot D16B will remain continuously triggered and the output
to D19 will remain HIGH.
The input signals SBAND_SW_DRIVE_ODD and SBAND_SW_DRIVE_EVEN are
switching signals between normal levels of +1 volts and -42 volts. They will only cause
the output of N22C and N22D to toggle if their HIGH voltage is greater than a nominal
value of -5.2 volts and their LOW voltage is less than a nominal value of -37.7 volts (due
to the hysteresis around N22C and N22D). The nominal pulse width of D17A and D17B
is 40 milliseconds. Therefore provided the frequency of these input signals is greater
than a nominal 25 Hz and they meet the input logic level excursion specification, one-
shots D17A and D17B will remain continuously triggered and the outputs to D19 will
remain HIGH.
Because of the long time between Ident transmissions, an analogue one-shot could not
be used for the IDENT_KEYING signal activity detector. Instead a digital one-shot,
implemented in a PLD, is used. A schematic representation of this PLD, D23B is shown
in Figure 2-21. The 15 volts logic level input signal IDENT_KEYING is converted to 5
volts logic level of D23 by resistors RN21D and RN14:1. Diode V20 provides protection
to D23 against excessive input voltage.
Figure 2-21 Ident Keying One-Shot PLD
Input signal CLK_F is a 13.18 Hz clock from the MBC PLD. It has a sufficiently high
frequency to detect the edges of the Ident signal pulses which may be as short as 100
milliseconds. On positive edges of input signal ONE_SHOT_IN the 5-stage binary
counter is asynchronously reset to a count of zero and the flip flop output
ONE_SHOT_OUT is synchronously set HIGH.
Input signal CLK_S is the 0.824 Hz DISPLAY_EN signal from the MBC PLD. It is used to
clock the 5-stage binary upcounter. This counter counts up from zero until it reaches a
binary count of 11111 at which time counting ceases and the count is held at 11111.
While the counter maintains a count of 11111 and provided another positive edge of
input signal ONE_SHOT_IN is not detected, flip flop output ONE_SHOT_OUT is
synchronously reset LOW.
Depending on the timing relationship between the positive edges of input signals
ONE_SHOT_IN and CLK_S, output ONE_SHOT_OUT will be HIGH for between 30 and
31 periods of CLK_S (36.4 seconds to 37.6 seconds) provided the one-shot is not
retriggered. Thus, provided positive transitions of input signal ONE_SHOT_IN are not
greater than 36 seconds apart, output ONE_SHOT_OUT will remain HIGH to indicate
correct operation of the monitored signal.
2-93
H4A71110 SECTION 2
2.3.16.1.7 Serial Communications Interface

The serial interface circuitry consists of a UART (Universal Asynchronous Receiver
Transmitter) D20 with its associated crystal oscillator using crystal G2, and RS-422
interface consisting of transmitter D21 and receiver D22.
Resistor R133 provides a 100 ohms termination for the receiver input (if required).
2.3.16.1.8 Power Supplies

The power supplies circuitry consists of a switching regulator producing the +5 volts
supply and a FET switch to control the +5 volts supply to the MBC circuitry.
The +5 volts switching regulator uses N 19 as its controller operating at a nominal 50
kHz. When input signal N_MBD_ON (a direct connection from the CTU) is HIGH the
regulator is OFF. It is turned ON when N_MBD_ON is pulled LOW either by the CTU or
at the test points XT4 and XT5.
Inductor L1 and capacitors C63 to C65 provide input filtering to smooth the current
pulses drawn by the regulator. Schottky diode V22 is the commutation diode, providing a
conduction path for the current in storage inductor L2 when the regulator switches off.
Capacitors C67 to C69 provide output filtering.
FET transistor V21 is used to control the switching of the +5 volts supply to the MBC
circuitry. The +15 volts supply to the MBD module is the +15 volts Monitor Supply which
can be switched OFF by the CTU to conserve power when monitoring is not required.
When the +15 volts supply fails below a nominal 10.0 volts, V22 is turned OFF and
power is removed from the MBC circuitry. When the +15 volts supply rises above a
nominal 10.9 volts, V22 is turned ON and power is restored to the MBC circuitry.
The 5 volts logic level signal MBC_OFF (derived from the FET control signal) is used to
control the tristate buffer D3 (on sheet 2) to remove all input signals to the MBC circuitry.
Green LED H1 is a front panel indicator that the MBD is powered.
2-94
H4A71110 SECTION 2
2.3.16.2 Display Board

Drawing 72567-2-03
Data +15 volts
-15 volts
+24 volts
Display range -172 to +188 degrees
Display resolution 0.01 degrees
Display multiplex frequency 52.7 Hz
Bearing update rate 1.214 seconds
Digital voltmeter input ranges ±2.0 volts
±10 volts
±20 volts
±100 volts
The circuitry of the Display Board (MBD) can be broadly divided into three functional
groups:
a. Bearing Display.
b. Status Indicators.
c. Digital Voltmeter Inputs.
2.3.16.2.1 Bearing Display

The bearing display consists of six 7-segment LED displays. Five are used to display the
measured bearing; the sixth is used to display the bearing sign. The five bearing
displays are multiplexed.
An active HIGH on one only of the input signals CHAR0 to CHAR4 selects the display to
be illuminated. The segment data for the selected display is provided on active LOW
input signals DSP_SEG_A to DSP_SEG_G.
An active LOW on input signal N_DSP_SIGN causes the centre horizontal segment of
the sixth display to be illuminated as a '-‘ sign.
An active LOW on input signal DSP_D_P causes the right hand decimal point of the
units digit display to be illuminated. DSP_D_P is the inverted state of DISPLAY_EN (by
D24A on the MBD Main Board - see sheet 2 of Drawing 72566-3-05). Since
DISPLAY_EN pulses LOW for approximately 100 milliseconds when the bearing
measurement is updated, the bearing display decimal point will flash OFF each time the
measurement is updated.
2.3.16.2.2 Status Indicators

H7 to H12 are illuminated when the corresponding _OK input signals are active HIGH.
Input signal DISPLAY_TEST is normal inactive LOW. When DISPLAY_TEST goes
HIGH all of the LEDs H7 to H14 are illuminated to prove correct operation of the drive
circuitry.
Amber LED H13 is illuminated when input FAULT_TEST is active HIGH to indicate that
the MBC is in test and that the bearing count is not correct. The green LED H7 should be
extinguished during fault testing.
2-95
H4A71110 SECTION 2
Red LED H14 is illuminated when input ABSOLUTE is active HIGH to indicate that the
bearing measurement mode is in Absolute and the bearing accuracy is no longer being
monitored.
2.3.16.2.3 Digital Multimeter Inputs

A resistive divider consisting of 0.1% tolerance resistors R2 to R6 provides a 1 Megohm
impedance for the DVM (digital voltmeter) input connections. Relays K2 and K3 select
the tap off the divider to give four selectable full scale ranges. When both K2 and K3 are
activated, K1 is also activated to change the gain of operational amplifier N1 from unity
to 2.5 times. This enables a full scale range of 2 volts to produce 5 volts to the analogue-
to-digital (A-D) converter.
The relays are controlled by the active HIGH input signals DMM_MUX_ADR0 to
DMM_MUX_ADR2.
2.3.16.3 Top Bay Motherboard

The interwiring to the major modules mounted in the top bay of the rack is accomplished
by use of a motherboard. The top rack mounts the following modules:
a. MRF - Monitor RF Amplifier.
b. MSC - Monitor Subcarrier.
c. MFI - Monitor Filter and Ident.
d. MBD - Monitor Bearing Counter and Data Acquisition.
e. CTU - Control and Test Unit.
The motherboard mounts eight connectors; these are:
CONNECTOR TYPE USED FOR

XF2 DIN-96 Connects to XN2 on the CTU
Processor Board
XF5 DIN-96 Connects to XN5 on the MBD
module
XF20 DIN-96 Connects to XN2 on the RCMS
Interface Board
XFH DB-25 Connects to rack wiring - control
XFK DB-37 Connects to rack wiring -
monitoring
XM4 DIN-96 Connects to XM4 on MBD
XMJ DB-37 Connects to rack wiring -
monitoring
XML CON4 Power connector
The interconnections between motherboard connectors are listed in Table 2-3, in signal
name order; connector pins not listed are not connected.
2-96
H4A71110 SECTION 2
Table 2-3 Top Bay Motherboard Interconnections

SIGNAL R2 R3 R5 R6 V1 XF2 XF5 XF20 XFH XFK XM4 XMJ XML
(to CTU (to MBD, (to CTU (to rack (to rack (to MBD, (to rack (to rack
Proc, XM5) RCMS, wiring) wiring) XM4) wiring) wiring)
XN2) XN2)
+15V_MON_SUPPLY 1 1 28a, 28b, 2

28c
+15V_MON_VOLTS 24c 37
+15V_VOLTS 24b 18
+24V_SWITCHED 5a 2
+24V_UNSWITCHED 30a, 30b, 1
30c
+24V_VOLTS 22c 16
+5V_VOLTS 24a 36
-15V_MON_SUPPLY 26a, 26b, 3
26c
-15V_MON_VOLTS 23c 17
-15V_VOLTS 23a 35
-40V_VOLTS 22a 15
-45V_VOLTS 22b 34
0V 1 A 1a, 1c, 2a, 16b, 32a, 19a, 21c, 13 8 1a, 1c, 2c, 6,8, 19 4
4c, 5c, 6a, 32b, 32c 25a, 27a, 4a, 5a, 6c,
7a, 9c, 29e, 30c, 7c, 9a,
10c, 12a, 31a. 31c, 10a, 12c,
19a, 21c, 32a, 32c 19c, 21a,
25a, 27a, 25c, 27c,
29c, 30c, 29a, 30a,
31a, 31c, 31 a, 31c,
32a, 32c 32a, 32c
30HZ_AM_LVL 18a 9
30HZ_AM_SQUARE_OUT 2a 21
30HZ_CLOCK 13c 19
30HZ_FM_LVL 18b 28
30HZ_FM_SQUARE_OUT 2c 22
30HZ_SINE_REFERENCE 16c 25
9960HZ_CLOCK 14a 21
BLENDING_FUNCT_LSB 14b 3
BLENDING_FUNCT_USB 15a 4
BUS_SUPPLY_OK 13a 13c
CARRIER_FORWARD_LVL 17a 7
CARRIER_REVERSE_LVL 16a 24
COMMUTATION 14c 22
FREQ_CTRL_LSB_LVL 19a 29
FREQ_CTRL_USBI_LVL 19C 30
INDENT_INH 2 27c 8
IDENT_KEYER_OUTPUT 13b 37
IDENT_LVL 15c 5
IDENT_SIG_15V 1 6
IDENT_SIG_5V 2 2 K 21a
2-97
H4A71110 SECTION 2

XN2) XN2)
LSB_SIDEBAND_LVL 21b 14
MONITOR_ON 30a 9
MONITOR_O_R_ON 30a 22
RACK_ON 29a 21
RECEIVED_CARRIER_LVL 17c 27
REC_IDENT_KEYING_1 22c 19
REC_IDENT_KEYING_2 22c 24
SBAND_SW_DRIVE_EVEN 13a 18
SBAND_SVV_DRIVE_ODD 12b 17
SERIAL_LINK_IN_A 12c 36
SERIAL_LINK_IN_B 12a 35
SERIAL_LINK_OUT_A 11a 15
SERIAL_LINK_OUT_B 11c 16
SUBCARR_LVL 18C 10
THIS_RACK_NOT_TO_ANT 4b 1
TRANSFER_RELAY 29a 10
TX_DRIVE_LVL 17b 26
TX_IMBALANCE_1_LVL 21c 33
TX_IMBALANCE_2_LVL 20a 12
TX_IMBALANCE_COM_LVL 20c 13
TX_INH 2 26c 20
USB_SIDEBAND_LVL 21a 32
XADDR0 12c 12a
XADDR1 11a 11c
XADDR2 11c 11a
XADDR3 10a 10c
XADDR4 8a 8c
XADDR5 8c 8a
XADDR6 6c 6a
XDAT0 14c 14a
XDAT1 14a 14c
XDAT2 15c 15a
XDAT3 15a 15c
XDAT4 16c 16a
XDAT5 16a 16c
XDAT6 17c 17a
XDAT7 17a 17c
XDEN 2c 2a
XDT_R 9a 9c
XINT 3a 3c
XRD 4a 4c
2-98
H4A71110 SECTION 2

XN2) XN2)
XRES 13c 13a

XWR 7c 7a
_30HZ_AM_HIGH_LVL_FLT 10c 33
_30HZ_AM_LOW_LVL_FLT 7c 10
-30HZ_AM_LVL_FLT 8C 30
_30HZ_AM_LVL_FLT_O_R 3c 5
_30HZ_FM_HIGH_LVL_FLT 10b 14
_30HZ_FM_LOW_LVL_FLT 7b 28
_30HZ_FM_LVL_FLT 8a 29
_30HZ_FM_LVL_FLT_O_R 6a 7
_ANTENNA_FLT 8b 11
_ANTENNA_FLT_O_R 5c 25
_BEARING_FLT_O_R 6b 26
_BEARING_FLT_TO_O_R 15b 23
_IDENT_FLT 9b 31
_IDENT_FLT_O_R 3a 4
_MBD_ON 26a 26c
_MCS1 5a 5c
_SIDEBAND_1_FLT 4a 24
_SIDEBAND_2_FLT 4c 6
_SUBCARR_HIGH_LVL_FLT 9c 13
_SUBCARR_LOVV_LVL_FLT 7a 9
_SUBCARR_LVL_FLT 9a 12
_SUBCARR_LVL_FLT_O_R 3b 23
_TX_FWD_PWR_FLT 10a 32
_TX_REV_MR_FLT 6c 27
spare_logic_signal_1 1a 1
spare_logic_signal_2 1c 2
spare_logic_signal_3 2b 3
spare_o_c_output_1 26a 23
spare_o_c_output_2 26c 12
spare_o_c_output_3 27c 25
2-99
H4A71110 SECTION 2
2.3.17 DCC - DC/DC Converter

Drawing 71129-3-09
Components DC/DC Converter 1A71129
Subunits Converter Board 1A71169
The DCC module operates from the 24 volts DC rack voltage and produces DC voltages
of +5, +15, -15, -40 and -45 volts. It contains a DC/DC converter followed by series
voltage regulators which provide the multiple DC supply voltages required by the rack
electronics. The converter features overvoltage and high-current protection.
The DCC module contains two subunits. The first unit is a pulse-width-modulated
converter providing a measure of regulation for its +8, +18, -18, -40 and -45 volts
outputs. The second unit employs three commercial regulators to derive +5, +15 and -15
volts from the +8, +18 and -18 volts supplies respectively.
2.3.17.1 Converter Board

Drawing 71169-2-21
Data
Voltage outputs +8 volts nominal
±18 volts nominal
-40 volts nominal
-45 volts nominal
Total input current 5 amperes nominal
The unit consists of a switching power supply using a regulating pulse-width modulator
N1 in a flyback configuration. The pulse-width modulator generates a train of 50 kHz
pulses with the pulse period determined by R2 and C2. The pulses are passed through a
buffer stage D1 before driving a pair of parallel-connected MOSFET power transistors
V11 and V12 which switch the current flowing in the primary winding of transformer T1.
The voltages on the multiple secondary windings are rectified and filtered to provide
supplies of +8, +18, -18, -40 and -45 volts.
The converter is regulated so as to maintain a DC voltage sample, derived from a
separate secondary winding, at a constant value. A fraction of this sample is applied to
N1:1 from the variable voltage divider R3, RV1 and R1. Internal circuits in N1 reduce the
width of the pulses driving the FET switches as the voltage from the secondary winding
increases, thus maintaining a constant sample voltage.
Overvoltage protection is provided by the circuit containing zener V6 and SCR V5. A
voltage surge will strike the zener, triggering and latching the SCR on and removing the
drive to the MOSFET transistors by clamping the D1 supply rail to ground. The supply is
restored to operation by switching the input supply off and on to allow the SCR to
extinguish and to reset the protection circuit.
Current limit sensing is provided by monitoring the transformer primary circuit current by
means of current transformer T2 which has a turns ratio of 100:1. The voltage resulting
from an excessive primary current will be applied through V8 to V7, causing V7 to turn
on and draw current from pin 9 of the modulator. As the current rises the internal
modulator circuit reduces the pulse duty ratio thereby limiting the output current supplied
by the unit. Voltage overshoot on the positive edges of the drive pulse across the
2-100
H4A71110 SECTION 2
primary winding is controlled by V10, C16 and R24. Isolated transient voltage spikes are
clamped by the zener diodes V13 and V14.
2-101
H4A71110 SECTION 2
Figure 2-22 DCC Converter Switching Waveforms
2-102
H4A71110 SECTION 2
2.3.17.2 Regulator Board

Drawing 71170-3-15
Data ±18 volts
Voltage outputs +5 volts
±15 volts
Voltage adjustment range:
+5 volts supply ±0.5 volts
±15 volts supply ±1.25 volts
Current limits:
+5 volts 3 amperes
+15 volts 3 amperes
-15 volts 1.5 amperes
The three input voltages +8, +18 and -18 volts from the Converter Board are regulated
by separate 3-terminal adjustable voltage regulators N1, N2 and N3. Variable controls
RV1, RV2 and RV3 in the output circuit of each regulator provide a limited range of
voltage adjustment.
2.3.18 CCB - Contactor Assembly

Drawing 71128-3-15
Component Contactor Assembly 1A71128
This module contains the main power switch for the 24 volts transmitter circuits which is
activated by logic control from the CTU. The unit used has three sets of contacts which
are paralleled to reduce contact pitting. Two circuit breakers are provided for protection
of the transmitter and control/monitor 24 volts circuits. Protection is also provided against
reverse connection of the supply.
Data
Logic control level 5 volts
Circuit breaker - transmitter 25 amperes
Circuit breaker - control/monitor 5 amperes
Transistor V2 is actuated by a logic level signal from the controller which closes the
contactor. At the same time a set of normally closed contacts K1/4 open, and resistance
R4 is inserted in series with the actuator coil to provide a low hold current.
Power diodes V4 and V5 provide equipment protection against reverse polarity
connection of the power supply. Resistors R3 and R5 limit the surge current to the
diodes. Diode V3 clamps the reverse voltage generated by the contactor inductance.
Diode V6 protects the transistor against reverse voltages.
2-103
H4A71110 SECTION 2
2.3.19 RLU - Relay Unit

Components Relay Unit 1A/2A716971
Subunits Relay Unit Board 1A71698
The 1A71697 Relay Unit (RLU) allows either one of the two equipment racks, in the dual
DVOR beacon, to be switched to the antenna system. It is the interface unit between the
two racks and the Antenna Distribution Switch (ADS) units; it controls the ADS switching
signals as well as the sideband and carrier RF signals from the racks.
Data
Current drain 1.5 amperes maximum
Switching time operate 15 milliseconds
release 10 milliseconds
Signal switching:
Number of circuits switched 26
Maximum switching current 1 ampere DC
RF switching:
Insertion loss (108-115 MHz) less than 0.4 dB
Isolation greater than 40 dB
VSWR 1.04
The 2A71697 Relay Unit (RLU) is electrically identical to the 1A71697 type, and
performs the same functions. Physically, it uses a different type of relay and has a relay
mounting bracket which permits individual relays to be replaced in the field.
The technical description, alignment and adjustment details for the two types are
identical.
The connections between the RLU and the other items in a dual beacon are shown on
Drawing 71110-3-168, Dual DVOR Station Cabling Diagram.
2.3.19.1 Relay Unit

Drawing 71697-3-12
The RLU contains two sets of relays:
a. Coaxial relays K1 to K5 mounted on the front panel.
b. Signal switching relays, K11 to K17, mounted on the Relay Unit Board
assembly inside the unit.
The coaxial relays are of the changeover type; they are connected to the RF outputs
from each DVOR rack, the antenna system and the dummy loads. Five relays are used
for the carrier and four sideband signals from the rack. The switching is arranged such
that the relays are operated when the No. 1 rack is connected to the antenna system
and released when the No. 2 rack is connected. In either case, the rack not feeding the
antennas is switched through to the dummy loads.
Connection of the switching signals to the RLU is made via the 'D' connectors on the
front panel, which connect to the equipment rack and the antenna distribution units.
Power and control signals for the relays are taken from the No. 1 rack only, the CTU
module determining the required state of the relays.
2-104
H4A71110 SECTION 2
2.3.19.2 Relay Unit Board

Drawing 71698-2-14
The Relay Unit Board assembly contains the signal switching relays, K11 to K17, and
the relay control/driver circuits.
Relays K11 to K17 provide selection of the switch drive signals for the Antenna
Distribution Switch (ADS) units. There are 12 drive signals for each ADS, plus a return
for the -40 volts DC switch bias. These relays are operated when the No. 1 rack is
driving the ADS units.
Control for the relays is taken from the CTU module in the No. 1 rack via connector
XMG:1. A +5 volts signal at this point turns on transistor V7, thus energising all of the
parallel connected relays.
Regulator N1 gives a +15 volts regulated voltage for signalling the state of the relays to
the No. 1 rack via XMG:8 and 9. LEDs H1 and H2 indicate the relay state on the RLU
itself.
Power for the unit is taken from the No. 1 rack via XMG:5 and the reverse protection
diode V1.
2.3.20 MSD - Monitor Signal Divider

Drawing 71160-3-07
Components Monitor Signal Divider 1A71160
The 1A71160 Monitor Signal Divider (MSD) is a passive 2-way power divider for low
level RF signals. It is used only in the dual Doppler DVOR station, to distribute the signal
from the monitor field antenna equally to the two DVOR equipment racks.
Performance Input return loss not less than 20 dB
Data
Insertion loss not exceeding 4 dB
Output balance not exceeding 0.5 dB
Output isolation not less than 20 dB
Nominal input level 100 mV
The signal at XFA is matched to an impedance of 25 ohms by transformer T1. This

intermediate signal is then divided by transformer T2 and fed to each output. Resistor R1
provides isolation between outputs, and gas discharge arrestor F1 gives protection
against input surges.
The MSD also contains surge protection at the monitor antenna input.
2-105
H4A71110 SECTION 2
2.3.21 Voltage Limiter

Drawing 71168-3-26
Components Voltage Limiter 1A71168
The Voltage Limiter module limits the voltage supplied to the RF power amplifiers to 24
volts in order to restrict the power dissipated in these units.
Data
Output voltage range 22 to 24 volts
Maximum continuous current 8 amperes
Maximum source drain voltage drop 0.2 volts at 6 amperes
The circuit consists of a pulse-width modulator N1, a voltage doubler V3, V4, C2 and C3,
a FET power transistor V12 operating as a series-pass element, and a differential
amplifier V6, V7 with a 5 volts reference derived from N1 applied to V6.
The pulse-width modulator N1 produces a pulse train of 200 kHz pulses to the voltage
doubler circuit, which delivers a boost voltage of 36 volts. A sample of this voltage is fed
back to N1:1, which regulates the 36 volts by controlling the pulse width delivered to the
voltage doubler.
When the input supply voltage to V12 rises above 24 volts, it is regulated by the
differential amplifier V6, V7 and by amplifier V12. When the voltage falls below 24 volts
the regulator amplifier applies maximum bias to the gate of the FET, turning it hard on so
that there is only a very small voltage drop across it.
2-106
H4A71110 SECTION 2
2.3.22 External I/O Board

Drawing 72557-1-26
Components External I/O Board 2A72557
The External I/O Board provides a common location for the termination of external wiring
to the CTU (and the Remote Maintenance and Monitoring (RMM) System Navaid
Maintenance Processor (NMP) if it is located in the DVOR rack). It also contains two
power supplies for use with connections to this unit.
Data
Modem power supply 11.8 ±0.6 volts at up to
300 mA
Protected 20 volts power supply Within 1.0 volts of input
voltage at up to 150 mA
Short circuit current 20 ±5 mA
The board contains two 64-way connectors: XN8 is connected via ribbon cable (in the
rack) to the RCMS Interface Board and XN6 is connected also via ribbon cable (in the
rack) to the CTU Processor Board (and the NMP if fitted).
XN8 is connected on the board to terminal blocks XB2 to XB11 which are designed to
terminate the external wiring to the Remote Control and Monitoring System (RCMS).
The 24 volts supply input on XN5 is also connected to XN8 to provide power to the
RCMS Interface Board of the CTU.
XN6 is connected on the board to terminal block XB1 and connectors XN2, XN3, XN4
and XN7. XB1 provides a terminal block connection to the protected 24 V supply. The
remainder of the connections on XB1 are not used on the DVOR. XN2 provides
signalling connections from the 24 volts power supply to the CTU for power supply
status monitoring. XN3 provides connection between a modem and the NMP for the
RMM System - when used. XN4 provides for a connection between the CTU and an
external NMP (that is, when the NMP is not located in the DVOR rack). XN7 provides the
connection between the NMP and the CTU of a second navaid when the NMP is located
in the DVOR rack.
The modem power supply consists of a 3-terminal regulator to produce a 12 volts output
for modems designed to operate from a 12 volts supply. The output is connected, via
selection 0 ohms resistors to five pins of connector XN3.
The protected 24 volts supply is designed to provide a source of nominal 24 volts for use
with the RCMS interface (and other connections) but protected against short circuit. It is
configured to provide a short circuit current of a nominal 20 mA, independent of the input
supply voltage. The maximum current that can be drawn before current limiting occurs is
therefore input voltage dependent, but is at least 150 mA with a minimum input voltage
of 22 volts.
2-107

H4A71110 Vol-1 All

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DOPPLER VOR

TYPE SERIES A71110

Interscan Navigation Systems

REVISION No. AUTHORITY DATE INSERTED INITIALS

© Copyright Interscan Navigation Systems Pty Ltd

REVISION DATE : 4 Aug 98

REVISION AUTHORITY : ECO E1841

Change table heading ‘QTY’ to ‘QTY/CODE’.

Item A6 (Low Pass Filter):

Change identity of COAX CABLE ASSY 71126-4-26 between DRIVER 1A71157

These changes are incorporated in Drawing 71126-3-32 Revision 01.

REVISION DATE : 10 Aug 98

REVISION AUTHORITY : ECO E1681

Add capacitors C51-C54 to code 1031094E.

Replace the existing detail with that shown following.

These changes are incorporated in Drawing 71138-2-25 Revision 02.

VOLUME 1 SECTION 1 BRIEF SPECIFICATION

VOLUME 2 3 ALIGNMENT AND ADJUSTMENT

VOLUME 3 APPENDIX A OPERATING INSTRUCTIONS

VOLUME 4 APPENDIX E TEST EQUIPMENT

VOLUME 6 APPENDIX H DATA SHEETS

VOLUME 6 IS OPTIONAL AND IS SUPPLIED

RADIATION EXPOSURE HAZARD

ELECTRIC SHOCK HAZARD

ACRONYMS AND ABBREVIATIONS

Letter Kind of Item

COMPONENT DESIGNATOR SUFFIXES

One Operator: Two Operators:

CHECK PROGRESS GET HELP

National Heart Foundation of Australia

1. BRIEF SPECIFICATION............................................................................. 1-1

Figure 1-1 DVOR Phase Definition.........................................................................1-3

Table 1-1 Performance Characteristics Summary.....................................................1-5

The following drawings appear at the end of Section 1

Figure 1A Block Diagram – Signal Generation Drawing 71110-1-189

1.1.3 Doppler VOR Function

1.1.4 Generation of Reference and Variable Phase Signals

Figure 1-1 DVOR Phase Definition

1.1.5 Monitor System.

1.2 MECHANICAL DESCRIPTION

1.3 PERFORMANCE SPECIFICATION

Power Supply Voltage +22 to +28 volts

CHARACTERISTIC PARAMETER VALUE/LIMITS

Amplitude modulation Less than 40%

Noise and ripple 0.5 volts peak to peak

CHARACTERISTIC PARAMETER VALUE/LIMITS

2. TECHNICAL DESCRIPTION ...................................................................... 2-1

Figure 2-1 Simulation of Rotating Antennas ...........................................................2-4

2.1.1 Station Description

2.1.2 Antenna Description

2.1.3 Rack Description

A motherboard, type 1A72504, is fitted to the top bay.

2.1.4 Subrack Description

2.1.5 Mechanical Description

2.1.6 Principles of Operation

2.1.6.1 Generation of VOR Signal

2.1.6.2 Antenna Switching and System Timing

Figure 2-3 Antenna Switching System Timing Diagram

Figure 2-4 Sideband Energy Supply to Antennas

2.2 SUBSYSTEM DESCRIPTION DESCRIPTIONS

2.2.1 Carrier Generation and Modulation Subsystem

2.2.2 Sideband Generation Subsystem

2.2.3 Timing Sequence Generation Subsystem